VHDL IMPLEMENTATION OF FLOATING POINT MULTIPLIER BASED ON VEDIC MULTIPLICATION TECHNIQUE

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1 VHDL IMPLEMENTATION OF FLOATING POINT MULTIPLIER BASED ON VEDIC MULTIPLICATION TECHNIQUE PRAGATI SACHAN M.Tech (VLSI) Scholar, Electronics and communication Engineering, Jayoti Vidyapeeth Women s University Jaipur, Rajasthan, India, sachanpragati.kgi@gmail.com ABSTRACT In th paper, IEEE floating point format was a standard format used in all processing elements since Binary floating point numbers one of the basic functions used in digital signal processing (DSP) application. In that work VHDL implementation of Floating Point Multiplier using ancient Vedic mathematics presented. The idea for designing the multiplier unit adopted from ancient Indian mathematics "Vedas". The Urdhvatriyakbhyam sutra will be used for the of Mantsa. The underflow and over flow cases will be handled. The inputs the multiplier in 32 bit format. The multiplier designed in VHDL or VERILOG and simulated using Modelsim. Key words: Vedic Mathematics, Urdhva triyakbhyam sutra, Floating Point multiplier, FPGA. 1. INTRODUCTION 1.1 FLOATING POINT MULTIPLIER FOR IEEE FORMATE Multiplication of two no s using Urdhva Tiryakbhyam sutra performed by vertically and crosswe, crosswe means diagonal and vertically means straight above and taking their sum. The feature any multi bit can be reduced down single bit and addition using th method. On account of these formulas, the carry propagation from LSB MSB reduces due one step generation of partial product, the efficient use of Vedic method in order multiply two floating point numbers.th work presents an implementation of a floating point multiplier that supports the IEEE binary interchange format. Based on the dcussion made above it very clear that a multiplier a very important element in any processor design and a processor spends considerable amount of time in performing and generally the most area consuming. Hence, optimizing the speed and area of the multiplier a major design sue. An improvement in speed by using new techniques can greatly improve system performance. In the next stage of the project the design will be designed using VHDL or VERILOG and will be simulated using Modelsim Simular. The design will be synthesized using Xilinx ISE 12.1 ol. A test bench will be used generate the stimulus and the multiplier operation be verified.the over flow and under flow flags are incorporated in the design in order show the over flow and under flow cases. The theory states that the efficient use of Vedic method in order multiply two floating point numbers. That the hardware requirement reduced, thereby reducing the power consumption. The power consumption upon reducing affectively may not comprome delay so much. Multiplication of the floating point numbers described in IEEE 754 single precion valid. Floating point multiplier done using VHDL.Implementation in VHDL(VHSIC Hardware Description Language) used because it allow direct implementation on the hardware while in other language they have convert them in HDL then only can be implemented on the hardware. In floating point, adding of the two numbers done with the help of various types of adders but for some extra shifting needed. Th floating point handles various conditions like overflow, underflow, normalization, rounding. In th work they use IEEE rounding method for perform the rounding of the resulted number.th work focuses only on single precion normalized binary interchange format targeted for Xilinx Spartan 3 FPGA based on VHDL. The multiplier was verified against Xilinx floating point multiplier core. It handles the overflow and underflow cases. Rounding not implemented give more precion when using the multiplier in a Multiply and Accumulate (MAC) unit. 1.2 VEDIC MULTIPLIER FOR BINARY NUMBERS The design of high speed and area efficient Binary Number Multiplier often called Binary Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics i.e.urdhva Tiryagbhyam Sutra. Urdhva Tiryagbhyam Sutra the Vedic method for which strikes a difference in the actual process of itself, giving minimum delay for of all types of numbers, either small or large. The work has proved the efficiency of Binary Number Multiplier designed using Urdhva Tiryagbhyam Sutra where process enables parallel generation of intermediate products and eliminates unwanted steps. Further, the Verilog HDL coding of Urdhva Tiryagbhyam Sutra for 23x23 bits and their implementation in Xilinx Synthes Tool on Spartan 3E kit have been done. The propagation time for the proposed architecture ns.the work then extends Vedic multiplier using "Nikhilam Sutra" technique. The International Journal of Science, Engineering and Technology

2 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8 8 Vedic multiplier modules; one 16 bit carry save adders, and two 17 bit full adder stages. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The Vedic multiplier coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. Th multiplier implemented on Spartan 2 FPGA device XC2S30 5pq208. The performance evaluation results in terms of speed and device utilization are compared with earlier multiplier architecture.vedic Mathematics has a unique technique of calculations based on 16 Sutras. Th work presents study on high speed 8x8 bit Vedic multiplier architecture which quite different from the Conventional method of like add and shift. Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 8x8 bits and their FPGA implementation by Xilinx Synthes Tool on Spartan 3 kit have been done and output has been dplayed on LED s of Spartan 3 kit.the work then extends Vedic multiplier using "Nikhilam Sutra" technique. The Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8 8 Vedic multiplier modules; one 16 bit carry save adders, and two 17 bit full adder stages. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The Vedic multiplier coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. Th multiplier implemented on Spartan 2 FPGA device XC2S30 5pq208.The 16x16 Vedic multiplier using Nikhilam Sutra found be better than 16x16 Vedic multiplier using Urdhva Tiryakbhyam Sutra in terms of speed when magnitude of both operands are more than half of their maximum values. 1.3 VEDIC MATHEMATICS DIFFERENT METHODOLOGIES FOR MULTIPLICATION A new 4 bit adder proposed which when used in multiplier, reduces its delay. Th multiplier can be used in applications such as digital signal processing, encryption and decryption algorithms in crypgraphy, and in other logical computations. Th design simulated using VHDL.A 4 bit adder has been implemented in 4X4 multiplier using Vedic sutras. It seen that the speed of the proposed multiplier higher than that of normal array multiplier i.e. the delay has been drastically reduced. 4X44 multiplier can be extended 8 bit and higher order multipliers. Th multiplier can be used in applications such as digital signal processing, encryption and decryption algorithms in crypgraphy. The proposed design can further be implemented at transr level and verified.the Vedic Multiplier tested by using BIST (Built in Self Test) and it found Fault free. The results are compared with the Booth's Multiplier in terms of time delay and power. The high speed processorr requires high speed and low power multipliers and the Vedic Multiplication technique were very much suitable for th purpose.high speed low power Vedic multiplier by comparing th design with a conventional Array Multiplier and Booth Multiplier. These multipliers are implemented using VHDL In order get the power report and delay report the multipliers are synthesized using Xilinx ISE ol and Spartan 2E FPGA used. 2. METHODOLOGY 2..1 VEDIC MULTIPLIER DSP applications essentially require the of binary floating point numbers. The IEEE 754 standard provides the format for representation of Binary Floating point numbers. The Binary Floating point numbers are represented in Single and Double formats. The Single const of 32 bits and the Double const of 64 bits. The formats are composed of 3 fields; Sign, Exponent and Mantsa. The Figure 3.1 showss the structure of Single and Double formats of IEEE 754 standard. In case of Single, the Mantsaa represented in 23 bits and 1 bit added the MSB for normalization, Exponent represented in 8 bits whichh biased 127, actually the Exponent represented in excess 127 bit format and MSB of Single reserved for Sign bit. When the sign bit 1 that means the number negativee and when the sign bit 0 that means the number positive. In 64 bits format the Mantsa represented in 52 bits, the Exponent represented in 11 bits which biased 1023 and the MSB of Double reserved for sign bit Urdhva TriyaKbhyam (Vertically & Crosswe) Urdhva tiryakbhyam Sutra a general formula applicable all cases of. It literally means Vertically and Crosswe. To illustrate th scheme, let us consider the of two decimal numbers ( ). The conventional methods already know us will require 16 s and 15 additions. An alternative method of using Urdhva tiryakbhyam Sutra shown in Fig The numbers be multiplied are written on two consecutive sides of the square as shown in the figure. The square dividedd in rows and columns where each row/column corresponds one of the digit of either a multiplier or a multiplicand. Thus, each digit of the multiplier has a small box common a digit of the multiplicand. These small boxes are partitioned in two halves by the crosswe lines. Each digit of the multiplier then independently multiplied with every digit of the multiplicand and the two digit product written in the common box. All the digits lying on a crosswe dotted line are added the previous carry. The least significant digit of the obtained number acts as the result digit and the rest as the carry for the next step. Carry for the first step (i.e., the dotted line on the extreme right side) taken be zero FLOATING POINT MULTIPLICATION International Journal of Science, Engineering and Technology

3 The multiplier for the floating point numbers represented in IEEE 754 format can be divided in four different units: x24 and B = x23. IEEE representations of operands are Mantsa Calculation Unit Exponent Calculation Unit Sign Calculation Unit Control Unit The standard format for representation of floating point number ( 1) S 2E (b0 b1b2 bp 1) The biased exponent e =E+127, and the fraction f = b1b2 bp 1. The Mantsa Calculation Unit requires a 24 bit multiplier if 32 bit single IEEE 754 format considered. In th work we propose the efficient use of Vedic Multiplication Technique for th 24 bit multiplier. The Exponent Calculation Unit implemented in th paper using 8 BIT Ripple Carry Adder.The advantages of ripple carry adder in addition its implementation ease are low area and simple layout. The Control Unit raes the flag when NaN, Infinity, zero, underflow and overflow cases are detected. The control unit raes appropriate flag accordingly when the cases occurs. The various cases and its constituent flags are: If e = 255 and f 0, then NaN If e = 255 and f = 0, then Infinity If 0 < e < 255, then Number ( 1) s 2e 127(1 f) If e = 0 and f 0, then ( 1)s 2 126(0 f) (demoralized numbers) If e = 0 and f = 0, then zero. Here, MSB of the 32 bit operand shows the sign bit, the exponents are expressed in excess 127 bit and the mantsa represented in 23 bit. Sign of the result calculated by XORing sign bits of both the operands A and B. In th case sign bit obtained after XORing 1. Exponents of A and B are added get the resultant exponent. Addition of exponent done using 8 bit ripple carry adder Figure 3.3. After addition the result again biased excess 127 bit Code. For th purpose 127 subtracted from the result. Two s complement subtraction using addition incorporated for th purpose. If ER the final resultant exponent then, ER = EA + EB 127 Where EA and EB are the exponent parts of operands A and B respectively. In th case ER = Mantsa done using the 24 bit Vedic Multiplier. The mantsa expressed in 23 bit which normalized 24 BIT by adding a 1 at MSB. The normalized 24 bit mantsas are Multiplication of two, 24 bit mantsa done using the Vedic Multiplier. In th case 48 bit result obtained after the of mantsa Now setting up three intermediate results the final result (normalizing the mantsa by eliminating most significant 1) we obtained : Th result deduced as Figure 2.2 shows the proposed architecture for the Floating point multiplier. Consider the of two floating point numbers A and B, where A = 19.0 and B = 9.5. The normalized binary representation are A= AxB = 19.0 x 9.5 = = x International Journal of Science, Engineering and Technology

4 = ( ) = ( 180.5) 10 ) 2 block, 8x8 bit block, 16x16bit block and then finally 32 x 32 bit Multiplier as shown infigure 3.5 has been made. 2.3 PROPOSED DESIGN The performancee of Mantsaa calculation Unit dominates overall performance of the Floating Point Multiplier. Th unit requires unsigned multiplier for of 24x24 BITs. The Vedic Multiplication technique chosen for the implementation of th unit. Th technique gives proming result in terms of speed and power [6].The Vedic system based on 16 Vedic sutras or aphorms, which describes natural ways of solving a whole range of mathematical problems. Out of these 16 Vedic Sutras the Urdhva triyakbhyam sutra suitable for th purpose. In th method the partial products are generated simultaneously which itself reduces delay and makes th method fast. The method for of two, 3 BITs number shown Figure 3.4. Consider the numbers A and B where A = a2a1a0 and B = b2b1b0. The LSB of A multiplied with the LSB of B: s0=a0b0; Then a0 multiplied with b1, and b0 multiplied with a1 and the results are added gether as: c1s1=a1b0+a0b1; Heree c1 carry and s1 sum. Next step add c1 with the results of a0 with b2, a1 with b1 and a2 with b0. c2s2=c1+a2b0+a1b1 + a0b2; The design starts first with Multiplier design that 2x2 bit multiplier as shown in figure 3.6. Here, Urdhva Tiryakbhyam Sutra or Vertically and Crosswe Algorithm for has been effectively used develop digital multiplier architecture. Th algorithm quite different from the traditional method of, which add and shift the partial products. To scale the multiplier further, Karatsuba Ofman algorithm can be employed. Karatsuba Ofman algorithm considered as one of the fastest ways multiply long integers. It based on the divide and conquer strategy. A of 2n digit integer reduced two n digit s, one (n+1) digit, two n digit subtractions, two left shift operations, two n digit additions and two 2n digit additions. Next step add c3 with the results of a1 with b2 and a2 with b1. c3s3=c2+a1b2+a2b1; Similarly the last step c4s4=c3+a2b2; Now the final result of of A and B c4s4s3s2s1s0. Fig 3.6: Hardware Realization of 2x2 block The proposed s were implemented using two different coding techniques viz., conventional shift & add and Vedic techniquee for 4, 8, 16, and 32 bit multipliers. It evident that there a considerable increase in speed of the Vedic architecture. The number of LUTs and slices required for the Vedic Multiplier less and due which the power consumption reduced. Also the repetitive and regular structure of the multiplier makes it easier design. And the time required for computing less than the other techniques. For Multiplier, first the basic blocks, that are the 2x2 bitmultipliers have been made and then, using these blocks, 4x4block has been made by adding the partial products using carrysave adders and then using th 4x4 An Overflow or Underflow case occurs when the result Exponent higher than the 8 BIT or lower than 8 BIT respectively. Overflow may occur during the addition of two Exponents which can be compensated at the time of subtracting the bias from the exponent result. When overflow occurs the overflow flag goes up. The under International Journal of Science, Engineering and Technology

5 flow can occur after the subtraction of bias from the exponent, it the case when the number goes below 0 and th situation can be handled by adding 1 at the time of normalization. When the underflow case occur the under flow flag goes high. 3. SIMULATION RESULTS We have taken two inputs A and B as a multiplier and multiplicand these are floating point signed value we are perform multiplier using Vedic Algorithm between these inputs and will be sred in other output port which we have taken as Z all operations are performing on positive edge of clock. For case I we take value of A and value of B Here A unsigned floating pint number and B Signed Floating Point Number. Now we have convert value of A binary format after normalize we get x2^7 then we have convert it in IEE 32 floating point format then we get then convert it in hexadecimal format we get 0x Now we have convert value of B binary format after normalize we get 1.001x2^1 then we have convert it in IEE 32 floating point format then we get then convert it in hexadecimal format we get 0xC After using Vedic Multiplier we get 0xC396D200 the value of th hexadecimal no fig 3.1 shows the simulation result of th data. Fig 3.1: Simulation Result of Case I For case II we take value of A 14.5 and value of B Here A signed floating pint number and B also a signed Floating Point Number. Now we have convert value of A binary format after normalize we get x2^3 then we have convert it in IEE 32 floating point format then we get then convert it in hexadecimal format we get 0xC Now we have convert value of B binary format after normalize we get 1.1x2^ 2 then we have convert it in IEE 32 floating point format then we get then convert it in hexadecimal format we get 0xBEC After using Vedic Multiplier we get 0x40AE0000 the value of th hexadecimal no fig 3.2 shows the simulation result of th data. International Journal of Science, Engineering and Technology

6 Fig 3.2: Simulation Result of Case III For case III we take value of A 7.5 and value of B 15.5 Here A unsigned floating pint number and B also a unsigned Floating Point Number. Now we have convert value of A binary format after normalize we get 1.111x2^2 then we have convert it in IEE 32 floating point format then we get then convert it in hexadecimal format we get 0x40F Now we have convert value of B binary format after normalize we get x2^3 then we have convert it in IEE 32 floating point format then we get then convert it in hexadecimal format we get 0x After using Vedic Multiplier we get 0x42E8800 the value of th hexadecimal no fig 3.3 shows the simulation result of th data. Fig 3.3: Simulation Result of Case III International Journal of Science, Engineering and Technology

7 3.1 SYNTHESIS RESULTS Fig 3.4 shows the RTL of our code, fig 3.5 shows the internal RTL and fig 3.6 shows the devices utilized in our work. Here we attach the synthes report of our code. Fig 3.4: Main RTL Fig 3.5: Internal RTL Fig 3.6: Device Utilization 4. FUTURE EXPECTS The time taken for operation reduced by employing the Vedic algorithms. Here Vedic multiplier architecture proposed for further reduction in time. Depending on the inputs, the better sutra selected by the architecture itself. Future work can also further extend increase the more speed and reduce area. It can be extended have more mathematical operations like ad der/subtracr, divider and exponential functions.an improvement in speed by using new techniques can greatly improve system performance. 5. CONCLUSION Th paper named VHDL Implementation of Floating Point Multiplier based on Vedic Multiplication Technique underok by the studentt of M.Tech (VERI LARGE SCALE INTEGERATION) FOURTH SEMESTER International Journal of Science, Engineering and Technology

8 under the guidance and support of our teacher.the paper shows the efficient use of Vedic method in order multiply two floating point numbers. The lesser number of LUTs verifies that the hardware requirement reduced, thereby reducing the power consumption. REFERENCES 1. Manoranjan Pradhan et al, Speed Comparon of 16x16 Vedic Multipliers International Journal of Computer Applications ( ) Volume 21 No.6, May Brian Hickman et al, A Parallel IEEE P754 Decimal Floating Point Multiplier University of Wconsin Madon Dept. of Electrical and Computer Engineering Madon, WI IEEE , IEEE Standard for Floating Point Arithmetic, Rekha K James, Poulose K Jacob, Sreela Sasi, Decimal Floating Point Multiplication using RPS Algorithm, IJCA Proceedings on International Conference on VLSI, Communications and Instrumentation (ICVCI): Brian Hickmann, Andrew Krioukov, and Michael Schulte, Mark Erle, A Parallel IEEE 754 Decimal Floating Point Multiplier, In 25 th International Conference on Computer Design ICCD, Oct International Journal of Science, Engineering and Technology