AN511. PLD Replacement INTRODUCTION IMPLEMENTING A PLA. Microchip Technology, Inc.

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1 AN5 PLD Replacement Author: INTRODUCTION Sumit itra icrochip Technology, Inc. PIC6C5X microcontrollers are ideal for implementing low cost combinational and sequential logic circuits that traditionally have been implemented using either numerous TTL gates or using programmable logic chips such as PLAs or EPLDs. The PIC6C5X is a family of high-performance 8-bit microcontrollers from icrochip Technology Inc. It employs a Harvard architecture, (i.e., has a separate data bus [8-bit] and program bus [2-bit]). All instructions are single word and execute in one cycle except for program branches. The instruction cycle time is 2 ns at 2 Hz. PIC6C5X microcontrollers are ideal for PLD-type applications because: Very low cost Few external components required Fully programmable. PIC6C5X icrocontrollers are offered as One Time Programmable (OTP) EPRO devices. Available off the shelf from distributors Calibration in software for improved measurement accuracy Power savings using PIC6C5X s Sleep mode. PIC6C5X s output pins have large, current source/sink capability to drive LED s directly. IPLEENTING A PLA To implement a generic combinational logic function, we can simply emulate an AND-OR PLA in software. This requires the logic outputs to be described as sums of products. To describe our algorithm, we will use a simple 8-input, 8-output PLA with 24 product terms (Figure ). We will further use the truth table in Figure 2 as the PLA function being implemented. In this example, only four inputs (A3:A) are used and the other four inputs (A7:A4) are don t care. On the output side, seven output pins (Y6:Y) are used and Y7 is unused. To implement this PLA, the logic inputs A,A,...,A7 can be connected to PORTB pins RB,RB,...,RB7 respectively. The logic outputs Y,Y,...,Y7 will appear on PORTC pins RC,RC,...,RC7 respectively. PORTB is configured as input and PORTC will be configured as output. To evaluate each product term one XOR (exclusive.or.) and one.and. operation will be required. For example, to determine product term P3 = A3.A2.A.A, the expression to evaluate is: (A7:A.XOR. xxxxb).and. b). The constant with which.xor. is performed will be referred to as P3_x in our discussion. P3_x = xxxxb will ensure that if A3:A = b, then the least significant 4-bits of the result will be b. The.AND. constant, referred to here as P3_a (Product term 3,.AND. constant) basically eliminates the don t care inputs (here A7:A4) by masking them. Therefore, if the result of the.xor.-.and. operation is zero then P3 = else P3 =. Once the Product terms are evaluated they are stored in four product registers Preg_ to Preg_3. To determine an output term: Y = P + P2 + P3 + P5 + P6 + P7 + P8 + P9 + P + P2 + P3 + P4 we need to evaluate the following expression: (Preg_a.AND. OR_a).OR. (Preg_b.AND. OR_b).OR. (Preg_c.AND. OR_c) In our case the constant values to implement Y are as follows: OR_a = P7 P6 P5 P3 P2 P OR_b = OR_c = For a larger number of inputs, outputs, or product terms, the evaluation will be more complex but follows the same principle. Appendix A shows the assembly code to implement this 8 input x 8 output x 24 Product PLA. This example optimizes speed as well as program memory requirements. Appendix B shows a slightly different implementation (only the EVAL_Y ACRO is different) that optimizes program memory usage over speed. Table shows the time and resources required to implement different size PLAs. 997 icrochip Technology Inc. DS5E-page

2 AN5 DS5E-page icrochip Technology Inc. FIGURE : A SIPLE PLA FIGURE 2: BINARY TO 7-SEGENT CONVERSION EXAPLE RB7 A7 RB6 A6 RB5 A5 RB4 A4 RB3 A3 RB2 A2 RB A RB A RC Y RC Y RC2 Y2 RC3 Y3 RC4 Y4 RC5 Y5 RC6 Y6 RC7 Y7 P23 P22 P2 P2 P3 P2 P P AND Plane OR Plane A3 SEG A2 A A SEG SEG2 SEG3 SEG4 SEG5 SEG6 LSB BINARY INPUT 7-SEG OUTPUT BINARY 7-SEGENT CONVERTER (COON CATHODE) Truth Table: Product Terms HEX A B C D E F A3 A2 A A Y Y Y2 Y3 Y4 Y5 Y6 P = A3, A2, A, A P P2 P3 P4 P5 P6 P7 P8 P9 P P P2 P3 P4 P5 = A3, A2, A, A

3 AN5 SPEED/RESPONSE TIE The worst case response time of a PLA implemented in this fashion can be calculated as follows. First, we define TD = time required to execute the PLA program assuming the worst case program branches are taken. Then the maximum propagation delay time from input change to valid output = 2TD. This is because if an input changes just after the program reads the input port, its effect will not show up until the program completes the current execution cycle, re-reads the input and recalculates the output. This is shown in Figure 3. There are ways to improve the delay time, such as sample inputs several times throughout the PLA program and if an input change is sensed, return to the beginning rather than execute the rest of the evaluation code. A Table Lookup ethod for Small PLA Implementation If the number of inputs is small (8 or less) then a simple table lookup method can be used to implement the PLA. This will improve execution time to around 5 µs (@ 8 Hz input clock). The following code implements the Binary Coded Decimal (BCD) to 7-segment conversion (Figure 2) using this technique. EXAPLE : LOOKUP TABLE PLA ETHOHD begin movlw ffh ; tris 6 ;Port_b = input clrw ; tris 7 ;Port_c = output pla 88 movf Port_b,w ;Read input andlw fh ;ask off bits 7:4 call op_tbl ; movwf Port_c ;Write output goto pla88 ; op_tbl addwf pc ;Computed jump for ;table lookup retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; retlw b ; TABLE : EXECUTION TIE AND RESOURCES NECESSARY FOR DIFFERENT SIZE PLAS Number of Inputs Including FDBK Number of Outputs Including FDBK and O/E Control Number of Products Number of RA Locations Required NRA Number of emory Locations Required NRO Number of Instruction Cycles to Execute PLA NCYC 2 Hz to Execute PLA µs Time Efficient µs Code Efficient µs Time Efficient µs Code Efficient µs Time Efficient µs Code Efficient µs Time Efficient µs Code Efficient If NI = Number of inputs Then, NIW + NPW : Time Efficient NIW = NI Number of input words, NIW = 8 NIW + NOW + NPW + 2: Code Efficient NP = Number of products 8 + NPW + NOW + NP [2 + 3NIW] + No 4: Time Efficient NPW = NP Number of product words, i.e. NPW = NPW + NOW + NP [2 + 3NIW] + No [NPW + 3]: Code Efficient NO = Number of output words 8 + NPW + NOW + NP[2 + 3NIW] + No [2NPW 4]: Time Efficient NOW = NO Number of output words, i.e., NOW = NPW + NOW + NP [2 + 3NIW] + 5N [NPW + ]: Code Efficient 997 icrochip Technology Inc. DS5E-page 3

4 AN5 FIGURE 3: PLA PROGRA FLOW Read Inputs Read Inputs Evaulate Product Terms TD No Has Input Changed? TD Evaulate Output Terms Yes Evaluate Product Terms TD2 TD Write to Output Ports A very simple PLA evaluation flow. Yes Has Input Changed? No Input_a Input_b Evaluate Output Terms TD3 Output_x TD TPROP 2TD TD New valid Output In this simple implementation, the maximum propagation delay from input change to output change is 2TD. Write Output to Ports ore complex program flow can be used, such as this one to reduce TPROP. In this example TD < TPROP < TD + TD3 FIGURE 4: ASYNCHRONOUS STATE ACHINE IPLEENTING AN ASYNCHRONOUS STATE ACHINE Inputs A A An Combinational Logic F F Fp Y Y Ym Outputs The concept can be easily extended to implement sequential logic (i.e., a state machine). Figure 4 shows a state machine with n inputs (A:An), m outputs (Y:Ym) and p states that feedback as inputs to the PLA (F:Fp). In a PIC6C5X the states will be stored as bits in RA location. Input will now mean input from a port as well as from the feedback registers. Figure 5 shows an example PLA with eight inputs A,A,..,A7 that are connected to PORTB pins RB,RB,..,RB7. This example PLA has a total of 24 outputs of which eight are actual outputs, another eight are output enable control for the outputs and the other eight are feedbacks (or states). The PLA shown here, therefore, in essence implements an asynchronous state machine (i.e., there is no system clock). DS5E-page icrochip Technology Inc.

5 AN5 FIGURE 5: A A A2 A3 A4 A5 A6 A7 EXAPLE OF A LARGER PLA IPLEENTATION RB RB RB2 RB3 RB4 RB5 RB6 RB7 F F F2 F3 F4 F5 F6 F7 Internal RA Locations P3 P2 P P P63 P62 P6 Y Y Y2 Y3 Y4 Y5 Y6 Y7 RC RC RC2 RC3 RC4 RC5 RC6 RC7 OR7 OR6 OR5 OR4 OR3 OR2 OR TRIS register for PORTC OR This example shows 6 inputs (including feedback), 64 product terms and 24 outputs including feedback and O/E control. This example demonstrates that O/E control is easily implementable using PIC6C5X s bi-directional ports with Tri-State control. Tri-State is a registered trademark of National Semiconductor Corporation 997 icrochip Technology Inc. DS5E-page-5

6 AN5 FIGURE 6: SYNCHRONOUS STATE ACHINE IPLEENTATION A Y Clock =? Yes Ai Combinational Logic Yi No Evaluate PLA outputs Fs Q D Fm Output Y - Yi Fs Q CK D Fm Output Fm - Fpm Fps CK Fpm Q D CK CLOCK Clock =? No Fmaster Fslave Yes Flowchart for implementing synchronous state machine. Clock is input to an I/O port. Fmaster and Fslave are RA locations that store state variables Fm,... Fpm and Fs,... Fps respectively. Clock A:Ai Fs:Fps Fm:Fpm Y:Yi IPLEENTING A SYNCHRONOUS STATE ACHINE In a synchronous system (Figure 6) usually all inputs are stable at the falling (or rising) edge of the system clock. The state machine samples inputs on the falling edge, then evaluates state and output information. The state outputs are latched by the rising edge of the clock before feeding them back to the input (so that they are stable at the falling edge of the clock). To implement such a state machine, the system clock will have to be polled by an input pin. When a falling edge is detected, the PLA evaluation procedure will be invoked to compute outputs and write them to output pins. The PLA procedure will also determine the new state variables, Fm, Fm,...,Fpm and store them in RA. The program will then wait until a rising edge on the clock input is detected and copy the master state variables (Fm,..,Fpm) to slave state variables (Fs,Fs,..,Fps). This step emulates the feedback flip-flops. SUARY In conclusion, the PIC6C5X can implement a generic PLA equation and provide a quick, low cost solution where system operation speed is not critical. DS5E-page icrochip Technology Inc.

7 AN5 Please check the icrochip BBS for the latest version of the source code. icrochip s Worldwide Web Address: Bulletin Board Support: CHIPBBS using CompuServe (CompuServe membership not required). APPENDIX A: PLA IPLEENTATION: TIE EFFICIENT APPROACH PAS.4 Released PLAA.AS :28:25 PAGE LOC OBJECT CODE VALUE LINE SOURCE TEXT LIST P = 6C54, n = 66 2 ; 3 ;******************************************************************* 4 ; plaa.asm : 5 ; This procedure implements a simple AND-OR PLA with: 6 ; 7 ; 8 inputs := A7 A6 A5 A4 A3 A2 A A 8 ; 24 product terms := P23 P22... P 9 ; 8 outputs := Y7 Y6 Y5 Y4 Y3 Y2 Y Y ; ; The eight inputs are assumed to be connected to PORT RB such that 2 ; RB = A, RB = A,..., RB7 = A7. 3 ; The outputs are programmed to appear on port RC such that 4 ; RC = Y, RC = Y,..., RC7 = Y7. 5 ; 6 ; This implementation optimizes both speed & program memory usage 7 ; 8 ; Program: PLAA.AS 9 ; Revision Date: 2 ; Compatibility with PASWIN.4 2 ; 22 ;******************************************************************** 23 ; 24 ; define RA locations used: 25 ; C 26 input equ d 2 ; RA location 2 holds input D 27 Y_reg equ d 3 ; holds output result 28 E 29 Preg_a equ d 4 ; Product terms P to P7. Preg_a<> = P F 3 Preg_b equ d 5 ; Product terms P8 to P5. Preg_b<> = P8 3 Preg_c equ d 6 ; Product terms P6 to P23. Preg_c<> = P ; define some constants and file addresses: 34 ; 35 bit equ ; 36 bit equ ; 2 37 bit2 equ 2 ; 3 38 bit3 equ 3 ; 4 39 bit4 equ 4 ; 5 4 bit5 equ 5 ; 6 4 bit6 equ 6 ; 7 42 bit7 equ 7 ; 43 ; 3 44 status equ 3 ; 6 45 port_b equ 6 ; 7 46 port_c equ 7 ; 47 ; 48 ; define the AND plane programming variables: 49 ; 5 P_x equ b ; F 5 P_a equ b ; 52 P_x equ b ; F 53 P_a equ b ; 2 54 P2_x equ b ; 997 icrochip Technology Inc. DS5E-page-7

8 AN5 F 55 P2_a equ b ; 3 56 P3_x equ b ; F 57 P3_a equ b ; 4 58 P4_x equ b ; F 59 P4_a equ b ; 5 6 P5_x equ b ; F 6 P5_a equ b ; 6 62 P6_x equ b ; F 63 P6_a equ b ; 7 64 P7_x equ b ; F 65 P7_a equ b ; 8 66 P8_x equ b ; F 67 P8_a equ b ; 9 68 P9_x equ b ; F 69 P9_a equ b ; A 7 P_x equ b ; F 7 P_a equ b ; B 72 P_x equ b ; F 73 P_a equ b ; C 74 P2_x equ b ; F 75 P2_a equ b ; D 76 P3_x equ b ; F 77 P3_a equ b ; E 78 P4_x equ b ; F 79 P4_a equ b ; F 8 P5_x equ b ; F 8 P5_a equ b ; 82 P6_x equ b ; 83 P6_a equ b ; 84 P7_x equ b ; 85 P7_a equ b ; 86 P8_x equ b ; 87 P8_a equ b ; 88 P9_x equ b ; 89 P9_a equ b ; 9 P2_x equ b ; 9 P2_a equ b ; 92 P2_x equ b ; 93 P2_a equ b ; 94 P22_x equ b ; 95 P22_a equ b ; 96 P23_x equ b ; 97 P23_a equ b ; ; define OR plane programming variables: ED OR_a equ b ; for output Y D7 2 OR_b equ b ; 3 OR_c equ b ; 9F 4 OR_a equ b ; for output Y 27 5 OR_b equ b ; 6 OR_c equ b ; FB 7 OR_a2 equ b ; for output Y2 2F 8 OR_b2 equ b ; 9 OR_c2 equ b ; 6D OR_a3 equ b ; for output Y3 79 OR_b3 equ b ; 2 OR_c3 equ b ; 45 3 OR_a4 equ b ; for output Y4 FD 4 OR_b4 equ b ; 5 OR_c4 equ b ; 7 6 OR_a5 equ b ; for output Y5 DF 7 OR_b5 equ b ; 8 OR_c5 equ b ; 7C 9 OR_a6 equ b ; for output Y6 EF 2 OR_b6 equ b ; DS5E-page icrochip Technology Inc.

9 AN5 2 OR_c6 equ b ; 22 OR_a7 equ b ; for output Y7 23 OR_b7 equ b ; 24 OR_c7 equ b ; FF 27 org ffh ; FF A 28 begin goto main ; 29 3 org h ; 3 ; define macro to evaluate product (AND) term: 32 ; main call pla88 ; A 34 goto main ; 35 ; EVAL_P ACRO Preg_x,bit_n,Pn_x,Pn_a 38 movf input,w ; 39 xorlw Pn_x ; 4 andlw Pn_a ; 4 btfsc status,bit2 ; skip if zero bit not set 42 bsf Preg_x,bit_n ; product term = 43 END ; define macro to load OR term constants: 47 ; 48 EVAL_Y ACRO OR_an,OR_bn,OR_cn,bit_n 49 LOCAL SETBIT ; 5 movf Preg_a,W ; 5 andlw OR_an ; 52 btfss status,bit2 ; 53 goto SETBIT ; movf Preg_b,W ; 56 andlw OR_bn ; 57 btfss status,bit2 ; 58 goto SETBIT ; 59 6 movf Preg_c,W ; 6 andlw OR_cn ; 62 btfss status,bit2 ; 63 SETBIT bsf Y_reg,bit_n ; 64 END ; now the PLA evaluation procedure: 67 ; 2 CFF 68 pla88 movlw ffh ; tris 6 ; port_b = input movf port_b,w ; read input 5 2C 7 movwf input ; store input in a register 6 6E 72 clrf Preg_a ; clear Product register a 7 6F 73 clrf Preg_b ; clear Product register b clrf Preg_c ; clear Product register c 9 6D 75 clrf Y_reg ; clear output register and_pl EVAL_P Preg_a,bit,P_x,P_a A 2C movf input,w ; B F xorlw P_x ; C EF andlw P_a ; D 643 btfsc status,bit2 ; skip if zero bit not set E 5E bsf Preg_a,bit ; product term = 78 EVAL_P Preg_a,bit,P_x,P_a F 2C movf input,w ; F xorlw P_x ; EF andlw P_a ; 997 icrochip Technology Inc. DS5E-page-9

10 AN btfsc status,bit2 ; skip if zero bit not set 3 52E bsf Preg_a,bit ; product term = 79 EVAL_P Preg_a,bit2,P2_x,P2_a 4 2C movf input,w ; 5 F2 xorlw P2_x ; 6 EF andlw P2_a ; btfsc status,bit2 ; skip if zero bit not set 8 54E bsf Preg_a,bit2 ; product term = 8 EVAL_P Preg_a,bit3,P3_x,P3_a 9 2C movf input,w ; A F3 xorlw P3_x ; B EF andlw P3_a ; C 643 btfsc status,bit2 ; skip if zero bit not set D 56E bsf Preg_a,bit3 ; product term = 8 EVAL_P Preg_a,bit4,P4_x,P4_a E 2C movf input,w ; F F4 xorlw P4_x ; 2 EF andlw P4_a ; btfsc status,bit2 ; skip if zero bit not set 22 58E bsf Preg_a,bit4 ; product term = 82 EVAL_P Preg_a,bit5,P5_x,P5_a 23 2C movf input,w ; 24 F5 xorlw P5_x ; 25 EF andlw P5_a ; btfsc status,bit2 ; skip if zero bit not set 27 5AE bsf Preg_a,bit5 ; product term = 83 EVAL_P Preg_a,bit6,P6_x,P6_a 28 2C movf input,w ; 29 F6 xorlw P6_x ; 2A EF andlw P6_a ; 2B 643 btfsc status,bit2 ; skip if zero bit not set 2C 5CE bsf Preg_a,bit6 ; product term = 84 EVAL_P Preg_a,bit7,P7_x,P7_a 2D 2C movf input,w ; 2E F7 xorlw P7_x ; 2F EF andlw P7_a ; btfsc status,bit2 ; skip if zero bit not set 3 5EE bsf Preg_a,bit7 ; product term = EVAL_P Preg_b,bit,P8_x,P8_a 32 2C movf input,w ; 33 F8 xorlw P8_x ; 34 EF andlw P8_a ; btfsc status,bit2 ; skip if zero bit not set 36 5F bsf Preg_b,bit ; product term = 87 EVAL_P Preg_b,bit,P9_x,P9_a 37 2C movf input,w ; 38 F9 xorlw P9_x ; 39 EF andlw P9_a ; 3A 643 btfsc status,bit2 ; skip if zero bit not set 3B 52F bsf Preg_b,bit ; product term = 88 EVAL_P Preg_b,bit2,P_x,P_a 3C 2C movf input,w ; 3D FA xorlw P_x ; 3E EF andlw P_a ; 3F 643 btfsc status,bit2 ; skip if zero bit not set 4 54F bsf Preg_b,bit2 ; product term = 89 EVAL_P Preg_b,bit3,P_x,P_a 4 2C movf input,w ; 42 FB xorlw P_x ; 43 EF andlw P_a ; btfsc status,bit2 ; skip if zero bit not set 45 56F bsf Preg_b,bit3 ; product term = 9 EVAL_P Preg_b,bit4,P2_x,P2_a 46 2C movf input,w ; 47 FC xorlw P2_x ; DS5E-page 997 icrochip Technology Inc.

11 AN5 48 EF andlw P2_a ; btfsc status,bit2 ; skip if zero bit not set 4A 58F bsf Preg_b,bit4 ; product term = 9 EVAL_P Preg_b,bit5,P3_x,P3_a 4B 2C movf input,w ; 4C FD xorlw P3_x ; 4D EF andlw P3_a ; 4E 643 btfsc status,bit2 ; skip if zero bit not set 4F 5AF bsf Preg_b,bit5 ; product term = 92 EVAL_P Preg_b,bit6,P4_x,P4_a 5 2C movf input,w ; 5 FE xorlw P4_x ; 52 EF andlw P4_a ; btfsc status,bit2 ; skip if zero bit not set 54 5CF bsf Preg_b,bit6 ; product term = 93 EVAL_P Preg_b,bit7,P5_x,P5_a 55 2C movf input,w ; 56 FF xorlw P5_x ; 57 EF andlw P5_a ; btfsc status,bit2 ; skip if zero bit not set 59 5EF bsf Preg_b,bit7 ; product term = EVAL_P Preg_c,bit,P6_x,P6_a 5A 2C movf input,w ; 5B F xorlw P6_x ; 5C E andlw P6_a ; 5D 643 btfsc status,bit2 ; skip if zero bit not set 5E 5 bsf Preg_c,bit ; product term = 96 EVAL_P Preg_c,bit,P7_x,P7_a 5F 2C movf input,w ; 6 F xorlw P7_x ; 6 E andlw P7_a ; btfsc status,bit2 ; skip if zero bit not set bsf Preg_c,bit ; product term = 97 EVAL_P Preg_c,bit2,P8_x,P8_a 64 2C movf input,w ; 65 F xorlw P8_x ; 66 E andlw P8_a ; btfsc status,bit2 ; skip if zero bit not set bsf Preg_c,bit2 ; product term = 98 EVAL_P Preg_c,bit3,P9_x,P9_a 69 2C movf input,w ; 6A F xorlw P9_x ; 6B E andlw P9_a ; 6C 643 btfsc status,bit2 ; skip if zero bit not set 6D 57 bsf Preg_c,bit3 ; product term = 99 EVAL_P Preg_c,bit4,P2_x,P2_a 6E 2C movf input,w ; 6F F xorlw P2_x ; 7 E andlw P2_a ; btfsc status,bit2 ; skip if zero bit not set bsf Preg_c,bit4 ; product term = 2 EVAL_P Preg_c,bit5,P2_x,P2_a 73 2C movf input,w ; 74 F xorlw P2_x ; 75 E andlw P2_a ; btfsc status,bit2 ; skip if zero bit not set 77 5B bsf Preg_c,bit5 ; product term = 2 EVAL_P Preg_c,bit6,P22_x,P22_a 78 2C movf input,w ; 79 F xorlw P22_x ; 7A E andlw P22_a ; 7B 643 btfsc status,bit2 ; skip if zero bit not set 7C 5D bsf Preg_c,bit6 ; product term = 22 EVAL_P Preg_c,bit7,P23_x,P23_a 7D 2C movf input,w ; 997 icrochip Technology Inc. DS5E-page-

12 AN5 7E F xorlw P23_x ; 7F E andlw P23_a ; btfsc status,bit2 ; skip if zero bit not set 8 5F bsf Preg_c,bit7 ; product term = or_pl EVAL_Y OR_a,OR_b,OR_c,bit LOCAL SETBIT ; 82 2E movf Preg_a,W ; 83 EED andlw OR_a ; btfss status,bit2 ; 85 A8D goto SETBIT ; 86 2F movf Preg_b,W ; 87 ED7 andlw OR_b ; btfss status,bit2 ; 89 A8D goto SETBIT ; 8A 2 movf Preg_c,W ; 8B E andlw OR_c ; 8C 743 btfss status,bit2 ; 8D 5D SETBIT bsf Y_reg,bit ; 25 EVAL_Y OR_a,OR_b,OR_c,bit LOCAL SETBIT ; 8E 2E movf Preg_a,W ; 8F E9F andlw OR_a ; btfss status,bit2 ; 9 A99 goto SETBIT ; 92 2F movf Preg_b,W ; 93 E27 andlw OR_b ; btfss status,bit2 ; 95 A99 goto SETBIT ; 96 2 movf Preg_c,W ; 97 E andlw OR_c ; btfss status,bit2 ; 99 52D SETBIT bsf Y_reg,bit ; 26 EVAL_Y OR_a2,OR_b2,OR_c2,bit2 LOCAL SETBIT ; 9A 2E movf Preg_a,W ; 9B EFB andlw OR_a2 ; 9C 743 btfss status,bit2 ; 9D AA5 goto SETBIT ; 9E 2F movf Preg_b,W ; 9F E2F andlw OR_b2 ; A 743 btfss status,bit2 ; A AA5 goto SETBIT ; A2 2 movf Preg_c,W ; A3 E andlw OR_c2 ; A4 743 btfss status,bit2 ; A5 54D SETBIT bsf Y_reg,bit2 ; 27 EVAL_Y OR_a3,OR_b3,OR_c3,bit3 LOCAL SETBIT ; A6 2E movf Preg_a,W ; A7 E6D andlw OR_a3 ; A8 743 btfss status,bit2 ; A9 AB goto SETBIT ; AA 2F movf Preg_b,W ; AB E79 andlw OR_b3 ; AC 743 btfss status,bit2 ; AD AB goto SETBIT ; AE 2 movf Preg_c,W ; DS5E-page icrochip Technology Inc.

13 AN5 AF E andlw OR_c3 ; B 743 btfss status,bit2 ; B 56D SETBIT bsf Y_reg,bit3 ; 28 EVAL_Y OR_a4,OR_b4,OR_c4,bit4 LOCAL SETBIT ; B2 2E movf Preg_a,W ; B3 E45 andlw OR_a4 ; B4 743 btfss status,bit2 ; B5 ABD goto SETBIT ; B6 2F movf Preg_b,W ; B7 EFD andlw OR_b4 ; B8 743 btfss status,bit2 ; B9 ABD goto SETBIT ; BA 2 movf Preg_c,W ; BB E andlw OR_c4 ; BC 743 btfss status,bit2 ; BD 58D SETBIT bsf Y_reg,bit4 ; 29 EVAL_Y OR_a5,OR_b5,OR_c5,bit5 LOCAL SETBIT ; BE 2E movf Preg_a,W ; BF E7 andlw OR_a5 ; C 743 btfss status,bit2 ; C AC9 goto SETBIT ; Preg_b,W ; C3 EDF andlw OR_b5 ; C4 743 btfss status,bit2 ; C5 AC9 goto SETBIT ; C6 2 movf Preg_c,W ; C7 E andlw OR_c5 ; C8 743 btfss status,bit2 ; C9 5AD SETBIT bsf Y_reg,bit5 ; 2 EVAL_Y OR_a6,OR_b6,OR_c6,bit6 LOCAL SETBIT ; CA 2E movf Preg_a,W ; CB E7C andlw OR_a6 ; CC 743 btfss status,bit2 ; CD AD5 goto SETBIT ; CE 2F movf Preg_b,W ; CF EEF andlw OR_b6 ; D 743 btfss status,bit2 ; D AD5 goto SETBIT ; D2 2 movf Preg_c,W ; D3 E andlw OR_c6 ; D4 743 btfss status,bit2 ; D5 5CD SETBIT bsf Y_reg,bit6 ; 2 EVAL_Y OR_a7,OR_b7,OR_c7,bit7 LOCAL SETBIT ; D6 2E movf Preg_a,W ; D7 E andlw OR_a7 ; D8 743 btfss status,bit2 ; D9 AE goto SETBIT ; DA 2F movf Preg_b,W ; DB E andlw OR_b7 ; DC 743 btfss status,bit2 ; DD AE goto SETBIT ; DE 2 movf Preg_c,W ; DF E andlw OR_c7 ; E 743 btfss status,bit2 ; 997 icrochip Technology Inc. DS5E-page-3

14 AN5 E 5ED SETBIT bsf Y_reg,bit7 ; ; Y_reg now contains 8 output values: E wr_out clrw ; E tris 7 ; port_c = output E4 2D 26 movf Y_reg,W ; E movwf port_c ; Y_reg -> port_c E retlw ; 29 E7 22 ZZZ nop END EORY USAGE AP ( X = Used, - = Unused) : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 4 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 8 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX C : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXX C : X All other memory blocks unused. Program emory Words Used: 233 Program emory Words Free: 279 Errors : Warnings : reported, suppressed essages : reported, suppressed DS5E-page icrochip Technology Inc.

15 AN5 Please check the icrochip BBS for the latest version of the source code. icrochip s Worldwide Web Address: Bulletin Board Support: CHIPBBS using CompuServe (CompuServe membership not required). APPENDIX B: PLA IPLEENTATION: CODE EFFICIENT APPROACH PAS.4 Released PLAB.AS :29:6 PAGE LOC OBJECT CODE VALUE LINE SOURCE TEXT LIST P = 6C54, n = 66 2 ; 3 ;******************************************************************* 4 ; plab.asm : 5 ; This procedure implements a simple AND-OR PLA with: 6 ; 7 ; 8 inputs := A7 A6 A5 A4 A3 A2 A A 8 ; 24 product terms := P23 P22... P 9 ; 8 outputs := Y7 Y6 Y5 Y4 Y3 Y2 Y Y ; ; The eight inputs are assumed to be connected to PORT RB such that 2 ; RB = A, RB = A,..., RB7 = A7. 3 ; The outputs are programmed to appear on port RC such that 4 ; RC = Y, RC = Y,..., RC7 = Y7. 5 ; 6 ; This implementation optimizes program memory usage over 7 ; speed 8 ; 9 ; Program: PLAB.AS 2 ; Revision Date: 2 ; Compatibility with PASWIN.4 22 ; 23 ;******************************************************************* 24 ; 25 ; define RA locations used: 26 ; C 27 input equ d 2 ; RA location 2 holds input D 28 Y_reg equ d 3 ; holds output result 29 E 3 Preg_a equ d 4 ; Product terms P to P7. Preg_a<> = P F 3 Preg_b equ d 5 ; Product terms P8 to P5. Preg_b<> = P8 32 Preg_c equ d 6 ; Product terms P6 to P23. Preg_c<> = P Pn_x equ d 8 ; 3 35 Pn_a equ d 9 ; 4 36 OR_a equ d 2 ; 5 37 OR_b equ d 2 ; 6 38 OR_c equ d 22 ; 39 4 ; define some constants and file addresses: 4 ; 42 bit equ ; 43 bit equ ; 2 44 bit2 equ 2 ; 3 45 bit3 equ 3 ; 4 46 bit4 equ 4 ; 5 47 bit5 equ 5 ; 6 48 bit6 equ 6 ; 7 49 bit7 equ 7 ; 5 ; 3 5 status equ ; 6 52 port_b equ 6 ; 7 53 port_c equ 7 ; 54 ; 55 ; define the AND plane programming variables: 997 icrochip Technology Inc. DS5E-page-5

16 AN5 56 ; 57 P_x equ b ; F 58 P_a equ b ; 59 P_x equ b ; F 6 P_a equ b ; 2 6 P2_x equ b ; F 62 P2_a equ b ; 3 63 P3_x equ b ; F 64 P3_a equ b ; 4 65 P4_x equ b ; F 66 P4_a equ b ; 5 67 P5_x equ b ; F 68 P5_a equ b ; 6 69 P6_x equ b ; F 7 P6_a equ b ; 7 7 P7_x equ b ; F 72 P7_a equ b ; 8 73 P8_x equ b ; F 74 P8_a equ b ; 9 75 P9_x equ b ; F 76 P9_a equ b ; A 77 P_x equ b ; F 78 P_a equ b ; B 79 P_x equ b ; F 8 P_a equ b ; C 8 P2_x equ b ; F 82 P2_a equ b ; D 83 P3_x equ b ; F 84 P3_a equ b ; E 85 P4_x equ b ; F 86 P4_a equ b ; F 87 P5_x equ b ; F 88 P5_a equ b ; 89 P6_x equ b ; 9 P6_a equ b ; 9 P7_x equ b ; 92 P7_a equ b ; 93 P8_x equ b ; 94 P8_a equ b ; 95 P9_x equ b ; 96 P9_a equ b ; 97 P2_x equ b ; 98 P2_a equ b ; 99 P2_x equ b ; P2_a equ b ; P22_x equ b ; 2 P22_a equ b ; 3 P23_x equ b ; 4 P23_a equ b ; 5 6 ; define OR plane programming variables: 7 ED 8 OR_a equ b ; for output Y D7 9 OR_b equ b ; OR_c equ b ; 9F OR_a equ b ; for output Y 27 2 OR_b equ b ; 3 OR_c equ b ; FB 4 OR_a2 equ b ; for output Y2 2F 5 OR_b2 equ b ; 6 OR_c2 equ b ; 6D 7 OR_a3 equ b ; for output Y OR_b3 equ b ; 9 OR_c3 equ b ; 45 2 OR_a4 equ b ; for output Y4 FD 2 OR_b4 equ b ; DS5E-page icrochip Technology Inc.

17 AN5 22 OR_c4 equ b ; 7 23 OR_a5 equ b ; for output Y5 DF 24 OR_b5 equ b ; 25 OR_c5 equ b ; 7C 26 OR_a6 equ b ; for output Y6 EF 27 OR_b6 equ b ; 28 OR_c6 equ b ; 29 OR_a7 equ b ; for output Y7 3 OR_b7 equ b ; 3 OR_c7 equ b ; FF 34 org ffh ; FF A 35 begin goto main ; org h ; 38 ; define macro to evaluate product (AND) term: 39 ; 9B 4 main call pla88 ; A 4 goto main ; 42 ; EVAL_P ACRO Preg_x,bit_n,Pn_x,Pn_a 45 movf input,w ; 46 xorlw Pn_x ; 47 andlw Pn_a ; 48 btfsc status,bit2 ; skip if zero bit not set 49 bsf Preg_x,bit_n ; product term = 5 END ; define macro to load OR term constants: 54 ; 55 EVAL_Y ACRO OR_an,OR_bn,OR_cn,bit_n 56 movlw OR_an ; load constants 57 movwf OR_a ; 58 movlw OR_bn ; 59 movwf OR_b ; 6 movlw OR_cn ; 6 movwf OR_c ; 62 call EVAL ; 63 btfss status,bit2 ; 64 bsf Y_reg,bit_n ; 65 END ; define procedure to evaluate output (OR) term: 68 ; 2 2E 69 EVAL movf Preg_a,W ; andwf OR_a, ; 7 4 2F 72 movf Preg_b,W ; andwf OR_b, ; movf Preg_c,W ; andwf OR_c,W ; iorwf OR_a,W ; iorwf OR_b,W ; A 8 8 retlw ; W = implies Yn = 8 82 ; now the PLA evaluation procedure: 83 ; B CFF 84 pla88 movlw ffh ; C 6 85 tris 6 ; port_b = input D movf port_b,w ; read input E 2C 87 movwf input ; store input in a register 997 icrochip Technology Inc. DS5E-page-7

18 AN5 F 6E 88 clrf Preg_a ; clear Product register a 6F 89 clrf Preg_b ; clear Product register b 7 9 clrf Preg_c ; clear Product register c 2 6D 9 clrf Y_reg ; clear output register and_pl EVAL_P Preg_a,bit,P_x,P_a 3 2C movf input,w ; 4 F xorlw P_x ; 5 EF andlw P_a ; btfsc status,bit2 ; skip if zero bit not set 7 5E bsf Preg_a,bit ; product term = 94 EVAL_P Preg_a,bit,P_x,P_a 8 2C movf input,w ; 9 F xorlw P_x ; A EF andlw P_a ; B 643 btfsc status,bit2 ; skip if zero bit not set C 52E bsf Preg_a,bit ; product term = 95 EVAL_P Preg_a,bit2,P2_x,P2_a D 2C movf input,w ; E F2 xorlw P2_x ; F EF andlw P2_a ; btfsc status,bit2 ; skip if zero bit not set 2 54E bsf Preg_a,bit2 ; product term = 96 EVAL_P Preg_a,bit3,P3_x,P3_a 22 2C movf input,w ; 23 F3 xorlw P3_x ; 24 EF andlw P3_a ; btfsc status,bit2 ; skip if zero bit not set 26 56E bsf Preg_a,bit3 ; product term = 97 EVAL_P Preg_a,bit4,P4_x,P4_a 27 2C movf input,w ; 28 F4 xorlw P4_x ; 29 EF andlw P4_a ; 2A 643 btfsc status,bit2 ; skip if zero bit not set 2B 58E bsf Preg_a,bit4 ; product term = 98 EVAL_P Preg_a,bit5,P5_x,P5_a 2C 2C movf input,w ; 2D F5 xorlw P5_x ; 2E EF andlw P5_a ; 2F 643 btfsc status,bit2 ; skip if zero bit not set 3 5AE bsf Preg_a,bit5 ; product term = 99 EVAL_P Preg_a,bit6,P6_x,P6_a 3 2C movf input,w ; 32 F6 xorlw P6_x ; 33 EF andlw P6_a ; btfsc status,bit2 ; skip if zero bit not set 35 5CE bsf Preg_a,bit6 ; product term = 2 EVAL_P Preg_a,bit7,P7_x,P7_a 36 2C movf input,w ; 37 F7 xorlw P7_x ; 38 EF andlw P7_a ; btfsc status,bit2 ; skip if zero bit not set 3A 5EE bsf Preg_a,bit7 ; product term = 2 22 EVAL_P Preg_b,bit,P8_x,P8_a 3B 2C movf input,w ; 3C F8 xorlw P8_x ; 3D EF andlw P8_a ; 3E 643 btfsc status,bit2 ; skip if zero bit not set 3F 5F bsf Preg_b,bit ; product term = 23 EVAL_P Preg_b,bit,P9_x,P9_a 4 2C movf input,w ; 4 F9 xorlw P9_x ; 42 EF andlw P9_a ; btfsc status,bit2 ; skip if zero bit not set 44 52F bsf Preg_b,bit ; product term = DS5E-page icrochip Technology Inc.

19 AN5 24 EVAL_P Preg_b,bit2,P_x,P_a 45 2C movf input,w ; 46 FA xorlw P_x ; 47 EF andlw P_a ; btfsc status,bit2 ; skip if zero bit not set 49 54F bsf Preg_b,bit2 ; product term = 25 EVAL_P Preg_b,bit3,P_x,P_a 4A 2C movf input,w ; 4B FB xorlw P_x ; 4C EF andlw P_a ; 4D 643 btfsc status,bit2 ; skip if zero bit not set 4E 56F bsf Preg_b,bit3 ; product term = 26 EVAL_P Preg_b,bit4,P2_x,P2_a 4F 2C movf input,w ; 5 FC xorlw P2_x ; 5 EF andlw P2_a ; btfsc status,bit2 ; skip if zero bit not set 53 58F bsf Preg_b,bit4 ; product term = 27 EVAL_P Preg_b,bit5,P3_x,P3_a 54 2C movf input,w ; 55 FD xorlw P3_x ; 56 EF andlw P3_a ; btfsc status,bit2 ; skip if zero bit not set 58 5AF bsf Preg_b,bit5 ; product term = 28 EVAL_P Preg_b,bit6,P4_x,P4_a 59 2C movf input,w ; 5A FE xorlw P4_x ; 5B EF andlw P4_a ; 5C 643 btfsc status,bit2 ; skip if zero bit not set 5D 5CF bsf Preg_b,bit6 ; product term = 29 EVAL_P Preg_b,bit7,P5_x,P5_a 5E 2C movf input,w ; 5F FF xorlw P5_x ; 6 EF andlw P5_a ; btfsc status,bit2 ; skip if zero bit not set 62 5EF bsf Preg_b,bit7 ; product term = 2 2 EVAL_P Preg_c,bit,P6_x,P6_a 63 2C movf input,w ; 64 F xorlw P6_x ; 65 E andlw P6_a ; btfsc status,bit2 ; skip if zero bit not set 67 5 bsf Preg_c,bit ; product term = 22 EVAL_P Preg_c,bit,P7_x,P7_a 68 2C movf input,w ; 69 F xorlw P7_x ; 6A E andlw P7_a ; 6B 643 btfsc status,bit2 ; skip if zero bit not set 6C 53 bsf Preg_c,bit ; product term = 23 EVAL_P Preg_c,bit2,P8_x,P8_a 6D 2C movf input,w ; 6E F xorlw P8_x ; 6F E andlw P8_a ; btfsc status,bit2 ; skip if zero bit not set 7 55 bsf Preg_c,bit2 ; product term = 24 EVAL_P Preg_c,bit3,P9_x,P9_a 72 2C movf input,w ; 73 F xorlw P9_x ; 74 E andlw P9_a ; btfsc status,bit2 ; skip if zero bit not set bsf Preg_c,bit3 ; product term = 25 EVAL_P Preg_c,bit4,P2_x,P2_a 77 2C movf input,w ; 78 F xorlw P2_x ; 79 E andlw P2_a ; 7A 643 btfsc status,bit2 ; skip if zero bit not set 997 icrochip Technology Inc. DS5E-page-9

20 AN5 7B 59 bsf Preg_c,bit4 ; product term = 26 EVAL_P Preg_c,bit5,P2_x,P2_a 7C 2C movf input,w ; 7D F xorlw P2_x ; 7E E andlw P2_a ; 7F 643 btfsc status,bit2 ; skip if zero bit not set 8 5B bsf Preg_c,bit5 ; product term = 27 EVAL_P Preg_c,bit6,P22_x,P22_a 8 2C movf input,w ; 82 F xorlw P22_x ; 83 E andlw P22_a ; btfsc status,bit2 ; skip if zero bit not set 85 5D bsf Preg_c,bit6 ; product term = 28 EVAL_P Preg_c,bit7,P23_x,P23_a 86 2C movf input,w ; 87 F xorlw P23_x ; 88 E andlw P23_a ; btfsc status,bit2 ; skip if zero bit not set 8A 5F bsf Preg_c,bit7 ; product term = or_pl EVAL_Y OR_a,OR_b,OR_c,bit 8B CED movlw OR_a ; load constants 8C 34 movwf OR_a ; 8D CD7 movlw OR_b ; 8E 35 movwf OR_b ; 8F C movlw OR_c ; 9 36 movwf OR_c ; 9 92 call EVAL ; btfss status,bit2 ; 93 5D bsf Y_reg,bit ; 22 EVAL_Y OR_a,OR_b,OR_c,bit 94 C9F movlw OR_a ; load constants movwf OR_a ; 96 C27 movlw OR_b ; movwf OR_b ; 98 C movlw OR_c ; movwf OR_c ; 9A 92 call EVAL ; 9B 743 btfss status,bit2 ; 9C 52D bsf Y_reg,bit ; 222 EVAL_Y OR_a2,OR_b2,OR_c2,bit2 9D CFB movlw OR_a2 ; load constants 9E 34 movwf OR_a ; 9F C2F movlw OR_b2 ; A 35 movwf OR_b ; A C movlw OR_c2 ; A2 36 movwf OR_c ; A3 92 call EVAL ; A4 743 btfss status,bit2 ; A5 54D bsf Y_reg,bit2 ; 223 EVAL_Y OR_a3,OR_b3,OR_c3,bit3 A6 C6D movlw OR_a3 ; load constants A7 34 movwf OR_a ; A8 C79 movlw OR_b3 ; A9 35 movwf OR_b ; AA C movlw OR_c3 ; AB 36 movwf OR_c ; AC 92 call EVAL ; AD 743 btfss status,bit2 ; AE 56D bsf Y_reg,bit3 ; 224 EVAL_Y OR_a4,OR_b4,OR_c4,bit4 AF C45 movlw OR_a4 ; load constants B 34 movwf OR_a ; B CFD movlw OR_b4 ; B2 35 movwf OR_b ; B3 C movlw OR_c4 ; DS5E-page icrochip Technology Inc.

21 AN5 B4 36 movwf OR_c ; B5 92 call EVAL ; B6 743 btfss status,bit2 ; B7 58D bsf Y_reg,bit4 ; 225 EVAL_Y OR_a5,OR_b5,OR_c5,bit5 B8 C7 movlw OR_a5 ; load constants B9 34 movwf OR_a ; BA CDF movlw OR_b5 ; BB 35 movwf OR_b ; BC C movlw OR_c5 ; BD 36 movwf OR_c ; BE 92 call EVAL ; BF 743 btfss status,bit2 ; C 5AD bsf Y_reg,bit5 ; 226 EVAL_Y OR_a6,OR_b6,OR_c6,bit6 C C7C movlw OR_a6 ; load constants C2 34 movwf OR_a ; C3 CEF movlw OR_b6 ; C4 35 movwf OR_b ; C5 C movlw OR_c6 ; C6 36 movwf OR_c ; C7 92 call EVAL ; C8 743 btfss status,bit2 ; C9 5CD bsf Y_reg,bit6 ; 227 EVAL_Y OR_a7,OR_b7,OR_c7,bit7 CA C movlw OR_a7 ; load constants CB 34 movwf OR_a ; CC C movlw OR_b7 ; CD 35 movwf OR_b ; CE C movlw OR_c7 ; CF 36 movwf OR_c ; D 92 call EVAL ; D 743 btfss status,bit2 ; D2 5ED bsf Y_reg,bit7 ; ; Y_reg now contains 8 output values: D wr_out clrw ; D tris 7 ; port_c = output D5 2D 232 movf Y_reg,W ; D movwf port_c ; Y_reg -> port_c D retlw ; 235 D8 236 ZZZ nop END EORY USAGE AP ( X = Used, - = Unused) : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 4 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 8 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX C : XXXXXXXXXXXXXXXX XXXXXXXXX C : X All other memory blocks unused. Program emory Words Used: 28 Program emory Words Free: 294 Errors : Warnings : reported, suppressed essages : reported, suppressed 997 icrochip Technology Inc. DS5E-page-2

22 Note the following details of the code protection feature on PICmicro CUs. The PICmicro family meets the specifications contained in the icrochip Data Sheet. icrochip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. icrochip is willing to work with the customer who is concerned about the integrity of their code. Neither icrochip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at icrochip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by icrochip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of icrochip s products as critical components in life support systems is not authorized except with express written approval by icrochip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The icrochip name and logo, the icrochip logo, FilterLab, KEELOQ, microid, PLAB, PIC, PICmicro, PICASTER, PICSTART, PRO ATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of icrochip Technology Incorporated in the U.S.A. and other countries. dspic, ECONOONITOR, FanSense, FlexRO, fuzzylab, In-Circuit Serial Programming, ICSP, ICEPIC, microport, igratable emory, PAS, PLIB, PLINK, PSI, XDEV, PICC, PICDE, PICDE.net, rfpic, Select ode and Total Endurance are trademarks of icrochip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of icrochip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 22, icrochip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. icrochip received QS-9 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 999. The Company s quality system processes and procedures are QS-9 compliant for its PICmicro 8-bit CUs, KEELOQ code hopping devices, Serial EEPROs and microperipheral products. In addition, icrochip s quality system for the design and manufacture of development systems is ISO 9 certified. 22 icrochip Technology Inc.

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