DESIGN OF FAULT SECURE ENCODER FOR MEMORY APPLICATIONS IN SOC TECHNOLOGY

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1 DESIGN OF FAULT SECURE ENCODER FOR MEMORY APPLICATIONS IN SOC TECHNOLOGY K.Maheshwari M.Tech VLSI, Aurora scientific technological and research academy, Bandlaguda, Hyderabad. k.sandeep kumar Asst.prof, Department of ECE, Aurora scientific technological and research academy Bandlaguda, Hyderabad Abstract: This paper describes a novel architecture of fault tolerant Memory. In today s memory applications protecting the memory from soft errors as become challengable.in order to protect against the soft errors such as transient errors we propose a design known as fault secure technology. This technology will be used to design an encoder and decoder circuits which are placed around the memory block. The key codes which will be using in the above technology are Euclidean Geometry Low- Density Parity Check (EGLDPC)CODES. Floor planning of fault secure encoder, placing everything on the chip without overlapping. Using these 3 methods floor planning, placement and routing we can get the floor planning in soc technology. keywords: Encoder, decoder, fault tolerant memory. I.INTRODUCTION: The memory system is most important part of operating system for data storage application. Memory cells have been protected from soft errors for more than a decade, due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors and must also be protected. A new approach is introduced to design fault-secure encoder and decoder circuitry for memory designs. Hamming codes are often used in today s memory systems to correct single error and detect double errors in any memory word. In these memory architectures, only errors in the memory words are tolerated and there is no preparation to tolerate errors in the supporting logic (i.e. encoder and corrector). However combinational logic has already started showing susceptibility to soft errors, and therefore the encoder and corrector units will no longer be immune from the transient faults. Therefore, protecting the memory systems support logic implementation is more important. A fault tolerant memory system is proposed that tolerates multiple errors in each memory word as well as multiple errors in the encoder and corrector units. The fault-tolerant memory system is illustrated using Euclidean Geometry codes due to their well-suited characteristics for this application. II.SYSTEM OVERVIEW: In this section, our memory system design that can tolerate errors in any part of the system, including the storage unit and supporting logic(encoder and corrector circuits) using the fault-secure detector. This design is feasible when the following two fundamental properties are satisfied: 1) Any single error in the encoder or corrector circuitry can at most corrupt a single code word (i.e, no single error can propagate to multiple). 2) There is a fault secure detector that can detect any combination of errors in the retreived code word. This fault secure detector can verify the Correctness of the encoder and also corrector operation. III.EUCLIDEAN GEOMETRY CODE: A class of error-correcting codes (ECCs) is identified that guarantees the existence of a simple fault-tolerant detector design. This class satisfies a new, restricted definition for ECCs which guarantees that the ECC codeword has an appropriate redundancy structure such that it can detect multiple errors occurring in both the stored codeword in memory and the surrounding circuitries. This type of error-correcting codes are known as fault-secure detector capable ECCs (FSD-ECC). The parity-check Matrix of an FSD-ECC has a particular structure that the decoder circuit, generated from the parity-check Matrix, is Fault-Secure

2 Euclidean Geometry codes are also called EG- LDPC codes based on the fact that they are lowdensity parity-check (LDPC) codes [1]. LDPC codes have a limited number of 1 s in each row and column of the matrix; this limit guarantees limited complexity in their associated detectors and correctors making them fast and light weight [2]. Let EG be a Euclidean Geometry with n points and J lines. EG is a finite geometry that is shown to have the following fundamental structural properties: 1) Every line consists of ρ points; 2) Any two points are connected by exactly one line; 3) Every point is intersected by γ lines; 4) Two lines intersect in exactly one point or they are parallel; i.e., they do not intersect. Let H be a J n binary matrix, whose rows and columns corresponds to lines and points in an EG Euclidean geometry, respectively, where h i, j = 1 if and only if the ith line of EG contains the jth point of EG, and h i, j = 0 otherwise. A row in H displays the points on a specific line of EG and have weight ρ.a column in H displays the lines that intersect at a specific point in EG and have weight γ. The rows of H are called the incidence vectors of the lines in EG, and the columns of H are called the intersecting vectors of the points in EG. Therefore, H is the incidence matrix of the lines in EG over the points in EG. It is shown in [1] that H is a LDPC matrix, and therefore the code is an LDPC code. A special subclass of EG-LDPC codes, type-i 2-D EG-LDPC is considered. The type-i 2-D EG-LDPC has the following parameters [5] for any positive integer t 2 : t t Information bits, k = Length, = 2 2 t n 1 Minimum distance, d min = 2 t + 1 t Row weight of the parity-check matrix, ρ = 2 t Column weight of the parity-check matrix, γ = 2 IV DESIGN STRUCTURE: In this section we provide the design structure of encoder,corrector,detector units of fault tolerant memory system. An overview of the proposed reliable memory system is shown in Fig.4 1 and is described. The information bits are fed into the encoder to encode the information vector, and the fault secure detector of the encoder verifies the validity of the encoded vector. If the detector detects any error, the encoding operation must be redone to generate the correct codeword. The codeword is then stored in the memory. During memory access operation, the stored code words will be accessed from the memory unit. Code words are susceptible to transient faults while they are stored in the memory; therefore a corrector unit is designed to correct potential errors in the retrieved code words. In the proposed design (Fig. 4.1) all the memory words pass through the corrector and any potential error in the memory words will be corrected. Similar to the encoder unit, a fault-secure detector monitors the operation of the corrector unit. Fig 1 Fault-tolerant Memory Architecture with Parallel Corrector A. ENCODER: An n-bit codeword c, which encodes a k -bit information vector i is generated by multiplying the k -bit information vector with a k n bit generator matrix G ; i.e., c = i. G.(4.2.1). EG-LDPC codes are not systematic and the information bits must be decoded from the encoded vector, which is not desirable for our fault-tolerant approach due to the further complication and delay that it adds to the operation. However, these codes are cyclic codes [1]. The procedure presented in [1] is 490

3 used to convert the cyclic generator matrices to systematic generator matrices for all the EG-LDPC codes under consideration. Consider the (15, 7, 5) EG-LDPC code has the generator polynomial: 1 + X 4 + X 6 + X 7 + X 8 (I) By comparing the two eqs(i)&(ii) and the equation the following values are obtained. go = 1,g1 = 0,g2 = 0,g3 = 0,g4 = 1,g5 = 0,g6 = 1,g7 = 1,g8 = 1 The generator matrix in cyclic format will be as below Any (n, k) cyclic code the generator polynomial can be represented as G(x) = g 0 + g 1 X + g 2 X 2 + g 3 X g n-k X n-k.(ii) Its corresponding generator matrix will b simply an inner product of information vector and a column of X, from G = [ I : X ]. Fig shows the encoder circuit to compute the parity bits of the (15, 7, 5) EG-LDPC code. In this figure i = ( i0, i1, i2,... i6 ) is the information vector and will be copied to ( c 0,... c6) bits of the encoded vector, c, and the rest of encoded vector, the parity bits, are linear sums (XOR) of the information bits. B. FAULT SECURE DETECTOR: The core of the detector operation is to generate the syndrome vector, which is basically implementing the following vector-matrix multiplication on the received encoded vector c and parity-check matrix H : T (4.3.1) s = c. H Fig 2 The generator matrix of (15, 7, 5) EG-LDPC code in cyclic format The generator matrix in cyclic code can be converted in systematic form by row operations. In the matrix the first 3 rows are not in systematic form. The core of the detector operation is to generate the syndrome vector (s), which is done by multiplying the received codeword (c) with parity-check matrix (H). S = C. H T H = [I N-K P T ] If S = 0, No Error If S = 1, Error present i0 = i0 + i4 + i6 i1 = i1 + i5 i2 = i2 + i6. Fig 3: Systematic Encoder Circuit The encoded vector consists of information bits followed by parity bits, where each parity bit is Fig 4.Error Detector 491

4 C. MEMORY A 128 X 16 memory is used i.e. memory width of 16 and depth of 128 is used Data bits stay in memory for a number of cycles and, during this period, each memory bit can be upset by a transient fault with certain probability. Therefore, transient errors accumulate in the memory words over time. E. DECODER: A simple decoder is used to obtain the information vector. Once the correct codeword is obtained, the bits 1 to 7 are taken which is the original information vector Fig 5 128x16Memory D. CORRECTOR: Later during memory access operation the stored code words will be accessed from the memory unit.code words are susceptible to transient faults while they are stored in the memory.therefore a corrector unit is dedigned to correct potential errors in the received code words.in our design all the memory words pass through the corrector and any potential error in the memory words will be corrected.smiliar to the encoder unit,a fault secure detector monitors the operation of the corrector unit. Fig 7 : C1 C7 Decoder FLOORPLANNING: Floorplanning is chip-level layout design.when designing a leaf cell,we used transistors and vias basic components. Floorplanning uses adders,registers and FSMs as the building blcks. PLACEMENT: Assign cells to positions on the chip, such that no two cells overlap with each other and some cost function is optimized. ROUTING : Routing means connecting wires with out overlapping. Fig 6 : Serial one-step majority logic corrector 492

5 V.SIMULATION RESULTS invalid codeword. 5.1 TOP MODULE Fig 9 corrector output waveform Fig.5.4.shows corrector output waveform the correct value of a each bit in the codeword directly from the received codeword and produce correct coderword. Fig 7 Output waveform of Encoder Fig.5.2 shows output waveform of encoder which encode input k-bit information vector i and produce n-bit codeword c as output Fig 10 simulation result for top module Fig 8 Detector output waveform when d=0. Fig.5.3 shows output waveform of detector which obtain syndrome vector by performing vector multiplication of codeword c and parity check matrix H, if output is zero then it is valid codeword, otherwise 493

6 Fig 11 Soc (RTL encounter): VII FUTURE SCOPE: Using larger EG-LDPC codes (63, 37, 9) 4 errors in the codeword can be corrected. These larger codes can be useful when using information length of 37 bits & codeword of length 63 bits. REFERENCES: Fig 12 Routing [1] Shu Lin and Daniel J. Costello. Error Control Coding. Prentice Hall, second edition, 2004 [2] R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT Press, [3] S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2004 [4] H. Naeimi and A. DeHon, Fault-tolerant nanomemory with fault secure encoder and decoder, presented at the Int. Conf. Nano-Netw., Catania, Sicily, Italy, Sep Fig 13 Memory in soc technology VI.Conclusion: Fault tolerant memory architecture is presented which tolerates transient faults both in storage unit and in the supprtoing logic. The (15, 7, 5) EG-LDPC code used here can correct upto 2 errors and the data_in value is re-written its correct value after the parallel corrector corrects. The structure can correct both the errors at same time in single clock which is due to the parallel architecture of the corrector in which all 15 corrector circuits operate at same time. When 3 or more errors occur the parallel corrector cannot correct them and the detector for parallel corrector detects the output of parallel corrector erroneous and sets its signal high indicating that the output of the parallel corrector is wrong. [5] H. Naeimi and A. DeHon, Fault secure encoder and decoder for memory applications, in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst., Sep. 2007, pp [6] Y. Kou, S. Lin, and M. P. C. Fossorier, Lowdensity parity- check codes based on finite geometries: A rediscovery and new results, IEEE Trans. Inf. Theory, vol. 47, no. 7, pp , Jul

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