Design of a Low Density Parity Check Iterative Decoder

Transcription

1 1 Design of a Low Density Parity Check Iterative Decoder Jean Nguyen, Computer Engineer, University of Wisconsin Madison Dr. Borivoje Nikolic, Faculty Advisor, Electrical Engineer, University of California, Berkeley Engling Yeo, Graduate Mentor, Electrical Engineer, University of California, Berkeley ABSTRACT A Low Density Parity Check iterative decoder is implemented in 0.13 µm CMOS technology with 6 metal layers. Using a 1023 x 32 parity-check matrix, this code has at least an order of magnitude less computational requirement than traditional error correcting methods that provide similar bit-error rate performance. Power and throughput optimization is achieved through exploitation of massive amount of parallelism in the decoding algorithm, while maintaining a manageable core area. The implementation and design flow of the LDPC decoder using computer-aided design tools are discussed. The LDPC decoder design occupies an area of 1.5mm x 1.5mm. INTRODUCTION A basic communication system is composed of three parts: a transmitter, channel, and receiver. Transmitted information becomes altered due to noise corruption and channel distortion. To account for these errors, redundancy is intentionally introduced, and the receiver uses a decoder to make corrections. In errorcorrecting control (ECC), it is pertinent to have a high code rate while maintaining low complexity. Soft-input-soft-output (SISO) decoders differ in that they have as inputs and outputs probabilistic information, instead of sequences of bits. SISO decoders use digital signal processing and therefore are more robust, but result in a high complexity [1]. In addition, SISO decoders ease in passing information in an iterative fashion. Iterative decoding is a new and powerful technique for error correction in communication systems; it leads to a significant improvement in bit error rate (BER) over conventional decoders. Low Density Parity Check (LDPC) coding is implemented as a SISO iterative decoder that represents a fundamentally new approach to error correction in wired, wireless, and optical communications. A large, dense parity-check matrix defines the LDPC message passing algorithm, and is essential to a successful implementation [2]. LDPC coding has many advantages including large coding gains, and less computational complexity compared to other coding schemes like the BCJR, Viterbi, and Turbo codes [3]. This type of coding also has a more effective BER performance than other schemes, like the ReedSolomon codes. Another advantage is the ability to pipeline the decoder for high-speed implementations in order to reduce delay at the cost of registers and latency. Yet another advantage is the smaller number of required iterations, and therefore lower complexity, due to being able to determine if a codeword is reached based on the parity-check matrix. Disadvantages of the LDPC decoder include the complicated memory structure for serial architectures, and the complexity with interconnect routing for parallel architectures. Serial architectures are slower, resulting in reduced cost. Parallel architectures have higher throughput and lower power dissipation. This paper is organized as follows. First, LDPC codes are introduced along with the message-passing algorithm. Next, the implementation for the physical design is discussed. The final section presents simulation results and conclusions. LDPC DECODER The decoder model consists of two classes of s: equality-bit s and parity-check s. Equality-bit s represent the bits of the codeword, and the paritycheck s represent the parity-check relationships. The log-likelihood ratio (LLR), defined as the natural logarithmic of the ratio of the probability of the value being 1 to the probability of the value being 0, are inputs sent directly to the equality-bit s: LLR(p) = log P(x = 1) (1) P(x = 0) The output corresponds to the parity of the parity-check s; if the parity-check value is positive, the output has even parity while a negative value has odd parity. Each iteration is defined as one complete cycle of passing information between the equality-bit and parity-check. After every iteration, the bit error rate is significantly reduced, as complexity increases. The equality-bit (Figure 1) uses an adder to sum up all inputs, except the input corresponding to the paritycheck the output is connected to, and the loglikelihood ratio. The inputs are labeled rij and outputs labeled qij, where the i index represents the equality-bit and j index represents the parity-check. Input

2 2 r12 r34 Σ q32 in order to avoid short cycles between the s. A very powerful error-correcting code results from a matrix that is random and irregular. Figure 3 shows an example parity-check matrix and the connections it defines. The circles represent equality-bit s and the squares represent parity-check s. LLR1 q32 = r34 + r12 + LLR1 Figure 1: Equality-bit and output values of the equality-bit in this design are represented in five bits. The parity-check (Figure 2) uses two lookup tables (LUT), an adder, and a multiplexer. All inputs, except the input corresponding to the equality-bit the output is connected to, are sent through the first lookup table (2). The lookup table outputs are then summed together and passed through a second lookup table (3). A multiplexer is then used to decide if the value should be negated based on the exclusive-or of the most significant bit of the inputs. Finally, parity bits are generated based on the multiplexer output. rij represents the output and qij represents the input. Outputs of the equality-bit s are the inputs to the parity-check s, and outputs of the parity-check s are the inputs to the equality-bit s. Similar to the equality-bit, input and output values of the parity-check in this design are represented in five bits. φ(x) = - log tanh(1/16x) (2) φ (x) = 6*(-log tanh(1/4x) ) (3) The parity-check matrix is a zero-one matrix defining the connections between the equality-bit s and parity-check s when a 1 in the matrix exists. The rows of the matrix represent the parity-check s, while the columns of the matrix represent the equality-bit s. In this design, there were 1023 rows for the parity-check s and 32 columns for the equality-bit s. The matrix must have low density COMPUTER-AIDED DESIGN TOOLS This section presents a brief summary of the computeraided design (CAD) tools used in the design of the LDPC decoder. Mathworks Matlab is a high-performance tool used in computing numerical values, especially computations involving matrices. Simulink is a companion of Matlab, used in modeling, simulating, evaluating, refining, and analyzing discrete- and continuous-time systems. Synopsys (MC) is a compilation tool that creates intensive modules to be enhanced and optimized. Design (DC), a companion to, is a logic synthesis tool used in gate-level design with a hardware description language, netlist, or schematic. Design Planner (DP) is a hierarchical tool that allows floorplanning, optimization, and analysis of gate designs. Cadence Silicon Ensemble is used in the placement and routing of the physical implementation of integrated circuits. Design Framework II (DFII) lays out the skeleton floorplan of the LDPC decoder. Mentor Graphics Calibre checks for block and cell physical verification. LDPC DESIGN FLOW Physical design of the LDPC decoder was done using previously described CAD tools, and following the Simulink-to-Silicon Hierarchical Automated Flow Tool (SSHAFT) design flow [5]. SSHAFT provided a fast, automated design flow for constructing the decoder. The design flow is shown in Figure 4. Emphasis was placed on implementing a design with minimal area. First, the equality-bit was defined as a in MC. To ensure correct ality, a Simulink q12 φ(x) q42 q33 φ(x) φ(x) Σ φ (x) M U X r32 Figure 2: Parity-check

3 outputs bit.bvhd VHDL Debugger al verification Simulink bit.bvhd check VHDL Debugger al verification Simulink check parity-check matrix Matlab script.m LDPC inputs Figure 3: Example parity-check matrix and corresponding LDPC model description of the equality-bit was implemented (Figure 5). Simulation of the MC description of the equality-bit produced a behavioral VHDL description. A VHDL testbench was used for comparison of the two different descriptions. The Simulink model generated random input values and calculated the correct output values. VHDL Debugger then used the same input values for the MC model, and compared both Simulink and MC output values. The VHDL Debugger displayed the waveforms as shown in Figure 6. The equality-bit defined in MC was delayed by one clock cycle compared to the Simulink model. Similarly, the parity-check was defined both in MC and Simulink (Figure 7). Figure 8 shows the VHDL debugger waveforms. The parity-check.mcl Synthesize and Optimize.db Design compile.edif Design Framework II skeleton floorplan Design Planner Floorplan Silicon Ensemble Place and Route Design Rul e Checking (DRC) Layout vs. Schematic (LVS) Figure 5: Simulink model of equality-bit Figure 4: LDPC physical design flow

4 4 Figure 6: VHDL Debugger waveforms for equality-bit defined in MC was delayed by three clock cycles compared to the Simulink model. The 1023 x 32 parity-check matrix was randomly defined in Matlab. Figure 9 shows the sparse characteristic of the matrix. A Matlab script was then written to define the entire LDPC module based on the parity-check matrix. The module instantiated equality-bit s and parity-check s, along with defining their connections and the inputs and outputs to the decoder. There were a total of 1056 equality-bit s, each with 31 inputs. 121 parity-check s with 3 inputs, 174 with 2 inputs, 281 with 1 input, and 460 s had 0 inputs. The MC description of the entire LDPC decoder was then synthesized and optimized, producing a.db file. With optimization constraint on speed, the area of the design was 2.0mm x 2.0mm with a delay of ns. With optimization constraint on size, the area of the design was 1.5mm x 1.5mm with a delay of ns. The results show a tradeoff between area and speed. The.db file produced by MC was then read and compiled using DC. The.db file is a database file of netlists compatible with Synopsys. Next, the file was Figure 8: VHDL Debugger waveforms for parity-check Figure 9: 1023 x 32 parity-check matrix then used to create an.edif (electronics design interchange format) file needed for the physical design of the decoder. The.edif file is a netlist in industrial standard format; DC translates the.db file to a.edif file that can be used with other CAD tools. DFII imports the.edif netlist defined and then creates a skeleton floorplan generated by automated flow. The skeleton floorplan allowed simple manual placement of instances and boundaries. Floorplanning was completed with Design Planner. The final floorplan is shown in Figure 10. This part of the design consisted of drawing out the cell rows, compacting the boundary around the drawn rows, and optimizing the pin positions. The cell rows were drawn with 50% utilization and an aspect ratio of 1.0. After the floorplan was mapped out, Silicon Ensemble routed the decoder. Placement and routing was done to generate mask layout patterns when the decoder is fabricated. Figure 7: Simulink model of parity-check

5 5 Figure 10: View of LDPC floorplan Although the LDPC decoder physical design is complete, errors must be checked. Design rule checking (DRC) is performed to ensure no errors occur with the specified design rules. Design rules are specified to ensure the decoder can be properly fabricated. Design rules used in the SSHAFT flow checked the density on all active, poly, and metals. In addition, manufacturability rules were performed. The DRC errors encountered in this design flow were due to cells being misaligned with the standard grid. Another DRC problem was the spacing between metal 1 objects and metal 2 objects. The last problem dealt with the area enclosed by metal 1. After DRC errors are corrected for, layout vs. schematic (LVS) checks for unmatched nets between the layout and schematic. Figure 11: LDPC decoder design CONCLUSION Table 1 shows a summary of the delay, power, and area of each component. The LDPC iterative decoder design occupies an area of 1.5mm x 1.5mm, with ns time delay and 0.06 W power dissipation. The most difficult aspect in the design flow is the complicated routing, leading to problems with design rules and block and cell verification. This decoder was a simple, flat design. Future work includes involves hierarchical LDPC decoder. Other work includes a redefined parity-check matrix which will benefit in lower complexity. Serial and parallel architectures that emphasize on delay and area for the LDPC decoder should also be explored. Node Inputs Area Power (W) Delay (ns) Instances equality-bit parity-check parity-check parity-check parity-check LDPC module Table 1: Summary of LDPC s and module

6 6 REFERENCES [1] E. Yeo, B. Nikolic, V. Anantharam, Architectures and Implementations of Iterative Decoders, to appear in IEEE Communications Magazine, 2002 [2] E. Yeo, P. Pakzad, B. Nikolic, V. Anantharm, VLSI Architectures for Iterative Decoders In Magnetic Recording Channels, IEEE Transactions on Magnetics, Vol. 37, March 2001 [3] T. Oenning and J. Moon, Low Density Parity Check Coding for Magnetic Recording Channels with Media Noise, to appear in ICC, 2001 [4] J. Fan and J. Cioffi, Constrained Coding and Soft Iterative Decoding, in Proc. GLOBECOM 99, vol. 16, Rio de Janeiro, Brazil, Dec [5] _Flow/ic_design_flow.htm