Laboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013

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1 CME 342 (VLSI Circuit Design) Laboratory 6 - Using Encounter for Automatic Place and Route By Mulong Li, 2013 Reference: Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Erik Brunvand

2 Background knowledge Place and Route: is the process of taking a structural file (Verilog in our case) and making a physical chip from that description. It involves placing the cells on the chip, and routing the wiring connections between those cells. The structural Verilog file (that we generated in Lab5) gives all the information about the circuit that should be assembled. Encounter Digital Implementation (EDI) System: is a Cadence tool for creation of digital integrated circuits. This includes floor planning, power planning, test and place and route. LEF: Library Exchange Format is a specification for representing the basic physical layout information of an integrated circuit in ASCII format. It includes only some of the design rules and abstract view information about the cells. In this lab, we will use some LEF files that contain layout information of the technology, the standard cell library and the IO library. 2

3 1 Getting Started In this lab, we will continue working on that ripple carry adder we synthesized in Lab 5. The optimized netlist of rca will be imported into the Encounter tool, along with the layout information of all standard cells. Then we will put a power ring as the power supply for all the cells in our design, place all the cells and let Encounter to route the connections. 1.1 Cadence Encounter start-up: a) In your home directory, type encounter to start Encounter. Directory ~/cabinet/cme342/encounter/ will be automatically created for you. $ encounter-cme342 b) After a while you should see a warning similar to the one below: encounter: WARNING: The current host architecture (lnx86 32bit) is not compatible encounter: with the selected binary (lnx86 64bit). encounter: To run the lnx86 64bit binary, you must use a 64bit processor encounter: and OS to use that binary. encounter: INFO:.Forcing the bit selection to 32bit. c) Ignore this warning. It just tells you that the default b4bit binary is not available. After a while the GUI pops out. It ll take a few minutes if you open Encounter for the first time. Figure 1.1 3

4 2 Encounter Place and Route 2.1 Importing the Design a) Once the tool is started, you need to read your design files into the tool. Select File -> Import Design and the Design Import window will pop up as shown in Figure 1.2. Figure 2.1 4

/encounter/lef and choose all 3 lef files: vst_n18_sc_tsm_c4_tech.lef is the technology file, vst_n18_sc_tsm_c4_stdcell.lef contains all standard library cells, and tpz973g_7lm.

5 b) In the Basic tab, choose Verilog for Netlist. Browse to your optimized RCA netlist. It should be under the directory of CME342/synopsys_dc/SYN/NETLIST/ c) Provide the Top Cell name: rca_n4 d) For Technology/Physical Libraries, browse to./encounter/lef and choose all 3 lef files: vst_n18_sc_tsm_c4_tech.lef is the technology file, vst_n18_sc_tsm_c4_stdcell.lef contains all standard library cells, and tpz973g_7lm.lef contains information about IO pads. NOTE: order matters here. Make sure the technology file is the first one. Figure 2.2 e) Since there s no clock in our RCA design, we can leave the Timing Libraries and Timing Constraint File fields blank. f) Switch to Advanced tab, click on Power, and put VDD and VSS in the Power and Ground Nets fields, as shown in Figure 2.3. Figure 2.3 5

6 g) Click Save to save the current settings, so that you can always reload the same settings in the future. Then click OK to finish the Design Import, the Encounter window will now look like Figure 2.4: 2.2 Floorplanning Figure 2.4 Floorplanning is the step where you make decisions about how densely packed the standard cells will be, and how the large pieces of your design will be placed relative to each other. Because there is only one top-level module in the rca adder, this is automatically assumed to cover the entire standard cell area. a) Select Floorplan -> Specify Floorplan to open the Specify Floorplan dialog box (Figure 2.5). In this dialog box you can change various parameters related to the floorplan: 6

7 Figure 2.5 Aspect Ratio: This sets the (rectangular) shape of the cell. An aspect of close to 1 is close to square. An aspect of 0.5 is a rectangle with the vertical edge half as long as the horizontal, and 1.5 is a rectangle with the vertical edge twice the horizontal. This is handy if you re trying to make a subsystem to fit in a larger project. For now, just for fun, we ll change the aspect ratio to 0.3. Note that the tool will adjust this number a little based on the anticipated cell sizes. Core Utilization: This lets the tool know how densely packed the core should be with standard cells. The default is around 70% which leaves room for in place optimization and clock tree synthesis, both of which may add extra cells during their operation. For a large complex design you may even have to reduce the utilization percentage below this. 7

8 Core Margins: These should be set by Core to IO Boundary and are to leave room for the power and ground rings that will be generated around your cell. All of the Core to... values should be set to 8. Note that even though you specify 5, when you apply those values they may change slightly according to Encounter s measurements. b) Keep the other fields default, and click OK. The main Encounter window should look like Figure 2.6. The rows in which cells will be placed are in the center with the little corner diagonals showing how the cells in those rows will be flipped. The dotted line is the outer dimension of the final cell. The power and ground rings will go in the space between the cells and the outer boundary. Figure 2.6 8

9 c) This is a good spot in which to save the current design. There are lots of steps in the process that are not undo-able. It s nice to save the design at various points so that if you want to try something different you can reload the design and try other things. Save the design with File -> Save Design.... Data Type Encounter and File name <filename>.enc. In my case I ll name it rca_n4_fplan.enc so that I can restore to the point where I have a floorplan if I want to start over from this point. Saved designs are restored into the tool using the File-> Restore Design... menu. 2.3 Power Planning a) Now it s time to put the power and ground ring around your circuit, and connect that ring to the rows so that your cells will be connected to power and ground when they re placed in the row. Start with Power -> Power Planning -> Add Ring From this dialog box (Figure 2.7) you can control how the power rings are generated. The fields of interest are Ring Type: The defaults are good here. You should have the Core ring(s) contouring set to Around core boundary. Ring Configuration: You can select the metal layers you want to use for the ring, their width, and their spacing. Make the top and bottom of the ring horizontal metal1, and the right and left vertical metal2 to match our routing protocol. Change the width of each side of the ring to 2.2 and the spacing should be set to Finally, the offset should be changed to center in channel. b) When you click OK you will see the power and ground rings generated around your cell. You can also zoom in and see that the tool has also generated arrays of vias where the wide horizontal and vertical wires meet. c) Now we can connect power to the rows where the cells will be placed. Select Route -> Special Route to route the power wires. Make sure that all your power supplies (VSS and VDD) are listed in the Net(s) field. Other fields don t need to be changed unless you have specific reasons to change them. Click OK and you will see the rows have their power connections made to the ring/stripe grid as seen in Figure 2.8. Zoom in to any of the connections and you ll see that an array of vias has been generated to fill the area of the connection. 9

10 Figure

Figure 2.8 d) If check the command terminal, you ll see a number of warnings at this step complaining that there are no standard cells and no block or pad pins to be routed.

11 Figure 2.8 d) If check the command terminal, you ll see a number of warnings at this step complaining that there are no standard cells and no block or pad pins to be routed. That s fine, since we haven t placed any cells yet. But our cells will be placed in the rows so that they'll use the power and ground wires. e) After the power rings are created you need to create Global Net Connections. This is done to specify the pins inside the standard cells/blocks that need to connect to the global power nets. Click on Power -> Connect Global Nets. We will first add VDD signal. In the Connect/Pin part of the dialog box, enter VDD. Under Scope, select check button "Apply All" and in the field To Global Net, enter VDD. After selecting these options, click on "Add to List". Repeat the procedure for the ground signal, VSS. Apply and Close. 11

into that floorplan. Select Place -> Place Standard Cells.

12 Figure 2.9 f) Now is another good time to save the design. This time save it as rca_n4_powerplan.enc. 2.4 Placing the Standard Cells a) Now you want the tool to place the standard cells in your design into that floorplan. Select Place -> Place Standard Cells... Leave the defaults in the dialog box as seen in Figure 2.9. You want to use Run Full Placement and Include Pre-Place Optimization. Figure

b) After pressing OK your cells will be placed in the rows of the floorplan. This might take a while for a large design. When it s finished the screen might not look any different.

13 b) After pressing OK your cells will be placed in the rows of the floorplan. This might take a while for a large design. When it s finished the screen might not look any different. Change to the Physical view (the rightmost design view widget - see Figure 2.10) and you ll see where each of your cells has been placed. Figure 2.11 c) Now save the current design as rca_n4_place.enc. 2.5 Routing a) Now that the cells are placed, since there s no global clock in our design, we can skip the Clock Tree Synthesis (CTS) step and jump to the final routing. Select Route -> NanoRoute -> Route to invoke the router. We ll keep all the settings default here. Of course, you are welcome to play around with these settings to see what happens. b) Click OK and the routing will start. This can take a long time on a large design. When it finishes, check the terminal window. You should see 0 DRC violations and 0 fails. Now the placed and routed design should look like Figure 2.11: 13

Figure 2.12 c) Save the routed design as rca_n4_route.enc. 2.6 Adding Filler Cells After the final optimization is complete, you need to fill the gaps in the cell row with filler cells.

Select Place -> Physical Cell -> Add Filler. Click on Select to select a Cell Name, Add FILL1, close.

14 Figure 2.12 c) Save the routed design as rca_n4_route.enc. 2.6 Adding Filler Cells After the final optimization is complete, you need to fill the gaps in the cell row with filler cells. These are cells in your library that have no active circuits in them, just power and ground wires and NWELL layers. Select Place -> Physical Cell -> Add Filler. Click on Select to select a Cell Name, Add FILL1, close. Clicking OK will fill all the gaps in the rows with filler cells for a final cell layout as seen in Figure You can also zoom around in the layout to see how things look and how they re connected. Figure

15 2.7 Checking the Result Figure 2.14 There are a number of checks you can run on the design in SOC Encounter. a) The first thing you should check is that all the connections specified in your original structural netlist have been made successfully. To check this, use the Verify -> Verify Connectivity menu choice. The defaults as seen in Figure 2.14 are fine. This should return a result in the terminal that says that there are no problems or warnings related to connectivity. If there are, you need to figure out what they are and start over from an appropriate stage of the place and route process to fix them. If there are problems it s likely that routing congestion caused the problem. You could try a new route, a new placement, or go all the way back to a new floorplan with a lower core utilization percentage or more space between rows for routing channels. b) Another check you can make is DRC check on the routing and abstract views. To do this, select Verify -> Verify Geometry. Use default settings. This is not a substitute for a full DRC check in Virtuoso. This check only runs on the routing and abstract views, and has only a subset of the full rules that are checked in Virtuoso. But, if you have errors here, you should try to correct them here before moving on to the next step. You can view the errors with the Violation Browser from the Tools menu. You can use this tool to find each error, get information about the error, and zoom in to the error in the design window. 15

16 Figure

17 Figure 2.16 c) Save the verified design in any name you like. Then we have finished the P&R for our ripple carry adder. 17

18 Exercise: In this exercise, you are asked to place and route the 4 bit comparator you synthesized in Lab5. Follow all the same steps we did for ripple carry adder: importing design, floorplanning, power planning, placing and routing, adding fillers, checking the design. Remember to save your design after each step, in case Linux crashes or you want to undo any step. Report: 1. Final layout view of the verified design 2. Results of Connectivity and Geometry verification 18

Tutorial for Cadence SOC Encounter Place & Route

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