LTCC (Low Temperature Co-fired Ceramic)

Transcription

1 LTCC (Low Temperature Co-fired Ceramic) Design Guide Line. 381, Wonchun-Dong, Paldal-Ku, Suwon City, Kyung Ki-Do, Republic of Korea Tel : (Ext. 470) Fax : Homepage : 1

2 LTCC DESIGN GUIDELINES TABLE OF CNTENTS 1. PROCESS 1-1. CAD SYSTEM 1-2. RF-SIMULATION 1-3. MANUFACTURING PROCESS 2. MATERIALS PROPERTY 2-1. GLASS CERAMIC MATERIALS 2-2. CONDUCTOR 3. BASIC OUT LINE 3-1. GREEN SHEET SIZE 3-2. SUBSTRATE SIZE 3-3.CAVITY SIZE 4. DESIGNRULE 2

3 1. PROCESS 1-1. CAD Design & RF Simulations 1-2. Manufacturing Process 3

4 2. MATERIAL PROPERTY 2-1. Glass Ceramic Materials Materials GC-3 GC-4 GC-5 GC-6 Dielectric constant 1MHZ RT GHZ RT GHZ RT Tanδ 1MHZ RT GHZ RT GHZ RT Thermal Conductivity W/mk Coefficient of Thermal Conductivity Density - X10-7/K */103k g/m3 Bending Strength MPa Particle size D50 um Dmax. um Conductor Materials Conductor Type Co-fire Electroless Plating (Ni/Au) Ag Ni 3~5um Au Volume Resistance (μω Cm) 2~3 3 Conductor Thickness (um) 15+/-5 >0.07 >0.5 Solderability X O O Bonderability X O O 4

5 3. BASIC OUTLINE 3-1. Substrate size a Basic Outline mm b Border Width mm 5 3 Dimensional Accuracy % ±0.5 ±0.3 Warpage (Camber) % ±0.4 ±0.2 * Border Width b is Subject to Change. It s depends on the Substrate Thickness & Size!! All designs are made on a fired size. * Camber is defined as below equation - C = T max - T min, C= Camber (Warpage) D T min C T max 5

6 3-2. Size of Green Sheet and Alignment Target Guide Hole Cut Line Orientation Hole for Laser Punching A B C Perimeter of sheet shall be used for guide hole, cutting line and orientation hole. Enlarged usable area shall be used for test structures. Usable area shall be used for actual circuit. Cut lines are placed on each corners of designed sheet size. Key Description Size A Usable Area 130 mm 130 mm B Enlarged Usable Area 142 mm 142 mm C Sheet Area 175 mm 175 mm 6

7 3-3. Cavity Size a b c t Bt a Substrate Edge to Cavity μm b Cavity Step Width μm c Cavity Depth μm 150~ t Layer Thickness μm Bt Base Layer Thickness μm Thickness Accuracy % ±20.0 ±10.0 Cavity Size Accuracy % ±10.0 ±5.0 7

8 4. DESIGN RULE 4-1. Wire bonding PAD a Pad Width μm b Pad to Pad Space μm c Pad to Cavity μm A Pad Pitch Accuracy (Inner Pad to Inner Pad) % ±0.5 ±0.3 B Pad Pitch Accuracy (Outer Pad to Outer Pad) % ±0.8 ±0.5 8

9 4-2. Flip Chip bonding PAD a Pad Diameter μm Pad Size Accuracy μm ±50 ±30 b Pad to Pad Pitch μm Pad Pitch Accuracy % ±150 ±60 c Via Diameter μm d Distance Between Pads (Right end to Left end Pads) % ±0.8 ±0.5 9

10 4-3. SMD PAD Item Std. a Pad Size μm 250 b Pad Spacing μm 200 c Pad edge to Substrate edge μm

11 4-4. Over glaze PAD Item Std. a Pad Edge to Overgraze Edge μm 200 b Pattern Width μm 250 c Spacing (Slit) μm 200 d Substrate Edge to Overgraze μm

12 4-5. Exposed Signal Conductor a Via Hole Diameter μm b Via Hole Catch Pad μm c Via Hole Pitch μm d Via Catch Pad to Line μm e Via Catch Pad to Substrate Edge μm f Via Catch Pad to Cavity Edge μm g Line Width μm h Line Spacing μm i Line to Substrate Edge μm j Line to Cavity Edge μm k Castellation to Line μm l Castellation to Via Catch Pad μm

13 4-6. Embedded Signal Conductor a Via Hole Diameter μm b Via Hole Catch Pad μm c Via Hole Pitch μm d Via Catch Pad to Line μm e Via Catch Pad to Substrate Edge μm f Via Catch Pad to Cavity Edge μm g Line Width μm h Line Spacing μm i Line to Substrate Edge μm j Line to Cavity Edge μm k Castellation to Line μm l Castellation to Via Catch Pad μm

14 4-7. Ground Plane & Power a Via Hole Diameter μm b Via Hole Catch Pad Diameter μm c Isolation Gap With Via in Upper Layer μm Without Via in Upper Layer μm d Solid Plane μm e Substrate Edge to Ground Plane μm f Substrate Edge to Via Cover μm g Cavity Edge to Ground Plane μm h Cavity Edge to Via Catch Pad μm

15 4-8. Castellation a Castellation Via Hole Diameter μm b Conductor Diameter μm a+300 a+200 c Space for Via to Via μm d Castellation to Ground Plane μm e Depth for Castellation Via μm <a <a 15

16 4-9. Embedded Components (Inductor) a Line Width μm b Line to Line Space μm c Line to Substrate Edge μm d Via Hole Diameter μm e Via Hole Catch Pad Diameter μm f Via Catch Pad to Substrate Edge μm

17 4-10. Embedded Components (Capacitor) Item Std. a Conductor Size mm ~5.0 b Conductor Layer to Layer Space mm >a c Distance Among Each Layers μm 25~ 17