Embedded UTCP interposers for miniature smart sensors

Transcription

1 Embedded UTCP interposers for miniature smart sensors T. Sterken 1,2, M. Op de Beeck 2, Tom Torfs 2, F. Vermeiren 1,2, C. Van Hoof 2, J. Vanfleteren 1,2 1 CMST (affiliated with Ugent and IMEC), Technologiepark 914a, 9052 Zwijnaarde, Belgium 2 IMEC, Kapeldreef 75, 3001 Leuven, Belgium 4 december 2012 IMAPS medical applications workshop, Paris

2 Motivation Lot of attention is given to system miniaturization small chip packages, stacking op chips,... towards small, light-weight, comfort, conformable,... in medicine, healthcare, sports, consumer, industry 2

3 HOW : Thin chip embedding Two-step approach towards miniaturization Chip package Ultra Thin Chip Package UTCP Embedding in flexible Circuit Board 3

4 Outline 3 parts : > INTRODUCTION : WHY? >> TECHNICAL PART : HOW?? >>> PROTOTYPES Step 1 : Ultra-Thin Chip Package > Note : future developments of UTCP Step 2 : Embedding in an FCB Chip package Ultra Thin Chip Package UTCP Embedding in flexible Circuit Board 4

5 UTCP in a 3 steps 1. Off-the-shelf dies, thinned down to ± μm 2. thin die embedded in polyimide 3. Cu metallisation for fan-out Thin Si die UTCP : Flexible package Thin : μm Interposer for embedding in FCB Si die Polyimide 2 Polyimide 1 - ESTC - Sept 2012 Tom Sterken 5

6 UTCP in a 3 steps 1. Off-the-shelf dies, thinned down to ± μm 2. thin die embedded in polyimide 3. Cu metallisation for fan-out Thin Si die UTCP : Flexible package Thin : μm Interposer for embedding in FCB Si die Polyimide 2 Polyimide 1 - ESTC - Sept 2012 Tom Sterken 6

7 1. UTCP process flow: chip thinning Chip thinning : chip thickness : 15-30μm ± 2μm 2 options: - die level (lab mode) on Logitech PM5 tool - wafer level thinning (Disco tool) Chip thinning issues : warping of the die influence of topography / layers on top of Si Si thickness chip thickness (!) thin chip handling (!) Die thinning < 30um Chip warping 120 μm 4600 μm 7

8 2. UTCP process flow: chip placement Coat HD4110 photo-patternable polyimide (PI) on rigid carrier with release layer Dispense/spin of BCB (Dow Chemical) curing at 250ºC without outgassing Placement (face up) of thinned IC Use gentle pressure during BCB curing to keep chips flat placement of multiple chips per substrate for higher throughput 8

9 UTCP process flow: chip cavity fabrication PI HD4110 spinning (chip thickness) Backside illumination (no mask needed) Make cavity by polyimide development 9

10 Advantages of chip cavity 1. Improved step coverage Non-flat UTCP Flat UTCP 2. Spreaded pressure distribution 10

11 3. Process Flow: fabrication of Cu fanout Chip placement Cavity formation Fabrication of Cu fanout ENIG finish PI HD4110 spinning Exposure to make via holes in PI Metallization: - seed: TiW (50nm) + Cu(1um) - electroplating : Cu (5um) Cu micro-etch (improves resist adhesion) Lithography and etch to pattern metal Release UTCP from carrier 11

12 Final result... finished UTCP 30-70um thin, highly flexible chip package ready for further integration 12

13 Testing: double fan-out pattern (1) (2) UTCP provides 2 fan-outs : (1) Easy testing before integration (2) Compatible with std. flex PCB Dedicated test fan-out is used during testing After testing, test fan-out is removed Test fanout should be small to enhance throughput 13

14 Ultra-Thin Chip Package : examples Prototypes : ZL70102 radio transceiver MSP430F1611 microcontroller Nrf24L01 radio Imec analog front-end amplifier Imec DSP ZL70102 MSP microcontroller Die Size Fanout Size Min. Bond pad pitch / spacing ZL x3.1 mm 2 6 x 4 cm 2 80 / 25 um 70 # bondpads Yield 100% (ESD) MSP430F x4.4 mm 2 1.2x1.2 cm 2 75 / 25 um 64 85% nrf24l01 1.9x1.97 mm x 0.8 cm 2 85 / 25 um 21 ( 68% ) Imec AFE 5.2 x 2.6 mm x 1.1 cm / 30 um 64 95% CMOS Imager 7.4 x 6.4 mm / 20 um 70-14

15 UTCP: Summary - Off-the-shelf ICs -60 μm thin package - Know-Good-UTCP - achieved lab-yield : 65% - 95% - bendable (1 cm bending radius) 15

16 UTCP: Outlook Multi-layered UTCP Multi-chip UTCP Thermal & Mechanical reliability UTCP (Sub-)System-in-UTCP Stacked UTCP Implantable UTCP (LCP, Parylene, ) Stretchable UTCP 16

17 Outline 3 parts : > INTRODUCTION : WHY? >> TECHNICAL PART : HOW?? >>> PROTOTYPES Step 1 : Ultra-Thin Chip Package > Note : future developments of UTCP Step 2 : Embedding in an FCB Chip package Ultra Thin Chip Package UTCP Embedding in flexible Circuit Board 17

18 Embedding of UTCP inside Flex PCB LF0100 adhesive Cu Cu PI Cu PI Cu PI UTCP UTCP is placed on adhesive, alignment towards 2 nd Cu layer Lamination of all layers (std. procedure) Via holes: laser drilling and Cu metallization (std. procedure) Assembly of other components (passives, connectors, battery,..) 18

19 19 Top single sided polyimide flex (25μm) UTCP-copper LF0100 Flex adhesive 3 layers of UTCP polyimide IC UTCP polyimide F-PCB: Inner polyimide (50μm) F-PCB-copper F-PCB-copper, outer layer

20 Result after placement and lamination 20

21 Result after placement and lamination L2 metal LF0100 adhesive 11 μm Silicon (ZL70102) HD4110 (UTCP) 30 μm 16 μm LF0100 adhesive 21

22 UTCP based system 22

23 UTCP based system MSP UTCP

24 Wireless ECG monitoring system - Integration of microntroller as flexible UTCP package - Enhanced flexibility of total system - Ohter components can be mounted on top and bottom (enables miniaturization) 24

25 ECG demonstrator prior to molding Electrode B Meander interconnect Magnetic on/off switch Antenna 3 UTCPs Electrode A Embedded UTCP

26 Finished ECG demonstrator after molding Human ECG

27 Embedding Thinned Dies in Flexible PCBs Thank you for your attention

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29 Reliability testing Environmental tests: very good results obtained Hot/humidity storage at 85% rel. humidity & 85 C, up to 1000h thermal cycling : -40/+125 C, up to 1000 cycles More tests are still ongoing Functionality during and after static mechanical load /bending Tests are still ongoing. Promising results, only for strong bending (R<10mm) some temporally artifacts have been observed on very few UTCP s. R Functionality during and after dynamic mechanical load Testing just started Moving cylinder compressible substrate time UTCP Connections with electrical measurement setup IMEC 2011 IMAPS Medical Workshop - June Maaike Op de Beeck 29

30 Chips with Ni/Au UBM prior to UTCP v2.1 fabrication (such as MSP) Ni-Au UBM Start: Chips with Ni-Au UBM Al passivation Chips without Ni/Au UBM (such as Coolbio, AFE ) UBM processing using top-pi layer with via as mask ox ox Al Start: Chips without Ni-Au UBM PI PI Final stage of UTCP: polyimide coat & patterning Cu TiW Final stage of UTCP: polyimide coat & patterning TiW seed & Cu plating TiW Ni-Au UBM by plating C u Possible leakage path Litho and etch Cu and TiW TiW seed & Cu plating, litho, etch Cu and TiW 30

31 31 UTCP v2.2: Ni/Au UBM using extra plating PI layer PI chip Al bond pads Glass substrate Thin die with Al bond pads placed on first PI layer Coating of second PI layer, exposure from backside and development Coating of third PI layer exposure of third PI layer from top side, to make mask for Ni/Au UBM Fabrication of Ni/Au UBM Bond pads are completely covered with Ni/Au Coating of fourth PI layer exposure from top side and development for via definition

32 UTCP : yield evolution 32 UTCP v2.0 using 2 photosensitive PI layers UTCP v2-v3 using 3 photosensitive PI layers UTCP fabrication yield (%) radio The process for producing UTCP-packages has been optimized towards yield and throughput improvement, as tested on 3 types of chips

33 IMEC s UTCP stacking: initial research Process: Stacking of individual UTCP s by lamination processes interconnection between UTCP layers by trough-hole laser vias and Cu plating potentially add functionality e.g. thin-film passives (on flex or on silicon) Advantages Thin stack: < 100 µm per layer aim: 250µm thickness for 4 layers feasible thanks to lamination and interconnect technology instead of soldering Testing and burn in of UTCP s before stacking IMEC 2011 IMAPS Medical Workshop - June Maaike Op de Beeck 33

34 UTCP : activities for 2012 Task 1: Consolidate UTCP process flow on analog IC and radio chip Task 2: Improve process flow towards industrialization: a. Introduce pattern plating b. Introduce thin-dies-on-carrier c. Multiple UTCPs on 1 carrier d. Transfer of UTCP technology to industrial environment Task 3: Future advance UTCP technologies: a. Stacking of UTCP b. Multi-chip system on polyimide Task 4: UTCP reliability testing 34

35 Motivation for our work Lot of attention is given to system miniaturization small chip packages, stacking op chips,... die-to-die or die-to-wafer bonding advanced flip chip and wire bonding TSV (Through-silicon-via) technology alternative packaging approach for system miniaturization: Chip package Ultra Thin Chip Package UTCP Embedding in flexible Circuit Board 35

36 From feasibility to mature processing First UTCP package: feasibility evaluation non-photosensitive polyimide HD PI via formation by laser ablation Process development - improve UTCP fabrication yield - Increase throughput - tested UTCP technology on various chips - adjust process for smaller bond pad pitch UTCP anno photosensitive polyimide HD via formation by lithography - less topography 36

37 From feasibility to mature processing First UTCP package: feasibility evaluation non-photosensitive polyimide HD PI via formation by laser ablation Process development - introduction of HD4110 photosensitive PI + higher viscosity : 1 spin step for 20μm + photosensitive : 1 exposure for 100 vias ± Self-priming - CTE : 35 ppm/deg UTCP anno photosensitive polyimide HD via formation by lithography - less topography 37

38 From feasibility to mature processing First UTCP package: feasibility evaluation non-photosensitive polyimide HD PI via formation by laser ablation Process development -Introduction of release layer (KCl, 400 nm) - Introduction of cavity layer -> Flat UTCP + Step coverage + ENIG finish during the process (bulk isolation) -Introduction of stepping masks : higher throughput - dedicated test fanout UTCP anno photosensitive polyimide HD via formation by lithography - less topography 38