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1 Working with highspeed PCB Design in OrCAD This guide walks through some of the highspeed PCB Design functionality that is available within OrCAD PCB Editor. The are more functionality available than what is described in this material. If you are using Allegro PCB Editor the same capabilities are available. Do not hesitate to contact us in case you have questions or need more information Table of Contents Working with highspeed PCB Design in OrCAD... 1 Installing exercise files... 1 Exercise 1: Net Schedule... 2 Exercise 2: Single-ended impedance... 5 Exercise 3: Min/max propagation delay... 8 Exercise 4: Relative (matched) propagation delay Exercise 5: Differential pair static phase Installing exercise files If the workshop is being performed on a laptop provided by Nordcad there is no need to install the workshop files. Download and installation: 1. Create folder C:\Workshop 2. Download exercise files to C:\Workshop 3. p 4. Unzip files in C:\Workshop This creates a directory C:\Workshop\OrCAD_HighSpeed with the files used in this workshop. Page 1 of 15

2 Exercise 1: Net Schedule This exercise walks through net scheduling which is a function to control that a signal is routed using a specific order. 1. Open the project pcb_editor.opj in the directory C:\Workshop\OrCAD_HighSpeed This is a design that has been cut down to 3 address signals DDR3_A3-0, 4 data signals DDR3_DQ3-0 and a differential strobe signal DDR3_DQS0N-P. 2. Within OrCAD Capture select pcb_editor.dsn in Project Manager and then Tools Create Netlist. 3. The Create netlist dialog setup should be correct. Verify the settings below and press OK. Input board file: C:\Workshop\PCBEditor\OrCAD_Highspeed\allegro\template.brd 4. If a license choice dialog is shown select OrCAD PCB Designer Professional. Page 2 of 15

3 In PCB Editor the mentioned nets are shown. The address signals are purple, data/strobe are green. Since the data/strobe signals are point to point (only consists of 2 pins) it makes no sense to schedule those. The address signals are connected to 4 memory devices and it is important to schedule those nets to ensure correct routing (and constraint setup) 5. Select Edit Net Schedule (Logic Net Schedule) 6. First select a pin with a purple ratsnets on U801 and then the corresponding pin on U600, then U601 and so on. Pins that are selectable are highlighted. Finally select the corresponding pin on R604 and Rightclick Finish. 7. Repeat the process for the other 3 address signals Page 3 of 15

4 8. Now all 3 adress signals are scheduled. Open Constraint Manager and select Electrical Net Routing Wiring. 9. It is easy to verify if all address signals are scheduled by opening the netclass ADDR_CMD and check if Schedule is User Defined as shown below 10. In order to check if the nets are routed according to the schedule it is important to verify the schedule. Set Verify Schedule to Yes for DDR3_A3-0 as shown below 11. Also add a Stub Length max value of 2mm. The reason for this is the fanout vias used. Net schedule will result in a DRC if the net is not routed 100% as scheduled from pin to pin. In this case the routing will be from via to via and there will be a piece of shared routing from the via into the pin on each component. 12. Close Constraint Manager. This is the end of Exercise 1. Routing is part of the upcoming exercises Page 4 of 15

5 Exercise 2: Single-ended impedance Many designs today require a specific impedance to avoid signal integrity issues. In this exercise impedance constraints are setup and used. 1. The exercise continue from Exercise 1 2. First the stackup needs to be verified. Since the impedance calculation depends on materials and their characteristics it is very important to specify the stackup correctly. 3. Select Setup Cross-section 4. Verify that the settings are as shown below 5. Open Constraint Manager and select Electrical Net Routing Impedance 6. Now add 60 Ohm constraints on the address signals DDR3_A3-0. Leave the tolerance 2% Page 5 of 15

6 7. The yellow Target field indicates that the constraint is in-active (online DRC is not performed). To enable/activate Right click on Target and select Analysis Mode 8. Close Constraint Manager and go to PCB Editor 9. Route the 4 address signals DDR3_A3-0 (purple ratsnests). Use inner layers I1 and I2 10. In case you re unfamiliar with routing you should either do our getting started workshop or there are a few lines below about how to route a. Right Click Application Mode Etch Edit (this changes PCB Editor to an object oriented way of working for routing) b. Left click a rat, pin or via to start routing. i. Left click to insert a corner and Double click to insert via and continue routing on another layer c. Finish a connection by left clicking on a pin/via d. Left click an existing connection to slide/push it e. Look at the Options panel to the right to find route settings Page 6 of 15

7 11. When the routing is finished run a DRC check. Select Check DRC Update 12. Open Constraint Manager and select Electrical Net Routing Wiring and verify that net schedule status is PASS 13. Close Constraint Manager and save the design in PCB Editor using File Save This concludes exercise 2 Page 7 of 15

8 Exercise 3: Min/max propagation delay To ensure that the termination resistors are placed closely to U603 a min/max delay constraint is specified on DDR3_A3-0 from U602 R Open Constraint Manager and select Electrical Net Routing Min/Max Propagation Delay 2. Create a pin-pair for each address signal from U603 to R Select DDR3_A0 and Right Click Create Pin Pair 4. In the Create Pin Pairs of xxxx dialog do the following a. Select U603.xx in the First Pins section b. Select R604.x in the Second Pins section c. Left click OK to create the pin pair Page 8 of 15

9 5. Repeat the above steps for the remaining address signals DDR3_A For each of the defined pin-pairs specify a Prop Delay min value of 10mm and a max value of 15mm 7. Depending on the routing in exercise 2 the min/max value will either pass (green) or fail (red). In the example aboe the pin pair U603.L8 R604.3 is too short. (If no nets fail, you could try to decrease or increase the routing length on one of the pin pairs.) 8. Switch back to PCB Editor and locate the routing between U603 and R Select Route Delay Tune and adjust the length for the net that is too short. Tuning patterns can be setup in the Options panel to the right a. Notice the meter that shows if the delay is correct (green in picture below) 10. Switch back to Constraint Manager and verify the min/max delay constraints This concludes exercise 3 Page 9 of 15

10 Exercise 4: Relative (matched) propagation delay The nets DDR3_DQ3-0, DDR3_DQS0N/P and DDR_DM0 must have equal length within a tolerance. Since all these nets are point to point connections there are no need to create pin pairs. 1. Open Constraint Manager and select Electrical Net Routing Relative Propagation Delay 2. Unfold netgroup BL0 and the differential pair DP2 (left click the + signs) 3. Select the nets DDR3_DQ3-0, DDR3_DQS0N-P and DDR3_DM0 4. Then Right click Create Match Group 5. In the Create Match Group dialog a name must be specified for the match group. Type bytelane0 and click Ok to create the match group Page 10 of 15

11 6. This creates the match group which can be found at the top of the list inside Electrical Net Routing Relative Propagation Delay 7. By default when a matched group is defined with a tolerance of +/-5%. In this case another constraint is needed. In the line with Bytelane0 Change Delta: Tolerance to 0mm:0.5mm The result is that all the signals in the match group must have the same length +/-0.5mm. (difference between shortest and longest signal can be 1mm) Page 11 of 15

12 8. Switch back to PCB Editor and route the remaining connections for the nets (Bytelane0) in the match group (green ratsnests) 9. Switch back to Constraint Manager, select Bytelane0 and Right Click Analyze PCB Editor automatically selects a net that is the target which is the net all the other nets are matched against. The net that is selected is the one with the longest manhatten length (x + y distance between pins). After routing, it is often an advantage to select the longest routed signal as the target. To find the longest signal double click the column header Length Page 12 of 15

13 10. In the shown example DDR3_DQS0N is the longest signal. It can differ in your example. Find the longest signal and Right click on Delta:Toleance in the line with the net name and select Set as target Switch back to PCB Editor and use Route Delay Tune to adjust the length on all the connections that are not long enough (should have a red DRC marker) a. For the differential pair it might be necessary to right click single trace mode to only change length of one of the signals. Alternatively change it at the pins. 12. When the length is tuned switch back to Constraint Manager and observe the results This concludes exercise 4 Page 13 of 15

14 Exercise 5: Differential pair static phase Typically, the length of the signals in the differential pair must have an equal length that is tighter than what is in the match group. In some cases a differential pair is not part of a matched group and would still require length matching. For this purpose a static phase can be defined. 1. Open Constraint Manager and select Electrical Net Routing Differential Pair 2. Unfold the netgroup BL0 in order to see DP2 which is the differential pair 3. Now specify Static Phace Tolerance to 0.1mm. This means that the 2 nets in the differential pair must match within 0.1mm In case the length difference is longer than 0.1mm this is marked with red in Constraint Manager 4. Notice the net that is to short in Constraint Manager. In example above it is DDR3_DQS0P Page 14 of 15

15 5. Switch back to PCB Editor 6. Depending on the routing use 1 of the following methodologies a. Route Delay Tune, select route and right click Single trace mode to add more routing length with tuning patterns b. Route Slide, select exiting tuning pattern and move mouse to get correct static phase 7. Make sure that the Static Phase meter shows green. 8. Do a File Save to save the board This concludes Exercise 5 Page 15 of 15