International Journal of Engineering Trends and Technology (IJETT) Volume 6 Number 3- Dec 2013

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1 High Speed Design of Ethernet MAC * Bolleddu Alekya 1 P. Bala Nagu 2 1 PG Student (M. Tech), Dept. of ECE, Chirala Engineering College, Chirala, A.P, India. 2 Associate Professor, Dept. of ECE, Chirala Engineering College, Chirala, A.P, India. Abstract: Nowadays, Ethernet technology is the most widely used network technology, and also widely used in plenty of industries, such as finance, business by means of its efficiency, high-speed and high performance. Gigabit Ethernet can provide communication bandwidth with 1 GB/s. Because it uses the same CSMA/CD protocol, frame format, frame length as the traditional 10/100M Ethernet network, so it is able to realize internet update smoothly and continuously based on the original slow Ethernet to protect user investment utter mostly. But in many applications, it calls for the realization of high-speed network data transmission without using the NIC (Network Interface Card) of PC, and transmitting the post processing data to Gigabit Ethernet. Then describes software design written by Verilog HDL in detail, including reset and initialization of the transmission of data packets. After testing, the transmission rate can reach our goal. The results show that this design meets most requirements of the real-time transmission system and proves to be a practical design with low cost and good stability. Keywords: MAC, CSMA Protocol, High Performance, VHDL. 1. Introduction Nowadays, Ethernet technology is the most widely used network technology, and Gigabit Ethernet is also widely used in plenty of industries, such as finance, business by means of its efficiency, high-speed and high performance. Gigabit Ethernet can provide communication bandwidth with 1Gb/s. Because it uses the same CSMA/CD protocol, frame format, frame length as the traditional 10/100M Ethernet network, so it is able to realize internet update smoothly and slow Ethernet to protect user investment mostly. But in many applications, it calls for the realization of high-speed network data transmission without using the NIC (Network Interface Card) of PC, and transmitting the post processing data to Gigabit Ethernet. This system adopts FPGA and Gigabit NIC to meet the needs. The Ethernet Mac core consists of five modules: Host interface connects the Ethernet Core to the rest of the system via the Wishbone (using DMA transfers). continuously based on the original ISSN: Page 131

2 Registers are also part of the host interface. TX Ethernet MAC performs transmit function. RX Ethernet MAC performs receive function. MAC Control Module performs full duplex flow control function. MII Management Module performs PHY control and gathers the status information from it. All modules together perform a full function 10/100 Mbit/s Media Access Control. The Ethernet core can operate in a half or a full duplex mode. The basic of the Ethernet is CSMA/CD protocol. The CSMA/CD stands for Carrier Sense Multiple Access / Collision Detection. In half duplex mode when a station wants to transmit, it has to observe the activity on the media (Carrier Sense). As soon as the media is idle (no one is transmitting), any station can start with the transmission (Multiple Access). If two or more stations are transmitting at the same time, a collision on the media is detected. All stations stop transmitting and back-off for some random time. After the back-off time, the station checks the activity on the media again. If the media is idle, it starts transmitting. All other stations wait for the current transmission to end. Frame structure of Ethernet Mac core is : Preamble: A 7 bytes pattern of alternating 0 s and 1 s used by the receiver to establish bit synchronization. Start of frame delimiter: The sequence , which indicate the actual start of the frame. Destination Address: specifies the station for which the frame is intended. It may be a unique physical address, a group address or a global address. Source Address: specifies the station that sent the frame. Length: length of the LLC data field. LLC data: Data unit supplied by logic link control (LLC). Pad: Bytes added to ensure that frame is long enough for proper collision detection operation. Frame Check Sequence (FCS):A 32 bit cyclic redundancy check, based on all fields except the preamble, sfd and FCS. ISSN: Page 132

3 2. ABOUT ETHERNET-MAC Ethernet IP Core consists of 5 modules as shown in fig.1. Figure 1 Ethernet IP Core Host Interface: The host interface is connected to the RISC and the memory through the Wishbone. The RISC writes the data for the configuration registers directly, while the data frames are written to the memory. Frames are accessed through the DMA. TX Ethernet MAC: TX Ethernet MAC generates 10BASE-T/100BASE-TX transmit MII nibble data streams in response to the byte streams supplied from the transmit logic (host). It performs the required deferral and back-off algorithms, takes care for the IPG, computes the checksum (FCS) and monitors the physical media (by monitoring Carrier Sense and collision signals). RX Ethernet MAC: RX Ethernet MAC interprets 10BASE-T/100BASE-TX MII receive data nibble stream and supplies correctly formed packet byte streams to the host. It searches for the SFD (start frame delimiter) at the beginning of the packet, verifies the FCS and detects any dribble nibbles or receive code violations. MAC Control Module: The function of this module is to implement the full-duplex flow control. The MAC Control Module consists of three sub modules that provide the following functionality: Control frame detection Control frame generation TX/RX Ethernet MAC Interface PAUSE Timer Slot Timer Control Frame Detector Checks the incoming frames for the control frames. Control frames can be discarded or passed to the host. When a PAUSE control frame is detected, it can stop the TX module From transmitting for a certain period of time. Control Frame Generator When there is a need to stop the transmitting station from the transmission (flow control in full duplex mode), a PAUSE control frame can be send to it. ISSN: Page 133

4 TX/RX Ethernet MAC Interface MAC Control module is connected between the host interface and the Tx and the Rx MAC modules. Signals from the host are passed by to the Tx MAC in certain occasions and vice versa. PAUSE Timer When a PAUSE control frame is received, the pause timer value is written to the PAUSE timer. This prevents the Tx module from transmitting for a»pause timer value«period of slot time. Slot Timer Slot timer measures time slots and generate a pulse to the PAUSE timer for every slot time passed by. MII Management Module The function of this module is to control the PHY and to gather the information from it (status). The MII Management Module consists of four sub modules: Operation Control Module Output Control Module Shift Register Clock Generator Operation Control Module The function of this module is to perform the following commands: Write control data Read status Scan status Output Control Module Controls the signal appearance on the MDO, MCK and MDOEN pins. Shift Register Holds the status read from an external PHY. Clock Generator Generates an appropriate output clock MCK according to the input host clock and the clock divider bits. TRANSMITTER ETHERNET MAC TxEthMAC implements CSMA/CD protocol when transmitting packets of data. Before transmitting packets of data, TxEthMAC must assure that medium is idle and then monitors medium continuously if there is a collision in the middle of transmit process. If collision happened, TxEthernet - MAC makes back off operation and retries to transmit after a random period depends on number of collision attempt. The transmit process can be aborted or dropped if one of the following conditions is detected: excess deferral, occurs when TxEthernet - MAC can't get opportunity to transmit longer than twice maximum length of Ethernet frame late collision, occurs when collision is detected after 512 bits of data has been transmitted excessive collision, ISSN: Page 134

5 occurs when collision is detected more than 15 times under run, occurs when host can't provide nibbles of data for transmit operation excessive length, occurs when the length of packet is longer than 1518 bytes Clock is provided by MII through tx_clk, which frequency is 2.5 MHz when operates at 10 Mbps and 25 MHz when operates at 100 Mbps. Figure 3 Transmitter State Machine The function of this module is to control transmit process. When host has packet of data to be transmitted, tx_sof will be activated. Then, the State Machine will give transmit_new_p signal to restart Defer Counter and Collision Counter and Figure 2 Block Diagram of Transmitter Ethernet MAC wait until transmit_available_p from TX Ethernet MAC consists of IFG Timer is detected to get eleven modules. They are listed below: opportunity to transmit Preamble and 1. FIFO Synchronization SFD. When waiting 2. IFG Timer transmit_available_p, the State 3. Defer Counter Machine monitors excess_deferral to 4. Frame Length Counter limit waiting time for transmit 5. Collision Counter operation. After IFG has passed and 6. Random Number Generator transmit operation has got 7. Back off Timer opportunity, the State Machine will 8. Jam Timer give appropriate data_select signal to 9. CRC Generator Data Multiplexer. 10. Data Multiplexer 11. TX State Machine ISSN: Page 135

6 And it will assert transmit_enable to FIFO Synchronization, Collision Counter, Frame Length Counter, and IFG Timer. The State Machine will also give transmit_preamble to Collision Counter followed by transmit_sfd. The Preamble Field will be transmitted if the transmit_available_p is detected until the next 15 clock cycles then SFD Field will be transmitted for one clock cycle. The Data Field will be transmitted if the value of count_length is greater then 16 until tx_eof is detected. But, the PAD pattern will be transmitted if tx_eof is detected when the value of count_length is less than 136, which is the minimum length of Data field added by Preamble and SFD Field, and will be deactivated if the value of count_length reaches 136. The FCS field will be transmitted if tx_eof is detected and the value of count_length is greater than or equal to 136. If Data Field starts to be transmitted, tx_data_used and compute_crc are asserted. Then, the State Machine will monitor tx_eof that indicates the last nibble of data is placed in tx_data. If tx_eof is detected active and Tx Eth MAC doesn't have to send PAD pattern, the State Machine will give transmit_fcs to Frame Length Counter and deassert compute_crc signal. While transmit operation is running, the State Machine monitors tx_underrun, coll_event_p, and excessive_length continuously. If detected, transmit operation will be aborted or dropped. If coll_event_p is detected, the State Machine will give tx_retransmit and start_backoff pulse signal, and deasserts transmit_enable, compute_crc, and tx_data_used. The following operation is waiting backoff_p and then asserts transmit_enable again to restart transmit operation from the beginning of Preamble Field or abort transmission because late collision and or excessive collision is detected. If transmit operation terminates in normal condition or because any error conditions, the State Machine will dessert transmit_enable and followed by status signal. 3. Results and Conclusions In this project we evaluated the integration of packet switching capabilities in 10 MAC GbE Ethernet Transmitter devices. The MAC architecture was first analyzed to design a switching system that can exploit the processing mechanism of the MAC Ethernet Transmitter layer. In particular, the latency introduced to compute the CRC was used to ISSN: Page 136

implement a classification module that does not add extra latency. The proposed architecture was implemented and validated on a synthesizer.

Modelsim Xilinx Edition will be used for functional simulation and verification of results. Xilinx ISE will be used for Figure 5 Technology Schematic View synthesis.

The Design utilization summary of the Designed Ethernet MAC is shown in Table-1.

7 implement a classification module that does not add extra latency. The proposed architecture was implemented and validated on a synthesizer. Its resource demand was evaluated to address the scalability of the architecture and to detect the most demanding modules. Modelsim Xilinx Edition will be used for functional simulation and verification of results. Xilinx ISE will be used for Figure 5 Technology Schematic View synthesis. Fig 4 & 5 shows the RTL Schematic & technology schematic of the proposed system. Fig 6 Shows the Simulation Result of the proposed system. The Design utilization summary of the Designed Ethernet MAC is shown in Table-1. Figure 6 Transmitter Ethernet MAC Simulation Results- Transmitter Waveform Table-1 Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of Slice Flip Flops % Number of 4 input LUTs % Figure 4 RTL Schematic Number of bonded IOBs % Number of GCLKs % ISSN: Page 137

Acknowledgements The authors would like to thank the anonymous reviewers for their comments which were very helpful in improving the quality and presentation of this paper. References: [1] S.

8 Acknowledgements The authors would like to thank the anonymous reviewers for their comments which were very helpful in improving the quality and presentation of this paper. References: [1] S. GadelRab, 10-Gigabit Ethernet Connectivity for Computer Servers, IEEE Micro, pp , [2] Intel Gigabit Ethernet Controller Datasheet. Intel Datasheet, May [3] IEEE LAN/MAN CSMA/CD (Ethernet) Access Method. IEEE, [4] A. Bianco, R. Birke, G. Botto, M. Chiaberge, J. Finochietto, G. Galante, M. Mellia, F. Neri, and M. Petracca, Boosting the performance of PC-based software routers with FPGAenhanced network interface cards, in Proc. of the 2006 IEEE Workshop on High Performance Switching and Routing (HPSR 2006), Poznan, Poland, 2006, pp [5] J. Shafer and S. Rixner, RiceNIC: A reconfigurable network interface for experimental research and education, in Proceedings of the Workshop on Experimental Computer Science,2007. [6] J. Lockwood, N. McKeown, G. Watson, G. Gibb, P. Hartke,J. Naous, R.Raghuraman, and J. Luo, NetFPGA-an open platform for gigabit-rate network switching and routing, in IEEE International Conference on Microelectronic Systems Education, [7] H. J. Chao and B. Liu, High Performance Switches and Routers. Hoboken, New Jersey: John Wiley & Sons Inc.,2007. [8] Ethernet 10GbE MAC, in Authors Profile: BOLLEDDU ALEKYA is Pursuing her M. Tech from Chirala Engineering College, Chirala in the department of Electronics & Communications Engineering (ECE) with specialization in VLSI & Embedded Systems P. Bala Nagu is working as an Associate Professor in the department of Electronics & Communication Engineering in Chirala Engineering College,Chirala. He has Nine years of teaching experience along with one year industrial experience. ISSN: Page 138

ETHERNET IP CORE VERIFICATION USING SYSTEM VERILOG HDL

ETHERNET IP CORE VERIFICATION USING SYSTEM VERILOG HDL Ms. P. Abinaya Ms. M. Janani Abstract Functional verification of IP is an essential process in the chip/ System on Chip (SoC) design process, since