Communication Frameworks for HPC and Big Data

Transcription

1 Communication Frameworks for HPC and Big Data Talk at HPC Advisory Council Spain Conference (215) by Dhabaleswar K. (DK) Panda The Ohio State University

2 High-End Computing (HEC): PetaFlop to ExaFlop 1-2 PFlops in EFlops in ? 2

3 Number of Clusters Percentage of Clusters Trends for Commodity Computing Clusters in the Top 5 List ( Percentage of Clusters Number of Clusters 87% Timeline 3

4 Drivers of Modern HPC Cluster Architectures Multi-core Processors High Performance Interconnects - InfiniBand <1usec latency, >1Gbps Bandwidth Accelerators / Coprocessors high compute density, high performance/watt >1 TFlop DP on a chip Multi-core processors are ubiquitous InfiniBand very popular in HPC clusters Accelerators/Coprocessors becoming common in high-end systems Pushing the envelope for Exascale computing Tianhe 2 Titan Stampede Tianhe 1A 4

5 Large-scale InfiniBand Installations 259 IB Clusters (51%) in the June 215 Top5 list ( Installations in the Top 5 (24 systems): 519,64 cores (Stampede) at TACC (8 th ) 76,32 cores (Tsubame 2.5) at Japan/GSIC (22 nd ) 185,344 cores (Pleiades) at NASA/Ames (11 th ) 194,616 cores (Cascade) at PNNL (25 th ) 72,8 cores Cray CS-Storm in US (13 th ) 76,32 cores (Makman-2) at Saudi Aramco (28 th ) 72,8 cores Cray CS-Storm in US (14 th ) 11,4 cores (Pangea) in France (29 th ) 265,44 cores SGI ICE at Tulip Trading Australia (15 th ) 37,12 cores (Lomonosov-2) at Russia/MSU (31 st ) 124,2 cores (Topaz) SGI ICE at ERDC DSRC in US (16 th ) 57,6 cores (SwiftLucy) in US (33 rd ) 72, cores (HPC2) in Italy (17 th ) 5,544 cores (Occigen) at France/GENCI-CINES (36 th ) 115,668 cores (Thunder) at AFRL/USA (19 th ) 76,896 cores (Salomon) SGI ICE in Czech Republic (4 th ) 147,456 cores (SuperMUC) in Germany (2 th ) 73,584 cores (Spirit) at AFRL/USA (42 nd ) 86,16 cores (SuperMUC Phase 2) in Germany (21 st ) and many more! 5

6 Two Major Categories of Applications Scientific Computing Message Passing Interface (MPI), including MPI + OpenMP, is the Dominant Programming Model Many discussions towards Partitioned Global Address Space (PGAS) UPC, OpenSHMEM, CAF, etc. Hybrid Programming: MPI + PGAS (OpenSHMEM, UPC) Big Data/Enterprise/Commercial Computing Focuses on large data and data analysis Hadoop (HDFS, HBase, MapReduce) Spark is emerging for in-memory computing Memcached is also used for Web 2. 6

7 Towards Exascale System (Today and Target) Systems 215 Tianhe Difference Today & Exascale System peak 55 PFlop/s 1 EFlop/s ~2x Power System memory Node performance 18 MW (3 Gflops/W) 1.4 PB (1.24PB CPU +.384PB CoP) 3.43TF/s (.4 CPU + 3 CoP) Node concurrency 24 core CPU cores CoP ~2 MW (5 Gflops/W) O(1) ~15x PB ~5X 1.2 or 15 TF O(1) O(1k) or O(1k) ~5x - ~5x Total node interconnect BW 6.36 GB/s 2 4 GB/s ~4x -~6x System size (nodes) 16, O(1,) or O(1M) ~6x - ~6x Total concurrency 3.12M 12.48M threads (4 /core) O(billion) for latency hiding MTTI Few/day Many/day O(?) ~1x Courtesy: Prof. Jack Dongarra 7

8 Parallel Programming Models Overview P1 P2 P3 P1 P2 P3 P1 P2 P3 Shared Memory Memory Memory Memory Logical shared memory Memory Memory Memory Shared Memory Model SHMEM, DSM Distributed Memory Model MPI (Message Passing Interface) Partitioned Global Address Space (PGAS) Global Arrays, UPC, Chapel, X1, CAF, Programming models provide abstract machine models Models can be mapped on different types of systems e.g. Distributed Shared Memory (DSM), MPI within a node, etc. 8

9 Partitioned Global Address Space (PGAS) Models Key features - Simple shared memory abstractions - Light weight one-sided communication - Easier to express irregular communication Different approaches to PGAS - Languages Unified Parallel C (UPC) Co-Array Fortran (CAF) X1 Chapel - Libraries OpenSHMEM Global Arrays 9

10 Hybrid (MPI+PGAS) Programming Application sub-kernels can be re-written in MPI/PGAS based on communication characteristics Benefits: Best of Distributed Computing Model Best of Shared Memory Computing Model Exascale Roadmap*: Hybrid Programming is a practical way to program exascale systems HPC Application Kernel 1 MPI Kernel 2 PGAS MPI Kernel 3 MPI Kernel N PGAS MPI * The International Exascale Software Roadmap, Dongarra, J., Beckman, P. et al., Volume 25, Number 1, 211, International Journal of High Performance Computer Applications, ISSN

11 Designing Communication Libraries for Multi- Petaflop and Exaflop Systems: Challenges Application Kernels/Applications Middleware Programming Models MPI, PGAS (UPC, Global Arrays, OpenSHMEM), CUDA, OpenMP, OpenACC, Cilk, Hadoop (MapReduce), Spark (RDD, DAG), etc. Co-Design Opportunities and Challenges across Various Layers Point-to-point Communication (two-sided and one-sided Communication Library or Runtime for Programming Models Collective Communication Energy- Awareness Synchronization and Locks I/O and File Systems Fault Tolerance Performance Scalability Fault- Resilience Networking Technologies (InfiniBand, 4/1GigE, Aries, and OmniPath) Multi/Many-core Architectures Accelerators (NVIDIA and MIC) 11

12 Broad Challenges in Designing Communication Libraries for (MPI+X) at Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided) Scalable Collective communication Offload Non-blocking Topology-aware Balancing intra-node and inter-node communication for next generation multi-core ( cores/node) Multiple end-points per node Support for efficient multi-threading Integrated Support for GPGPUs and Accelerators Fault-tolerance/resiliency QoS support for communication and I/O Support for Hybrid MPI+PGAS programming (MPI + OpenMP, MPI + UPC, MPI + OpenSHMEM, CAF, ) Virtualization Energy-Awareness 12

13 Additional Challenges for Designing Exascale Software Libraries Extreme Low Memory Footprint Memory per core continues to decrease D-L-A Framework Discover Overall network topology (fat-tree, 3D, ) Network topology for processes for a given job Node architecture Health of network and node Learn Impact on performance and scalability Potential for failure Adapt Internal protocols and algorithms Process mapping Fault-tolerance solutions Low overhead techniques while delivering performance, scalability and faulttolerance 13

14 MVAPICH2 Software High Performance open-source MPI Library for InfiniBand, 1-4Gig/iWARP, and RDMA over Converged Enhanced Ethernet (RoCE) MVAPICH (MPI-1), MVAPICH2 (MPI-2.2 and MPI-3.), Available since 22 MVAPICH2-X (MPI + PGAS), Available since 211 Support for GPGPUs (MVAPICH2-GDR) and MIC (MVAPICH2-MIC), Available since 214 Support for Virtualization (MVAPICH2-Virt), Available since 215 Support for Energy-Awareness (MVAPICH2-EA), Available since 215 Used by more than 2,45 organizations in 76 countries More than 286, downloads from the OSU site directly Empowering many TOP5 clusters (June 15 ranking) 8 th ranked 519,64-core cluster (Stampede) at TACC 11 th ranked 185,344-core cluster (Pleiades) at NASA 22 nd ranked 76,32-core cluster (Tsubame 2.5) at Tokyo Institute of Technology and many others Available with software stacks of many vendors and Linux Distros (RedHat and SuSE) Empowering Top5 systems for over a decade System-X from Virginia Tech (3 rd in Nov 23, 2,2 processors, TFlops) -> Stampede at TACC (8 th in Jun 15, 519,64 cores, Plops) 14

15 MVAPICH2 Software Family Requirements MVAPICH2 Library to use MPI with IB, iwarp and RoCE MVAPICH2 Advanced MPI, OSU INAM, PGAS and MPI+PGAS with IB and RoCE MPI with IB & GPU MVAPICH2-X MVAPICH2-GDR MPI with IB & MIC MVAPICH2-MIC HPC Cloud with MPI & IB MVAPICH2-Virt Energy-aware MPI with IB, iwarp and RoCE MVAPICH2-EA 15

16 Overview of A Few Challenges being Addressed by MVAPICH2 Project for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimal memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 16

17 Latency (us) Bandwidth (MBytes/sec) Latency & Bandwidth: MPI over IB with MVAPICH Small Message Latency Unidirectional Bandwidth Message Size (bytes) Message Size (bytes) TrueScale-QDR GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switch ConnectX-3-FDR GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switch ConnectIB-Dual FDR GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switch ConnectX-4-EDR GHz Deca-core (IvyBridge) Intel PCI Gen3 Back-to-back 17

18 Bandwidth (MB/s) Bandwidth (MB/s) Latency (us) MVAPICH2 Two-Sided Intra-Node Performance (Shared memory and Kernel-based Zero-copy Support (LiMIC and CMA)) Latency Intra-Socket Inter-Socket.45 us.18 us K Message Size (Bytes) Latest MVAPICH2 2.2a Intel Ivy-bridge Bandwidth (Intra-socket) intra-socket-cma intra-socket-shmem intra-socket-limic Bandwidth (Inter-socket) 14,25 MB/s inter-socket-cma 13,749 MB/s 12 inter-socket-shmem 1 inter-socket-limic Message Size (Bytes) Message Size (Bytes) 18

19 Connection Memory (KB) Normalized Execution Time Node 2 P4 P5 Node P P1 Minimizing Memory Footprint further by DC Transport Node 3 P6 P IB Network Node 1 P2 P3 Constant connection cost (One QP for any peer) Full Feature Set (RDMA, Atomics etc) Separate objects for send (DC Initiator) and receive (DC Target) DC Target identified by DCT Number Messages routed with (DCT Number, LID) Requires same DC Key to enable communication Available with MVAPICH2-X 2.2a DCT support available in Mellanox OFED Memory Footprint for Alltoall NAMD - Apoa1: Large data set RC DC-Pool UD XRC RC DC-Pool 97 UD XRC Number of Processes Number of Processes H. Subramoni, K. Hamidouche, A. Venkatesh, S. Chakraborty and D. K. Panda, Designing MPI Library with Dynamic Connected Transport (DCT) of InfiniBand : Early Experiences. IEEE International Supercomputing Conference (ISC 14).

20 Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimum memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 2

21 Latency (us) Latency (us) Latency (us) Latency (us) Hardware Multicast-aware MPI_Bcast on Stampede Small Messages (12,4 Cores) Default Multicast Message Size (Bytes) Default 16 Byte Message Multicast Large Messages (12,4 Cores) Default Multicast 2K 8K 32K 128K Message Size (Bytes) 32 KByte Message Default Multicast Number of Nodes Number of Nodes ConnectX-3-FDR (54 Gbps): 2.7 GHz Dual Octa-core (SandyBridge) Intel PCI Gen3 with Mellanox IB FDR switch 21

22 Run-Time (s) Application Run-Time (s) Normalized Performance Co-Design with MPI-3 Non-Blocking Collectives and Collective Offload Co-Direct Hardware (Available with MVAPICH2-X 2.2a) % Data Size Modified P3DFFT with Offload-Alltoall does up to 17% better than default version (128 Processes) HPL-Offload HPL-1ring HPL-Host 4.5% HPL Problem Size (N) as % of Total Memory Modified HPL with Offload-Bcast does up to 4.5% better than default version (512 Processes) PCG-Default Modified-PCG-Offload % Number of Processes Modified Pre-Conjugate Gradient Solver with Offload-Allreduce does up to 21.8% better than default version K. Kandalla, et. al.. High-Performance and Scalable Non-Blocking All-to-All with Collective Offload on InfiniBand Clusters: A Study with Parallel 3D FFT, ISC 211 K. Kandalla, et. al, Designing Non-blocking Broadcast with Collective Offload on InfiniBand Clusters: A Case Study with HPL, HotI 211 K. Kandalla, et. al., Designing Non-blocking Allreduce with Collective Offload on InfiniBand Clusters: A Case Study with Conjugate Gradient Solvers, IPDPS 12 Can Network-Offload based Non-Blocking Neighborhood MPI Collectives Improve Communication Overheads of Irregular Graph Algorithms? K. Kandalla, A. Buluc, H. Subramoni, K. Tomko, J. Vienne, L. Oliker, and D. K. Panda, IWPAPS 12 22

23 Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimum memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs MPI-T Interface Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 23

24 MPI + CUDA - Naive Data movement in applications with standard MPI and CUDA interfaces At Sender: CPU cudamemcpy(s_hostbuf, s_devbuf,...); MPI_Send(s_hostbuf, size,...); At Receiver: MPI_Recv(r_hostbuf, size,...); cudamemcpy(r_devbuf, r_hostbuf,...); PCIe GPU NIC Switch High Productivity and Low Performance 24

25 MPI + CUDA - Advanced Pipelining at user level with non-blocking MPI and CUDA interfaces At Sender: for (j = ; j < pipeline_len; j++) cudamemcpyasync(s_hostbuf + j * blk, s_devbuf + j * blksz, ); for (j = ; j < pipeline_len; j++) { } while (result!= cudasucess) { } result = cudastreamquery( ); if(j > ) MPI_Test( ); MPI_Isend(s_hostbuf + j * block_sz, blksz...); MPI_Waitall(); <<Similar at receiver>> CPU PCIe GPU NIC Switch Low Productivity and High Performance 25

26 GPU-Aware MPI Library: MVAPICH2-GPU Standard MPI interfaces used for unified data movement Takes advantage of Unified Virtual Addressing (>= CUDA 4.) Overlaps data movement from GPU with RDMA transfers At Sender: MPI_Send(s_devbuf, size, ); inside MVAPICH2 At Receiver: MPI_Recv(r_devbuf, size, ); High Performance and High Productivity 26

27 CUDA-Aware MPI: MVAPICH Releases Support for MPI communication from NVIDIA GPU device memory High performance RDMA-based inter-node point-to-point communication (GPU-GPU, GPU-Host and Host-GPU) High performance intra-node point-to-point communication for multi-gpu adapters/node (GPU-GPU, GPU-Host and Host-GPU) Taking advantage of CUDA IPC (available since CUDA 4.1) in intra-node communication for multiple GPU adapters/node Optimized and tuned collectives for GPU device buffers MPI datatype support for point-to-point and collective communication from GPU device buffers 27

28 GPU-Direct RDMA (GDR) with CUDA OFED with support for GPUDirect RDMA is developed by NVIDIA and Mellanox OSU has a design of MVAPICH2 using GPUDirect RDMA Hybrid design using GPU-Direct RDMA GPUDirect RDMA and Host-based pipelining Alleviates P2P bandwidth bottlenecks on SandyBridge and IvyBridge Support for communication using multi-rail Support for Mellanox Connect-IB and ConnectX VPI adapters Support for RoCE with Mellanox ConnectX VPI adapters IB Adapter SNB E5-267 / IVB E5-268V2 CPU Chipset SNB E5-267 P2P write: 5.2 GB/s P2P read: < 1. GB/s IVB E5-268V2 P2P write: 6.4 GB/s P2P read: 3.5 GB/s System Memory GPU GPU Memory 28

29 Bi-Bandwidth (MB/s) Latency (us) Bandwidth (MB/s) Performance of MVAPICH2-GDR with GPU-Direct-RDMA GPU-GPU Internode Small Message Latency 3 MV2-GDR2.1RC2 25 MV2-GDR2.b 2 MV2 w/o GDR X 3.5X 2.15 usec K Message Size (bytes) GPU-GPU Internode Bi-directional Bandwidth 45 4 MV2-GDR2.1RC2 MV2-GDR2.b 35 MV2 w/o GDR 2x x K 4K Message Size (bytes) GPU-GPU Internode MPI Uni-Directional Bandwidth 35 MV2-GDR2.1RC2 3 MV2-GDR2.b 25 MV2 w/o GDR 11x X K 4K Message Size (bytes) MVAPICH2-GDR-2.1RC2 Intel Ivy Bridge (E5-268 v2) node - 2 cores NVIDIA Tesla K4c GPU Mellanox Connect-IB Dual-FDR HCA CUDA 7 Mellanox OFED 2.4 with GPU-Direct-RDMA 29

30 Application-Level Evaluation (HOOMD-blue) Platform: Wilkes (Intel Ivy Bridge + NVIDIA Tesla K2c + Mellanox Connect-IB) HoomdBlue Version 1..5 GDRCOPY enabled: MV2_USE_CUDA=1 MV2_IBA_HCA=mlx5_ MV2_IBA_EAGER_THRESHOLD=32768 MV2_VBUF_TOTAL_SIZE=32768 MV2_USE_GPUDIRECT_LOOPBACK_LIMIT=32768 MV2_USE_GPUDIRECT_GDRCOPY=1 MV2_USE_GPUDIRECT_GDRCOPY_LIMIT=

31 Using MVAPICH2-GDR Version MVAPICH2-GDR 2.1RC2 with GDR support can be downloaded from System software requirements Mellanox OFED 2.1 or later NVIDIA Driver or later NVIDIA CUDA Toolkit 6. or later Plugin for GPUDirect RDMA Strongly Recommended : use the new GDRCOPY module from NVIDIA Has optimized designs for point-to-point communication using GDR Contact MVAPICH help list with any questions related to the package mvapich-help@cse.ohio-state.edu HPCAC Brazil Conference (Aug 15) 31

32 Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimum memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 32

33 MPI Applications on MIC Clusters Flexibility in launching MPI jobs on clusters with Xeon Phi Xeon Xeon Phi Multi-core Centric Host-only MPI Program Offload (/reverse Offload) MPI Program Offloaded Computation Symmetric MPI Program MPI Program Coprocessor-only Many-core Centric MPI Program 33

34 MVAPICH2-MIC 2. Design for Clusters with IB and MIC Offload Mode Intranode Communication Coprocessor-only and Symmetric Mode Internode Communication Coprocessors-only and Symmetric Mode Multi-MIC Node Configurations Running on three major systems Stampede, Blueridge (Virginia Tech) and Beacon (UTK) 34

35 Latency (usec) Bandwidth (MB/sec) Better Latency (usec) Bandwidth (MB/sec) Better MIC-Remote-MIC P2P Communication with Proxy-based Communication Latency (Large Messages) 8K 32K 128K 512K 2M Message Size (Bytes) Latency (Large Messages) 8K 32K 128K 512K 2M Message Size (Bytes) Intra-socket P2P Better Inter-socket P2P Better Bandwidth K 64K 1M Message Size (Bytes) Bandwidth K 64K 1M Message Size (Bytes)

36 Latency (usecs) x 1 Execution Time (secs) Latency (usecs) Latency (usecs)x 1 Optimized MPI Collectives for MIC Clusters (Allgather & Alltoall) Node-Allgather (16H + 16 M) Small Message Latency MV2-MIC MV2-MIC-Opt 76% Node-Allgather (8H + 8 M) Large Message Latency MV2-MIC MV2-MIC-Opt 58% K Message Size (Bytes) 32-Node-Alltoall (8H + 8 M) Large Message Latency MV2-MIC MV2-MIC-Opt 55% K 16K 32K 64K 128K 256K 512K 1M Message Size (Bytes) P3DFFT Performance Communication Computation MV2-MIC-Opt MV2-MIC 4K 8K 16K 32K 64K 128K 256K 512K 32 Nodes (8H + 8M), Size = 2K*2K*1K Message Size (Bytes) A. Venkatesh, S. Potluri, R. Rajachandrasekar, M. Luo, K. Hamidouche and D. K. Panda - High Performance Alltoall and Allgather designs for InfiniBand MIC Clusters; IPDPS 14, May

37 Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimum memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 37

38 MVAPICH2-X for Advanced MPI and Hybrid MPI + PGAS Applications MPI, OpenSHMEM, UPC, CAF or Hybrid (MPI + PGAS) Applications OpenSHMEM Calls CAF Calls UPC Calls MPI Calls Unified MVAPICH2-X Runtime InfiniBand, RoCE, iwarp Unified communication runtime for MPI, UPC, OpenSHMEM, CAF available with MVAPICH2-X 1.9 (212) onwards! Feature Highlights Supports MPI(+OpenMP), OpenSHMEM, UPC, CAF, MPI(+OpenMP) + OpenSHMEM, MPI(+OpenMP) + UPC MPI-3 compliant, OpenSHMEM v1. standard compliant, UPC v1.2 standard compliant (with initial support for UPC 1.3), CAF 28 standard (OpenUH) Scalable Inter-node and intra-node communication point-to-point and collectives 38

39 Time (s) Time (seconds) Application Level Performance with Graph5 and Sort MPI-Simple MPI-CSC MPI-CSR Graph5 Execution Time Hybrid (MPI+OpenSHMEM) 7.6X 4K 8K 16K No. of Processes Performance of Hybrid (MPI+ OpenSHMEM) Graph5 Design 8,192 processes - 2.4X improvement over MPI-CSR - 7.6X improvement over MPI-Simple 16,384 processes - 1.5X improvement over MPI-CSR - 13X improvement over MPI-Simple 13X Sort Execution Time J. Jose, K. Kandalla, S. Potluri, J. Zhang and D. K. Panda, Optimizing Collective Communication in OpenSHMEM, Int'l Conference on Partitioned Global Address Space Programming Models (PGAS '13), October 213. J. Jose, S. Potluri, K. Tomko and D. K. Panda, Designing Scalable Graph5 Benchmark with Hybrid MPI+OpenSHMEM Programming Models, International Supercomputing Conference (ISC 13), June 213 J. Jose, K. Kandalla, M. Luo and D. K. Panda, Supporting Hybrid MPI and OpenSHMEM over InfiniBand: Design and Performance Evaluation, Int'l Conference on Parallel Processing (ICPP '12), September MPI Hybrid 5GB-512 1TB-1K 2TB-2K 4TB-4K Input Data - No. of Processes 51% Performance of Hybrid (MPI+OpenSHMEM) Sort Application 4,96 processes, 4 TB Input Size - MPI 248 sec;.16 TB/min - Hybrid 1172 sec;.36 TB/min - 51% improvement over MPI-design 39

40 Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimum memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 4

41 Can HPC and Virtualization be Combined? Virtualization has many benefits Job migration Compaction Not very popular in HPC due to overhead associated with Virtualization New SR-IOV (Single Root IO Virtualization) support available with Mellanox InfiniBand adapters Enhanced MVAPICH2 support for SR-IOV Publicly available as MVAPICH2-Virt library J. Zhang, X. Lu, J. Jose, R. Shi and D. K. Panda, Can Inter-VM Shmem Benefit MPI Applications on SR-IOV based Virtualized InfiniBand Clusters? EuroPar'14 J. Zhang, X. Lu, J. Jose, M. Li, R. Shi and D.K. Panda, High Performance MPI Libray over SR-IOV enabled InfiniBand Clysters, HiPC 14 J. Zhang, X.Lu, M. Arnold and D. K. Panda, MVAPICH2 Over OpenStack with SR-IOV: an Efficient Approach to build HPC Clouds, CCGrid 15 41

42 Execution Time (s) Execution Time (us) Application-Level Performance (8 VM * 8 Core/VM) MV2-SR-IOV-Def MV2-SR-IOV-Opt MV2-Native 9% MV2-SR-IOV-Def MV2-SR-IOV-Opt MV2-Native 9% % % FT-64-C EP-64-C LU-64-C BT-64-C NAS Class C NAS 2,1 2,16 2,2 22,1 22,16 22,2 Problem Size (Scale, Edgefactor) Graph5 Compared to Native, 1-9% overhead for NAS Compared to Native, 4-9% overhead for Graph5 65

43 NSF Chameleon Cloud: A Powerful and Flexible Experimental Instrument Large-scale instrument Targeting Big Data, Big Compute, Big Instrument research ~65 nodes (~14,5 cores), 5 PB disk over two sites, 2 sites connected with 1G network Reconfigurable instrument Bare metal reconfiguration, operated as single instrument, graduated approach for ease-of-use Connected instrument Workload and Trace Archive Partnerships with production clouds: CERN, OSDC, Rackspace, Google, and others Partnerships with users Complementary instrument Complementing GENI, Grid 5, and other testbeds Sustainable instrument Industry connections 43

44 Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimum memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 44

45 Energy-Aware MVAPICH2 & OSU Energy Management Tool (OEMT) MVAPICH2-EA (Energy-Aware) A white-box approach New Energy-Efficient communication protocols for pt-pt and collective operations Intelligently apply the appropriate Energy saving techniques Application oblivious energy saving OEMT A library utility to measure energy consumption for MPI applications Works with all MPI runtimes PRELOAD option for precompiled applications Does not require ROOT permission: A safe kernel module to read only a subset of MSRs 45

46 MV2-EA : Application Oblivious Energy-Aware-MPI (EAM) An energy efficient runtime that provides energy savings without application knowledge Uses automatically and transparently the best energy lever Provides guarantees on maximum degradation with 5-41% savings at <= 5% degradation Pessimistic MPI applies energy reduction lever to each MPI call 1 A Case for Application-Oblivious Energy-Efficient MPI Runtime A. Venkatesh, A. Vishnu, K. Hamidouche, N. Tallent, D. K. Panda, D. Kerbyson, and A. Hoise - Supercomputing 15, Nov 215 [Best Student Paper Finalist] 46

47 Overview of A Few Challenges being Addressed by MVAPICH2/MVAPICH2-X for Exascale Scalability for million to billion processors Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided RMA) Extremely minimum memory footprint Collective communication Hardware-multicast-based Offload and Non-blocking Integrated Support for GPGPUs Integrated Support for Intel MICs Unified Runtime for Hybrid MPI+PGAS programming (MPI + OpenSHMEM, MPI + UPC, CAF, ) Virtualization Energy-Awareness InfiniBand Network Analysis and Monitoring (INAM) 47

48 OSU InfiniBand Network Analysis Monitoring Tool (INAM) Network Level View Full Network (152 nodes) Zoomed-in View of the Network Show network topology of large clusters Visualize traffic pattern on different links Quickly identify congested links/links in error state See the history unfold play back historical state of the network 48

49 Upcoming OSU INAM Tool Job and Node Level Views Visualizing a Job (5 Nodes) Finding Routes Between Nodes Job level view Show different network metrics (load, error, etc.) for any live job Play back historical data for completed jobs to identify bottlenecks Node level view provides details per process or per node CPU utilization for each rank/node Bytes sent/received for MPI operations (pt-to-pt, collective, RMA) Network metrics (e.g. XmitDiscard, RcvError) per rank/node 49

50 MVAPICH2 Plans for Exascale Performance and Memory scalability toward 5K-1M cores Dynamically Connected Transport (DCT) service with Connect-IB Hybrid programming (MPI + OpenSHMEM, MPI + UPC, MPI + CAF ) Enhanced Optimization for GPU Support and Accelerators Taking advantage of advanced features User Mode Memory Registration (UMR) On-demand Paging Enhanced Inter-node and Intra-node communication schemes for upcoming OmniPath enabled Knights Landing architectures Extended RMA support (as in MPI 3.) Extended topology-aware collectives Energy-aware point-to-point (one-sided and two-sided) and collectives Extended Support for MPI Tools Interface (as in MPI 3.) Extended Checkpoint-Restart and migration support with SCR 5

51 Two Major Categories of Applications Scientific Computing Message Passing Interface (MPI), including MPI + OpenMP, is the Dominant Programming Model Many discussions towards Partitioned Global Address Space (PGAS) UPC, OpenSHMEM, CAF, etc. Hybrid Programming: MPI + PGAS (OpenSHMEM, UPC) Big Data/Enterprise/Commercial Computing Focuses on large data and data analysis Hadoop (HDFS, HBase, MapReduce) Spark is emerging for in-memory computing Memcached is also used for Web 2. 51

52 Can High-Performance Interconnects Benefit Big Data Computing? Most of the current Big Data systems use Ethernet Infrastructure with Sockets Concerns for performance and scalability Usage of High-Performance Networks is beginning to draw interest What are the challenges? Where do the bottlenecks lie? Can these bottlenecks be alleviated with new designs (similar to the designs adopted for MPI)? Can HPC Clusters with High-Performance networks be used for Big Data applications using Hadoop and Memcached? 52

53 Designing Communication and I/O Libraries for Big Data Systems: Solved a Few Initial Challenges Applications Benchmarks Big Data Middleware (HDFS, MapReduce, HBase, Spark and Memcached) Upper level Changes? Programming Models (Sockets) Other RDMA Protocols? Point-to-Point Communication Communication and I/O Library Threaded Models and Synchronization Virtualization I/O and File Systems QoS Fault-Tolerance Networking Technologies (InfiniBand, 1/1/4GigE and Intelligent NICs) Commodity Computing System Architectures (Multi- and Many-core architectures and accelerators) Storage Technologies (HDD and SSD) 53

54 Design Overview of HDFS with RDMA Applications Design Features Others HDFS Write RDMA-based HDFS write RDMA-based HDFS replication Java Socket Interface Java Native Interface (JNI) Parallel replication support OSU Design On-demand connection setup 1/1 GigE, IPoIB Network Verbs RDMA Capable Networks (IB, 1GE/ iwarp, RoCE..) InfiniBand/RoCE support Enables high performance RDMA communication, while supporting traditional socket interface JNI Layer bridges Java based HDFS with communication library written in native code 54

55 Communication Time (s) Communication Times in HDFS GigE IPoIB (QDR) OSU-IB (QDR) 15 1 Reduced by 3% 5 Cluster with HDD DataNodes 2GB 4GB 6GB 8GB 1GB File Size (GB) 3% improvement in communication time over IPoIB (QDR) 56% improvement in communication time over 1GigE Similar improvements are obtained for SSD DataNodes N. S. Islam, M. W. Rahman, J. Jose, R. Rajachandrasekar, H. Wang, H. Subramoni, C. Murthy and D. K. Panda, High Performance RDMA-Based Design of HDFS over InfiniBand, Supercomputing (SC), Nov 212 N. Islam, X. Lu, W. Rahman, and D. K. Panda, SOR-HDFS: A SEDA-based Approach to Maximize Overlapping in RDMA-Enhanced HDFS, HPDC '14, June

56 Enhanced HDFS with In-memory and Heterogeneous Storage Hybrid Replication Applications Triple-H Data Placement Policies Eviction/ Promotion Heterogeneous Storage RAM Disk SSD HDD Lustre Design Features Three modes Default (HHH) In-Memory (HHH-M) Lustre-Integrated (HHH-L) Policies to efficiently utilize the heterogeneous storage devices RAM, SSD, HDD, Lustre Eviction/Promotion based on data usage pattern Hybrid Replication Lustre-Integrated mode: Lustre-based fault-tolerance N. Islam, X. Lu, M. W. Rahman, D. Shankar, and D. K. Panda, Triple-H: A Hybrid Approach to Accelerate HDFS on HPC Clusters with Heterogeneous Storage Architecture, CCGrid 15, May

57 Total Throughput (MBps) Execution Time (s) Performance Improvement on TACC Stampede (HHH) 6 5 IPoIB (FDR) OSU-IB (FDR) Increased by 7x Increased by 2x 3 25 IPoIB (FDR) OSU-IB (FDR) Reduced by 3x write read TestDFSIO 8:3 16:6 32:12 Cluster Size:Data Size RandomWriter For 16GB TestDFSIO in 32 nodes For 12GB RandomWriter in 32 Write Throughput: 7x improvement nodes over IPoIB (FDR) 3x improvement over IPoIB (QDR) Read Throughput: 2x improvement over IPoIB (FDR) 57

58 Execution Time (s) Execution Time (s) Evaluation with Spark on SDSC Gordon (HHH) IPoIB (QDR) OSU-IB (QDR) 8:5 16:1 32:2 Cluster Size : Data Size (GB) TeraGen Reduced by 2.1x For 2GB TeraGen on 32 nodes Spark-TeraGen: HHH has 2.1x improvement over HDFS-IPoIB (QDR) Spark-TeraSort: HHH has 16% improvement over HDFS-IPoIB (QDR) IPoIB (QDR) OSU-IB (QDR) 8:5 16:1 32:2 Cluster Size : Data Size (GB) TeraSort Reduced by 16% N. Islam, M. W. Rahman, X. Lu, D. Shankar, and D. K. Panda, Performance Characterization and Acceleration of In- Memory File Systems for Hadoop and Spark Applications on HPC Clusters, IEEE BigData 15, October

59 Design Overview of MapReduce with RDMA Java Socket Interface MapReduce Job Tracker 1/1 GigE, IPoIB Network Applications Task Tracker Map Reduce Java Native Interface (JNI) OSU Design Verbs RDMA Capable Networks (IB, 1GE/ iwarp, RoCE..) Design Features RDMA-based shuffle Prefetching and caching map output Efficient Shuffle Algorithms In-memory merge On-demand Shuffle Adjustment Advanced overlapping map, shuffle, and merge shuffle, merge, and reduce On-demand connection setup InfiniBand/RoCE support Enables high performance RDMA communication, while supporting traditional socket interface JNI Layer bridges Java based MapReduce with communication library written in native code 59

60 Job Execution Time (sec) Job Execution Time (sec) Performance Evaluation of Sort and TeraSort 12 1 IPoIB (QDR) UDA-IB (QDR) OSU-IB (QDR) 7 IPoIB (FDR) UDA-IB (FDR) OSU-IB (FDR) Data Size: 6 GB Data Size: 12 GB Data Size: 24 GB Data Size: 8 GB Data Size: 16 GBData Size: 32 GB Cluster Size: 16 Cluster Size: 32 Cluster Size: 64 Cluster Size: 16 Cluster Size: 32 Cluster Size: 64 Sort in OSU Cluster TeraSort in TACC Stampede For 24GB Sort in 64 nodes (512 cores) 4% improvement over IPoIB (QDR) with HDD used for HDFS For 32GB TeraSort in 64 nodes (1K cores) 38% improvement over IPoIB (FDR) with HDD used for HDFS 6

61 Design Overview of Shuffle Strategies for MapReduce over Lustre Map 1 Map 2 Map 3 In-memory merge/sort Intermediate Data Directory Lustre Lustre Read / RDMA Reduce 1 Reduce 2 reduce In-memory merge/sort reduce Design Features Two shuffle approaches Lustre read based shuffle RDMA based shuffle Hybrid shuffle algorithm to take benefit from both shuffle approaches Dynamically adapts to the better shuffle approach for each shuffle request based on profiling values for each Lustre read operation In-memory merge and overlapping of different phases are kept similar to RDMAenhanced MapReduce design M. W. Rahman, X. Lu, N. S. Islam, R. Rajachandrasekar, and D. K. Panda, High Performance Design of YARN MapReduce on Modern HPC Clusters with Lustre and RDMA, IPDPS, May

62 Job Execution Time (sec) Job Execution Time (sec) Performance Improvement of MapReduce over Lustre on TACC-Stampede Local disk is used as the intermediate data directory Reduced by 44% IPoIB (FDR) OSU-IB (FDR) IPoIB (FDR) OSU-IB (FDR) Reduced by 48% GB 4 GB 8 GB 16 GB 32 GB 64 GB Data Size (GB) Cluster: 4 Cluster: 8 Cluster: 16 Cluster: 32 Cluster: 64 Cluster: 128 For 5GB Sort in 64 nodes For 64GB Sort in 128 nodes 44% improvement over IPoIB (FDR) 48% improvement over IPoIB (FDR) M. W. Rahman, X. Lu, N. S. Islam, R. Rajachandrasekar, and D. K. Panda, MapReduce over Lustre: Can RDMAbased Approach Benefit?, Euro-Par, August

63 Design Overview of Spark with RDMA Design Features RDMA based shuffle SEDA-based plugins Dynamic connection management and sharing Non-blocking and out-oforder data transfer Off-JVM-heap buffer management InfiniBand/RoCE support Enables high performance RDMA communication, while supporting traditional socket interface JNI Layer bridges Scala based Spark with communication library written in native code X. Lu, M. W. Rahman, N. Islam, D. Shankar, and D. K. Panda, Accelerating Spark with RDMA for Big Data Processing: Early Experiences, Int'l Symposium on High Performance Interconnects (HotI'14), August

64 Time (sec) Time (sec) Performance Evaluation on TACC Stampede - SortByTest IPoIB RDMA 77% IPoIB RDMA 58% Data Size (GB) Worker Nodes, SortByTest Shuffle Time 16 Worker Nodes, SortByTest Total Time Intel SandyBridge + FDR, 16 Worker Nodes, 256 Cores, (256M 256R) RDMA-based design for Spark 1.4. RDMA vs. IPoIB with 256 concurrent tasks, single disk per node and RamDisk. For SortByKey Test: Shuffle time reduced by up to 77% over IPoIB (56Gbps) Total time reduced by up to 58% over IPoIB (56Gbps) Data Size (GB) 64

65 Memcached-RDMA Design Sockets Client 1 2 Master Thread Sockets Worker Thread Shared Data RDMA Client 1 2 Sockets Worker Thread Verbs Worker Thread Verbs Worker Thread Memory & SSD Slabs Items Server and client perform a negotiation protocol Master thread assigns clients to appropriate worker thread Once a client is assigned a verbs worker thread, it can communicate directly and is bound to that thread Memcached Server can serve both socket and verbs clients simultaneously All other Memcached data structures are shared among RDMA and Sockets worker threads Memcached applications need not be modified; uses verbs interface if available High performance design of SSD-Assisted Hybrid Memory J. Jose, H. Subramoni, M. Luo, M. Zhang, J. Huang, M. W. Rahman, N. Islam, X. Ouyang, H. Wang, S. Sur and D. K. Panda, Memcached Design on High Performance RDMA Capable Interconnects, ICPP 11 J. Jose, H. Subramoni, K. Kandalla, M. W. Rahman, H. Wang, S. Narravula, and D. K. Panda, Scalable Memcached design for InfiniBand Clusters using Hybrid Transport, CCGrid 12 D. Shankar, X. Lu, J. Jose, M. W. Rahman, N. Islam, and D. K. Panda, Can RDMA Benefit On-Line Data Processing Workloads with Memcached and MySQL, ISPASS 15 65

66 Average latency (us) Throughput (million trans/sec) Performance Benefits on SDSC-Gordon OHB Latency & Throughput Micro-Benchmarks IPoIB (32Gbps) RDMA-Mem (32Gbps) RDMA-Hyb (32Gbps) Message Size (Bytes) ohb_memlat & ohb_memthr latency & throughput micro-benchmarks Memcached-RDMA can - improve query latency by up to 7% over IPoIB (32Gbps) - improve throughput by up to 2X over IPoIB (32Gbps) - No overhead in using hybrid mode with SSD when all data can fit in memory IPoIB (32Gbps) RDMA-Mem (32Gbps) RDMA-Hybrid (32Gbps) 2X No. of Clients D. Shankar, X. Lu, M. W. Rahman, N. Islam, and D. K. Panda, Benchmarking Key-Value Stores on High-Performance Storage and Interconnects for Web-Scale Workloads, IEEE BigData

67 The High-Performance Big Data (HiBD) Project RDMA for Apache Hadoop 2.x (RDMA-Hadoop-2.x) RDMA for Apache Hadoop 1.x (RDMA-Hadoop) RDMA for Memcached (RDMA-Memcached) OSU HiBD-Benchmarks (OHB) HDFS and Memcached Micro-benchmarks Users Base: 125 organizations from 2 countries More than 13, downloads from the project site RDMA for Apache HBase and Spark 67

68 Future Plans of OSU High Performance Big Data (HiBD) Project Upcoming Releases of RDMA-enhanced Packages will support Spark HBase Upcoming Releases of OSU HiBD Micro-Benchmarks (OHB) will support MapReduce RPC Advanced designs with upper-level changes and optimizations E.g. MEM-HDFS 68

69 Looking into the Future. Exascale systems will be constrained by Power Memory per core Data movement cost Faults Programming Models and Runtimes for HPC and BigData need to be designed for Scalability Performance Fault-resilience Energy-awareness Programmability Productivity Highlighted some of the issues and challenges Need continuous innovation on all these fronts 69

70 Funding Acknowledgments Funding Support by Equipment Support by 7

71 Personnel Acknowledgments Current Students A. Augustine (M.S.) K. Kulkarni (M.S.) A. Awan (Ph.D.) M. Li (Ph.D.) A. Bhat (M.S.) M. Rahman (Ph.D.) S. Chakraborthy (Ph.D.) D. Shankar (Ph.D.) C.-H. Chu (Ph.D.) A. Venkatesh (Ph.D.) N. Islam (Ph.D.) J. Zhang (Ph.D.) Past Students P. Balaji (Ph.D.) W. Huang (Ph.D.) D. Buntinas (Ph.D.) W. Jiang (M.S.) S. Bhagvat (M.S.) J. Jose (Ph.D.) L. Chai (Ph.D.) S. Kini (M.S.) B. Chandrasekharan (M.S.) M. Koop (Ph.D.) N. Dandapanthula (M.S.) R. Kumar (M.S.) V. Dhanraj (M.S.) S. Krishnamoorthy (M.S.) T. Gangadharappa (M.S.) K. Kandalla (Ph.D.) K. Gopalakrishnan (M.S.) P. Lai (M.S.) Past Post-Docs J. Liu (Ph.D.) Current Senior Research Associates K. Hamidouche H. Subramoni X. Lu Current Post-Doc Current Programmer J. Lin D. Shankar M. Luo (Ph.D.) A. Mamidala (Ph.D.) G. Marsh (M.S.) V. Meshram (M.S.) A. Moody (M.S.) S. Naravula (Ph.D.) R. Noronha (Ph.D.) X. Ouyang (Ph.D.) S. Pai (M.S.) S. Potluri (Ph.D.) J. Perkins Current Research Specialist M. Arnold G. Santhanaraman (Ph.D.) A. Singh (Ph.D.) J. Sridhar (M.S.) S. Sur (Ph.D.) H. Subramoni (Ph.D.) K. Vaidyanathan (Ph.D.) A. Vishnu (Ph.D.) J. Wu (Ph.D.) W. Yu (Ph.D.) R. Rajachandrasekar (Ph.D.) H. Wang E. Mancini Past Research Scientist Past Programmers X. Besseron S. Marcarelli S. Sur D. Bureddy H.-W. Jin J. Vienne M. Luo 71

72 Thank You! Network-Based Computing Laboratory The MVAPICH2 Project The High-Performance Big Data Project 72

73 Call For Participation International Workshop on Extreme Scale Programming Models and Middleware (ESPM2 215) In conjunction with Supercomputing Conference (SC 215) Austin, USA, November 15th,

74 Multiple Positions Available in My Group Looking for Bright and Enthusiastic Personnel to join as Post-Doctoral Researchers PhD Students Hadoop/Big Data Programmer/Software Engineer MPI Programmer/Software Engineer If interested, please contact me at this conference and/or send an to 74