Next-Generation Switching Systems

Transcription

1 Next-Generation Switching Systems Atsuo Kawai Shin ichi Iwaki Haruyoshi Kiyoku Keizo Kusaba ABSTRACT: Today, the telecommunications industry is encountering a new wave of multimedia communications for the Internet, and mobile services such as PHS (personal handyphone system). Demands for a more sophisticated and powerful node system are increasing to implement these multimedia services. Hitachi, Ltd. and NTT (Nippon Telegraph and Telephone Corporation) have jointly designed and manufactured the New Node Systems, based on a new concept, i.e. single unified architecture for full services. New Node Systems are aimed at improving system scalability, reliability and maintainability, as well as functional expansions. To achieve these goals, various new technologies have been developed in both hardware and software that include many key devices. The New Node Systems are composed of MHN-S (multimedia handling node-), (multimedia handling node-packet), MHN-A (multimedia handling node-atm), MHN-F (multimedia handling node-frame relay). Among these, narrowband communication services were first established. The PHS exchange service was launched in December 1996, and the ISDN (integrated services digital network) service was released in December Other services such as legacy analog telephone service will be soon available. INTRODUCTION THE environment of the public communications network is drastically changing toward a multimedia communication society of the 21st century. The following changes are necessary to keep up with this speedy evolution. A shift of the network s resources from telephone services to multimedia communications. Ability to provide multiple services rapidly. Tolerant to the tariff, lowering pressure for public telecom carriers. In the newly designed node systems, the above requirements are satisfied by: (a) system integration of all nodes through common hardware and common PHS terminals CS SBM ASM MHN-S Telephone network Packet network CS: cell station SBM: subscriber module ASM: architectural module : synchronous transfer mode MHN-S: multimedia handling node- : multimedia handling node-packet : fiber-optic transmission lines MHN-S Fig. 1 MHN-S and in a Public Carrier Network. Hitachi Review Vol. 47 (1998), No. 2 67

2 SBM or SDH interface Service trunks Frame handler SDH: synchronous digital hierarchy ISDN signaling Control processor (a) ASM Other module via ASM SDH interface Frame handler ISDN subcriber module Packet network 2-Mbit/s interface 6-Mbit/s interface Protocol processor Protocol processor ATM Protocol processors interface Fig. 2 Configuration of ASM and. No single part of failure with the redundant configuration. Control processor (b) platform software techniques and, (b) production of a more compact and economical design using LSI circuits. The following paragraphs describe features of the new node systems which provide PHS (personal handyphone system) exchange services and other services such as ATM (asynchronous transfer mode) and frame relay. In addition, the main related technologies are discussed. NODES FOR PHS SERVICES System Configuration Fig. 1 shows the configuration of the new node systems for the integrated PHS exchange services. The new system comprises two types of nodes, the MHN-S and the. The first node accommodates CSs to perform circuit ing, while the second performs packet ing. The MHN-S accommodates SBM-C/S (subscriber module-central/ satellite) and ASM. The SBM concentrates the traffic and the ASM provides the ing services. For these nodes, the following technologies have been developed in order to realize enhanced maintainability and reliability. Moreover, this system is also designed to allow easier expansion of features such as further spread of PHS exchange services. TABLE 1. Main Specifications of ASM Highly multiplexed LSI circuit achieves 80,000 80,000 ing capacity with a single-stage time division. System scale Speech path Max. number of CSs Max. number of trunk lines Configuration Time- scale 2800 CSs 24,000 lines Location Time- single stage 80,000 80,000 ch (@ 64 kbit/s) TABLE 2. Main Specifications of SBM Two types of SBM allow the optimum configuration depending on the CSA characteristics. Subscriber type SBM-C : Same building as ASM SBM-S : Separate building from ASM (1) PHS CS (2) ISDN subscriber Control processor Configuration Processor Dual (each is single processor) Generalpurpose MPU Max. number of subscribers Interface to ASM 3840 subscriber lines 156-Mbit/s fiber-optic transmission line MPU: microprocessing unit 68 Hitachi Review Vol. 47 (1998), No. 2

3 Introduction of per-channel line circuits (one circuit per board) accommodating PHS CSs, for minimization and improved maintainability. Easy maintenance techniques. Improved development efficiency through the use of common platform software. More flexible software functional expansion through object-oriented design. SDH (synchronous digital hierarchy) transmission between the SBM and the ASM. MHN-S (1) ASM The ASM is comprised of a control processor, an, an SDH interface, a frame handler, an ISDN signal processor, and service trunks. The configuration of the ASM is shown in Fig. 2 (a), while its main ations are given in Table 1. The processor is a general-purpose MPU and employs a single-processor configuration which is both compact and economical. The provides a single-stage time- function with up to 80,000 by 80,000 channels on 64-kbit/s basis and non-block speech paths. The key device of this is a 16,000-channel time-division multiplexing LSI circuit. The remaining LSI circuits are employed in the interfaces between the and various peripherals. These LSI circuits transfer electrical 156-Mbit/s signals, realizing compactness and lower cost. The frame handler uses a frame- handler LSI circuit which multiplexes/routes 16-kbit/s or 64- kbit/s n multi-rate frames for D-channel signals and user packets. The ISDN signal processor performs 8000 links LAPD (link access procedure on the D- channel) processing using a multiplexed link-control LSI circuit. (2) SBM There are two types of SBM modules, the first is an SBM-C module, which is installed in the same building as the ASM, while the second is an SBM-S module, which is installed in a separate building. These options allow the optimum deployment of SBMs in more than one building over a wide area. The SBM has a subscriber accommodation section which accommodates PHS CSs, a concentrator, and an ASM interface. Table 2 shows the main ations of the SBM. The following are characteristics of the SBM. Introduction of a per-channel system (one circuit per board) into line circuits which accommodate PHS CSs for improved maintainability. Adoption of a drawer type configuration for the above line circuits for miniaturization. 156-Mbit/s fiber-optic standard interface to the ASM. The consists of common control processor (call operation and maintenance) and protocol handling processors. The latter processors are exclusively allocated for processing vast amounts of protocols, the number of which can be flexibly increased or decreased TABLE 3. Main Specifications of Multi-processor architecture is deployed to meet the higher demands for protocol processing capability. Max. number of packet subscriber lines 25,000 lines System scale Max. number of accommodated MHN-S Max. number of accommodated ISMs 128 MHN-Ss 126 (through SDH) 256 (through 2-Mbit/s interface) Control processor Configuration Dual (two single processors) Protocol processor Processor Configuration General-purpose MPU N + M standby Next-Generation Switching Systems 69

4 Control processor Node A- Node A- Node A Control processor ATM Node B- Node B- Fig. 3 Examples of s Configuration. The concept of common s makes the rapid development possible. Node B- Node B depending on the required throughput. Fig. 2 (b) shows the configuration of the, while its main ations are given in Table 3. The ATM is employed in the as an inter-processor junction. This promises a highly flexible configuration which will support burst traffic such as program loading to the protocol processors. The junction between the circuit interface and protocol processors is the which will allow any connection between these two devices. NODES FOR OTHER SERVICES MHN-A The MHN-A (multimedia handling node-atm), like the, consists of a control processor and an ATM. The peripherals of the ATM include a line interface control unit and a low-/ highspeed line interface unit. They accommodate either 156-Mbit/s or 52-Mbit/s ATM lines in the high-speed interface, or 6-Mbit/s or 1.5-Mbit/s ATM lines in the low-speed interface. The number of line interfaces can be increased or decreased depending on the required throughput. MHN-F The configuration of the MHN-F (Multimedia Handling Node-Frame Relay) is like a hybrid of the and MHN-A. An ATM and line interfaces are similar to those used in the MHN-A, while the protocol control section, which handles frame-relay protocols, is more like the s protocol processors. Consequently, the development time of the MHN-F is shorter than that of the other nodes. HARDWARE/SOFTWARE TECHNOLOGY Common Architecture The newly developed systems use an (functional block) as its basic unit. A variety of nodes can be implemented by combining several s. There are two types of, the first is a common shared by different types of nodes, while the other is a node used only in one type of node. Some examples of common s are shown in Fig. 3. In this case, a control processor and an are commonly employed in both nodes. Such common s help to increase the development speed. The Interfaces positioned between s guarantee the independent features. Functional modifications can be accomplished flexibly by the addition or replacement of unit s. Easier Maintenance The following features facilitate easy maintenance: (1) Prevention of incorrect board insertion The connector part of each PCB (printed circuit board) is equipped with keys corresponding to the different types of boards. The keys fit into OS: operating system Application common part SBM application ASM application application Service layer Common platform interface Expanded OS Basic OS interface Common platform layer Fig. 4 Common Platform Software. Basic OS 70 Hitachi Review Vol. 47 (1998), No. 2

5 grooves in the appropriate back-panel connector preventing insertion of an incorrect board. (2) Hot swap feature The power to each board can be automatically turned on, or off, or reset through the operation of a special lever on the board when it is removed or inserted. This feature makes it unnecessary for maintenance personnel to turn the power off when removing or inserting a board. (3) Automatic diagnostics Each board incorporates an autonomous diagnostic feature which is activated on insertion, and reports the results to the control software, simplifying the board replacement procedure. If the diagnostics fail, the board is kept out of service. (4) Board identification feature The above diagnostics cannot detect an error if an incorrect version of the board is inserted. To prevent this, each board has a ROM (read-only memory) which stores information including the board version and amendment record. This information is softwarereadable, and by comparing the data read by the software with the prespecified attribute information, any error can be detected before an incompatible board is incorporated in the system. (5) Firmware downloading To enhance or modify the features of an, the firmware inside can be updated without ejecting or inserting the boards, by adopting software-controlled downloading of new firmware into the. The software-controlled downloading makes maintenance work easier, and upgrades maintenance reliability. Software Technologies The new node systems employ the following advanced software technologies: (1) Common platform software Fig. 4 shows the configuration of the common platform software. The difference in types of hardwares for nodes can be made invisible to the application software by adopting a configuration of the basic OS and the expanded OS. Therefore, we can easily replace the latest hardware, i.e. processors, without changing the application software. By combining the common platform software and the necessary application software, programming efficiency has been increased. (2) Object-oriented design The ing software is a huge system which must handle the increased demand for reliability, feature expendability, and productivity. To answer these demands, an object-oriented design using C++ language has been extensively employed. By greatly reducing the amount of description needed, logical models of the have been matched to the classes which are the basic elements of the object-oriented design, and calls have been matched to instances. Moreover, inheritance and polymorphism have been used aggressively to reduce the volume of lines of the software code. (3) Plug-in technology Previously, legacy ing software were used to be modified through the use of file updates or software patches. File updates are often accompanied by the interruption of call processing and usually involve heavy work, such as the need for the call relief feature; Source program Address information Switch Instruction memory Tool Loader Modification area * New instructions Jump * Fig. 5 Plug-in Mechanism. The loader inserts new instructions while old instructions are executed. Next-Generation Switching Systems 71

6 thus it cannot be performed so frequently. A software patch can cover only small changes and generally lacks reliability, because it is based on assemblerlevel description. The plug-in mechanism is employed where only source-modified portions have been replaced so that partial file updates are allowed online without interruption of the call processing. This plug-in mechanism is shown in Fig. 5. (4) Software development environment using workstation simulation Specific hardware and software have been designed and manufactured in parallel in order to accelerate the development of the software. A common platform simulator and a basic workstation-based OS simulator, operating the same as the actual system, have been devised for use in the development process. MAIN LSI CIRCUITS The following LSI circuits, which are key devices in the new node systems, have been developed by Hitachi. (1) 16,000-channel time division multiplexing LSI circuit This LSI circuit provides ing connections for 16,000 circuits per chip (in terms of 64 kbit/s) and is one of the major devices incorporated in the ASM/. Hitachi s LSI circuit has four times the capacity of the preceding product. This LSI circuit contributes to making the new node systems significantly smaller and much cheaper. (2) Frame handler LSI circuit This LSI circuit multiplexes and routes frames on 16-kbit/s, 64-kbit/s m circuits. This LSI circuit allows the multiplexing and demultiplexing of D-channel signals, and the routing of packets without software intervention, dramatically improving the overall system performance. (3) LSI circuit for ATM adaptation layer processing This LSI circuit handles the ATM adaptation layer type 5 (AAL5). It distributes incoming frame to the AAL5 cells and constructs AAL5 cells to the frameformat output. By incorporating this LSI circuit into functional blocks, we can realize AAL5 communication between these blocks in a more compact manner. CONCLUSIONS This article describes the New Node Systems for future multimedia networks. The architecture has been designed through the joint-development of Hitachi, Ltd. and NTT. New hardware and software technologies are adopted to improve the system scalability, reliability and maintainability as well as flexible functional expansions. Our MHN (multimedia handling node) systems support PHS exchange services, packet, ATM, and frame relay services cost effectively. Narrowband communication services are launched first and the operation of PHS exchange services were started in December ISDN services were also released in December Other multimedia services such as analog telephony will be initiated soon in the future. ACKNOWLEDGMENT Finally, we deeply appreciate the kind guidance from members at the Network Service Systems Laboratory of NTT. ABOUT THE AUTHORS Atsuo Kawai Joined Hitachi, Ltd. in Belongs to the Advanced Systems Department, Public Telecommunications Operation of the Telecommunications Division. Currently engaged in the development of the ing systems. atsuo_kawai@cm.tcd.hitachi.co.jp Shin ichi Iwaki Joined Hitachi, Ltd. in Belongs to the Advanced Systems Department, Public Telecommunications Operation of the Telecommunications Division. Currently engaged in the development of the ing systems. Member of the Institute of Electronics, Information and Communication Engineers. shinichi-iwaki@cm.tcd.hitachi.co.jp Haruyoshi Kiyoku Joined Hitachi, Ltd. in Belongs to the Software Department, Public Telecommunications Operation of the Telecommunications Division. Currently engaged in the development of the software for the ing systems. Member of the Institute of Electronics, Information and Communication Engineers. kiyoku@tcd.hitachi.co.jp Keizo Kusaba Joined Hitachi, Ltd. in Belongs to the Software Department, Public Telecommunications Operation, Telecommunications Division. Currently engaged in development of software for ing systems. Member of the Institute of Electronics, Information and Communication Engineers. kusaba@tcd.hitachi.co.jp 72 Hitachi Review Vol. 47 (1998), No. 2