Implementation of single bit Error detection and Correction using Embedded hamming scheme

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1 Implementation of single bit Error detection and Correction using Embedded hamming scheme Anoop HK 1, Subodh kumar panda 2 and Vasudeva G 1 M.tech(VLSI & ES), BNMIT, Bangalore 2 Assoc Prof,Dept of ECE, BNMIT, Bangalore 3 Project consultant, Knowx innovations Abstract-Multiple bit upsets due to radiation-induced soft errors are a major concern in Nano scale technology nodes. Once such errors occur in the configuration frames of an FPGA device, they permanently affect the functionality of the mapped design. Existing solutions exploit coding techniques with considerably high overhead to protect configuration frames against multiple bit upsets. Our proposed scheme does not require any changes to the FPGA architecture. Experimental results on a Xilinx SPARTAN 3 FPGA device show that the proposed scheme achieves error recovery coverage of 99.30% with only 3% resource occupation while the mean time to repair is comparable with previous scheme. Hamming and embedded hamming schemes are proposed from the literature survey and memory overhead is reduced in order toachieve the successful implementation of error detection and correction codes. Keywords-Hammingcode, Embedded hamming code, Xilinx,moore s law,spartan3 I. INTRODUCTION Due to high density[1], short time-to-market, programmability, and cost-efficiency, SRAMbased FPGAs are widely used in a variety of application domains[4]. However, increasing transistor count per chip (i.e. Moore s law),[2] aggressive transistor downscaling, and reduced operating voltage result in an exponential growth in soft error rate (SER) of digital circuits in the past years [1, 2]. Considering the proliferation of FPGA devices in various safety and mission-critical applications, it is important to increase their immunity to this kind of errors[5]. To meet performance and power demands, FPGAs are generally fabricated using the most advanced technology nodes. Recently, FPGAs based on 14nm technology have been announced and more dense integration schemes such as FinFET and 3D die stacking have been explored [3, 4]. In such small device geometries, a single particle strike might affect multiple adjacent cells in a memory array resulting in a Multiple Bit Upset[3] (MBU) [5]. Since the MBU rate in nanoscale technology nodes is comparable with the SEU rate [6, 7], an appropriate technique is required to correct multiple errors in memory arrays. Particularly, SRAM-based FPGAs are more prone to soft errors since a radiation strike[6] in a configuration frame1 has a permanent effect on the functionality of the mapped design. Since the configuration frames constitute the majority of SRAM cells in FPGA devices (e.g. more than 80% for Xilinx SPARTAN 3 device), the protection of configuration frames against MBUs is of decisive importance. Several approaches have been proposed to address the grow- 1A configuration frame is the smallest addressable portion of a configuration memory Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed[8] for profit or commercial advantage and that copies bear this notice and the full citation on the first page.soft error concern in FPGA configuration frames. The main objective of these approaches is to reduce error latency and to prevent error accumulation within configuration frames. High overhead modular redundancy [8] is a conventional approach to mitigate soft errors in both configuration frames and functional All rights Reserved 88

2 However, accumulated errors in both data[7] and configuration bits significantly limit the mean time to failure of such techniques [9]. Another approach is to optimize the storage element circuitry of configuration frames for soft errors as detailed in [10, 11]. However, such hardening techniques are not implemented in nowadays commercial FPGA-devices because of their high area overheads. Hence, a technique is required to correct erroneous configuration frames during operation. The combination of configuration scrubbing and Error Correction Codes (ECCs)[10] is an effective solution to correct soft error induced permanent errors in configuration bits. Single Event Upset (SEU) tolerant scrubbing [12, 13] is very well studied in the literature, and Xilinx and Altera have already included it in their design flows [14, 15]. There are also several schemes to explicitly address MBUs in FPGAs. The scheme presented in [16] exploits a two dimensional hamming code to correct MBUs in each configuration frame. In [17], another scheme based on interleaved single error correction hamming code has been proposed which is able to correct up to four bit adjacent errors. Furthermore, Xilinx offers a soft error mitigation controller (IP block) based on ECC and Cyclic Redundancy Code (CRC) which can correct up to two adjacent erroneous cells per configuration frame [18]. Recent experiments show that as technology scales, the number of affected bits by an MBU incident grows as well [6]. Therefore, a more complicated ECC with very high area overhead is required by the system to efficiently address this increase in MBU incidence. Based on the fact that error detection can be done at much lower cost than error correction [19], in this project, employs a low-cost interleaved two dimensional parity technique to detect MBUs in the configuration frames of the FPGA. The interleaving distance is optimized based on the actual MBU patterns and their respective probabilities obtained from a detailed technology dependent analysis. Once an MBU is detected, by taking advantage of erasure codes and using the data stored in a redundant frame, the correct contents of the affected configuration frame is reconstructed.] II. RELATED WORK 2.1 FPGA Configuration Frames: The configuration memory of an FPGA device is organized into configuration frames which are the smallest addressable units and constitute the majority of SRAM cells in FPGA devices. The number and the size of the configuration frames vary from one device to another. In Xilinx SPARTAN 3 device which is used as a case study in this work, there are 28,464 configuration frames, each comprising of bit words (total of 72,049 Kb) whereas there are only 461 of 36 Kb BRAMs. Thus, for this device, 81.28% of the total SRAM cells belong to the configuration frames. For a given design, the FPGA device utilizes only a subset of the total available configuration frames and these are known as sensitive frames. Any errors occurring in sensitive frames of the device can lead to a system malfunction. 2.2 MBU Patterns: A fair quantification of the MBU correction capability of the proposed scheme requires detailed information about the possible MBU patterns and their respective occurrence probabilities. In this regard, performed a 3D-TCAD-based neutron particle strike simulation using a commercial soft error evaluation tool [20]. The SPICE netlist and the layout of the memory unit as well as the radiation environment information are provided as inputs to this tool which computes the distribution of generated current pulses for each cell according to a nuclear database. Then, the obtained current pulses are injected in the SPICE netlist to extract the SEU and MBU rate. Using this tool, obtained the occurrence probabilities of neutron-induced MBU patterns on an SRAM memory designed for a 45 nm technology in the terrestrial environment. For this experiment, the neutron energy distribution is specified by the JEDEC89a standard [21]. 0% 10% 20% 30% 40% 50% 60% Occurrence Probability MBU Size (a) 51.72% 9.38% 4.94% 3.04% 3.72% 0.97% 0.97% 1.69% 1.69% 1.35% 0.94% 0.94% 0.25% 0.25% 0.21% 0.23% 0.29% 0.18% 0.18% 0.28% 0.28% 0.28% 0.07% 0.07% 0.19% All rights Reserved 89

3 0.18% 0.18% 0.15% 0.07% 0.07% 0.17% 0.18% 0.38% 0.31% 0.68% (b) a) MBU Size Distribution b) Some of MBU Patterns with High Occurrence As it can be seen, almost half of the SRAM soft errors in the employed 45 nm technology result in an MBU incident. The largest MBU size observed in this experiment was 24. For smaller technology nodes, this ratio and also largest MBU size further increases [6]. This clearly shows the importance of protecting configuration frame against MBU incidents. 2.3 Erasure Codes: Our proposed scheme is based on the concept of erasure codes [22, 23]. An optimal erasure code is a data reconstruct Encoding Decoding m data blocks n redundant blocks m+n blocks Figure 1 Figure 1: Encoding and Decoding of Erasure codes Encoding and Decoding of Erasure Codes, technique which transforms m blocks into m + n blocks such that the original m blocks can be recovered from an arbitrary set of m blocks among m+n coded blocks (see Figure 2). This kind of data recovery technique is widely used in reliable storage devices (hard disks and CDs) [10], signal transfer protocols, and multimedia multi-casting [11]. Variety of erasure codes with different area overhead, recovery coverage, and encoding/decoding complexity are presented in the literatures [14]. The area overhead of an erasure code is defined as the ratio of redundant blocks to data blocks (i.e. n/m). The recovery coverage of an erasure code is defined as number of erasures that could be tolerated. For optimal erasure codes, the recovery coverage is equal to the number of redundant blocks (i.e. n). Erasure codes are not designed to detect or correct errors rather to recover the original blocks when a subset of blocks is erased (i.e. not available). However, once an error is detected in some blocks, by assuming that those blocks are erased, the original blocks could be recovered by means of an erasure code. III.DESIGN AND ANALYSIS 3.1 Embedded Hamming Code In order to illustrate the technique of embedded hamming code, a simpler technique of embedded parity code is first explained. A parity bit is a check bit that represents whether the number of ones in the frame is even (p e ) or odd (p o ). In a traditional parity code, the parity bit is appended after the frame. However, in the technique of embedded parity code, the parity of the essential bits is stored in one of the non-essential bits of the same frame. This converts the entire frame into a parity compliant code since any single bit error in the frame can be detected by computing its parity. For the rest of the examples illustrated in this section, f i and f i M shown in Figure 3 are used. Both these frames are combined into one frame (f + ) for easier comprehension, where the non-essential bits are represented by don t care bits X. In order to apply embedded parity code to f +, p e for the essential bits is calculated. p e = 1 in this case since there are an odd number of ones (5) in the essential bits. This value is then stored in one of the non essential bits (X 1 in this example) while the other non-essential bits are set to 0 as shown in Figure 3. The entire frame f + is now parity compliant. When a bit-flip occurs, the error can be detected as the p e of the frame changes to All rights Reserved 90

4 Extending the same concept used in embedded parity code, an embedded hamming code manipulates the non-essential bits of a frame such that the entire frame becomes hamming code compliant. A typical hamming code consists of a number of data bits (d i ) with parity bits (p i ) embedded in indices (ix) that are powers of two as shown in Figure 4. These parity bits are computed by choosing a different set of data bits for each parity bit as specified by a hamming check matrix (H) [11]. Each row of H corresponds to a parity bit while the columns specify whether a data bit is included in the parity bit of that row. Fig 2 hamming check matrix Fig 3-error detection & correction using embedded hamming code For the H shown in Figure 4, the parity bit p 1 of f i isgiven by p 1 = d 1 d 2 d 4 d 5 d 7 d 9 d 11. Other parity bits are computed in a similar manner according to H. For the example frame f +, computing the values of the parity bits using H, results in a set of XOR equations with the different non-essential bits as shown below. Solving these equations gives the values of the non-essential bits that make the frame hamming code compliant. For the example considered, we obtain X 1 = X 2 = X 4 = X 5 =X 6 = X 7 = X 8 = 0 and X 3 = 1. Figure 5 shows the frame f + before and after embedding. Algorithm 1 illustrates the steps needed to embed the hamming code into a configuration frame. The algorithm essentially tries to find a suitable value for the non-essential bits, such that the entire frame becomes hamming compliant. Algorithm for embedded hamming Lines 1-4 compute the required for f i. The hamming check matrix H (dimensions ) is then generated (line 5) in order to compute the parity bits of the hamming code [11]. The column vector b, which is then computed using H and f i (line 6), represents the All rights Reserved 91

5 of the linear equality constraints of the hamming code. The function repmat in line 7 replicates the mask frame f i M for rows so that it can be XORed with H in order to obtain the coefficients of the linear equality constraints (tmp) of the hamming code. Line 8 selects only those columns of matrix tmp which correspond to non-essential bits of f i. Finally the values of the non-essential bits are computed by solving the binary linear equation function solve lineq(a; b). 3.2ESSENTIAL AND NON-ESSENTIAL FRAMES: Essential bits are present in the circuit whereas non-essential bits will not be present in the circuit. Example for ess- Mask bitstream whereas for non-ess-the difference of the bits in FPGA is taken Frame utilization ratio: It is the ratio of essential bits to the total number of bits in a frame. 3.3 Bit Interleaving If the embedded hamming code was applied to the entire frame, only SBUs can be corrected, as hamming code is capable of correcting only one error. Bit interleaving has been considered in combination with embedded hamming to increase the number of errors than can be detected and corrected. Fig 4- bit interleaving Fig 5-overall process of kit implementation IV.RESULTS AND DISCUSSIONS The proposed technique is implemented on a Xilinx SPARTAN 3 device as a proof of concept. In this section, explain the implementation flow for this device. Then, discuss the area overhead and recovery time trade-off in details and quantitatively compare the proposed scheme with the previous schemes. Fig 6 RTL Schematic for embedded All rights Reserved 92

6 Fig 7 Single bit eror detection and correction The RTL Schematic for the proposed work is as shown in fig-6.it includes encoders and decoders along with hamming block,the code is written in Verilog,synthesized netlist is obtained from Xilinx tool and simulated using ISE Simulator. The simulation results are shown in fig-7 and fig 8. Fig 8. Multi bit error detection and correction using embedded hamming V.CONCLUSION & FUTURE SCOPE 5.1 CONCLUSION The proposed scheme is implemented as a generic soft core alongside with the user application and does not require any changes to the FPGA architecture. Compared to the previous approaches, our proposed scheme achieves the highest level of MBU protection at very low costs while the recovery time is negligible. The proposed scheme is implemented on Xilinx Spartan 3 device which incurs only 1% memory and 3% logic resource overhead. Moreover, the error correction latency is also very small (0.35 ms for 50 clusters). These confirm that the proposed scheme is a viable solution for MBU protection in FPGA configuration frames. The following objectives have been achieved : 1.Analysis of hamming encoder and decoder is done and simulated using Xilinx ISE simulator by achieving successful results. 2. The synthesized netlist which gives the first cut information about the embedded hamming code using SRAM was generated successfully and area,timing reports are generated. 5.2 FUTURE SCOPE There are wide range of coding techniques used in error control coding schemes. Hamming code and embedded hamming code forms an integral part in error control coding. These techniques can be used in future to solve linear equations depending on higher order and higher degree. Solving All rights Reserved 93

7 equations can also be done by numerical methods such as Euler s method,newton-raphson method, Regula-falsimethod,etc. these methods can solve the linear equation by calculating the forward difference and backward difference operators. But the number of iterations are limited and accuracy is less. Hence embedded hamming code technique can be used to solve these linear equations. REFERENCES [1] Dixit and A. Wood. The impact of new technology on soft error rates. In IRPS, [2] H. Kaul et al. Near-threshold Voltage (NTV) Design: Opportunities and Challeges. In DAC, [3] P. Dorsey. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx White Paper: Virtex-7 FPGAs, [4] Altera Corp. Meeting the Performance and Power Imperative of the Zettabyte Era with Generation 10. Altera White Paper WP , [5] M. Ebrahimi et al. A layout-based approach for multiple event transient analysis. In DAC, pages , [6] E. Ibe et al. Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. TED, 57(7): , [7] D. Radaelli et al. Investigation of multi-bit upsets in a 150 nm technology SRAM device. TNS, 52(6): , [8] Carmichael. Triple module redundancy design techniques for Virtex FPGAs. Xilinx Application Note XAPP197, [9] M. Ebrahimi et al. Low-cost Scan chain-based technique to recover multiple errors in TMR systems. TVLSI, [10] S. Srinivasan et al. Improving soft-error tolerance of FPGA configuration bits. In ICCAD, [11] B.S. Gill et al. A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA. In DATE, [12] M. Berg et al. Effectiveness of internal versus external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design, test, and analysis. TNS, 55(4), [13] A. Sari et al. Combining checkpointing and scrubbing in fpga-based real-time systems. In VTS, [14] L. Jones. Single event upset (SEU) detection and correction using Virtex-4 devices. Xilinx Application Note XAPP714, [15] Altera Corp. Enhancing Robust SEU Mitigation with 28-nm FPGAs. Altera White Paper WP , [16] S.P. Park et al. Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. TVLSI, 20(2), [17] M. Lanuzza et al. A self-hosting configuration management system to mitigate the impact of Radiation-Induced Multi- Bit Upsets in SRAM-based FPGAs. In ISIE, pages , [18] LogiCORE IP Soft Error Mitigation Controller v3.4. Product Guide PG036, [19] R.H. Morelos-Zaragoza. The Art of Error Correcting Coding. John Wiley & Sons, [20] E. Costenaro et al. A Practical All rights Reserved 94