Virtex-6 FPGA GTX Transceiver OTU1 Electrical Interface

Transcription

1 Virtex-6 FPGA GTX Transceiver OTU1 Electrical Interface Characterization Report

2 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 11/12/ Initial Xilinx release. Virtex-6 FPGA GTX Transceiver OTU1 Interface

3 Table of Contents Revision History Virtex-6 FPGA GTX Transceiver OTU1 Electrical Interface Introduction Test Conditions Transceiver Selection Summary of Results OTU1 Electrical Characterization Details Transmitter Near-End Output Eye ITU-T G.8251 Transmitter Output Jitter ITU-T G.8251 Receiver Jitter Tolerance References Virtex-6 FPGA GTX Transceiver OTU1 Interface 3

4 4 Virtex-6 FPGA GTX Transceiver OTU1 Interface

5 Introduction Virtex-6 FPGA GTX Transceiver OTU1 Electrical Interface Introduction This characterization report compares the electrical performance of the Virtex -6 FPGA GTX transceiver against International Telecommunication Union Telecommunication Standardization Sector (ITU-T) Recommendation G.8251, The control of jitter and wander within the optical transport network (OTN) [Ref 1]. The characterization is performed as per ITU-T Recommendation G.8251 at a data rate of Gb/s across voltage, temperature, and worst-case transceiver performance corners. The following tests are included in this report: ITU-T Recommendation G.8251 Transmitter Output Jitter ITU-T Recommendation G.8251 Receiver Input Jitter Tolerance Test Conditions Table 1 and Table 2 show the supply voltage and temperature conditions, respectively. Table 1: Supply Voltage Test Conditions Condition MGTAVCC (V) MGTAVTT (V) V MIN See Note (1) 1.14 V MAX See Note (1) 1.26 Notes: 1. Refer to Virtex-6 FPGA Data Sheet: DC and Switching Characteristics [Ref 2] for the MGTAVCC values. 2. Other FPGA voltages remain at their nominal values. Table 2: Temperature Test Conditions Condition Temperature ( C) T T 0 0 T Virtex-6 FPGA GTX Transceiver OTU1 Interface 5

6 Transceiver Selection Transceiver Selection Volume generic transceiver characterization is first performed across process, voltage, and temperature (PVT). The generic data can be found in the Virtex-6 FPGA GTX Transceiver Characterization Report [Ref 3]. Protocol-specific characterization is then performed using representative transceivers from generic characterization across PVT. The chosen transceivers represent a mixture of worst-case and typical performance transmitters and receivers. The selected worst-case transceivers used in this protocol characterization are within the worst case distribution of the transceivers found in the generic volume characterization. The histograms in this characterization report do not contain a true statistical representation normally present in a random (or even typical) population. The histograms are skewed toward the worst-case performance because of the transceiver selection and are not representative of typical production silicon. Summary of Results Table 3 shows a comparison of the Virtex-6 FPGA GTX transceiver against the ITU-T Recommendation G.8251 using a reference clock rate of divide-by-16 from the line rate clock. The data reported in Table 3 represents the worst-case voltage, temperature, and performance corners tested. Table 3: OTU1 Characterization: Summary of Results Test Parameter Specification (P2P) (1) Worst-Case Test Result (P2P) Units Compliant ITU-T G.8251 HP1 + LP UI Yes Transmitter Output Jitter (2) HP2 + LP UI Yes ITU-T G.8251 Receiver Jitter Tolerance 500 Hz (3) UI Yes 20 MHz UI Yes Notes: 1. P2P is peak to peak. 2. The tests are run for 60 seconds as per the ITU-T Recommendation G This is the limit of the jitter tolerance tester. 6 Virtex-6 FPGA GTX Transceiver OTU1 Interface

7 Figure 1 shows the SONET filters, and Table 4, page 7 describes them. X-Ref Target - Figure UI Frequency (Hz) RPT148_01_ Figure 1: SONET Filter Table 4: SONET Filter Description Parameter Specification HP1 HP2 LP 5 KHz 1 MHz 20 MHz OTU1 Electrical Characterization Details This section contains the detailed Optical channel Transport Unit 1 (OTU1) test methodology and results of each test summarized in Table 3. The GTX transceiver is configured using the GTX Wizard v1.5, including the attribute settings. GTX transceiver attribute settings that differ from the GTX Wizard default settings are identified in the Test Setup and Conditions table (Table 6, page 8, Table 7, page 11, and Table 9, page 17) for each test. Table 5 shows the phase-locked loop (PLL) settings used during OTU1 characterization. Table 5: Data Rate (Gb/s) Gb/s Line Rate PLL Settings PLL Frequency (GHz) REFCLK Frequency (MHz) [TX/RX]PLL_DIVSEL_REF [TX/RX]PLL_DIVSEL45_FB x [TX/RX]PLL_DIVSEL_FB [TX/RX]PLL_DIVSEL_OUT = 16 2 Virtex-6 FPGA GTX Transceiver OTU1 Interface 7

8 Transmitter Near-End Output Eye Test Methodology The FPGA is configured to transmit a received pattern on the TX data pins. The resulting eye is captured using an Agilent 86100C Infiniium DCA-J Wideband Oscilloscope at nominal voltage and room temperature conditions. Table 6 defines the test setup and conditions for the transmitter near-end output eye. Table 6: Transmitter Near-End Output Eye Test Setup and Conditions Parameter Value Measurement Instrument TX Coupling Voltage Temperature Agilent 86100C DCA-J Wideband Oscilloscope AC coupled using DC blocks Nominal Room temperature Pattern OTN bulk PRBS23 Load Board ML623 characterization platform (FF1156) (1) TX Amplitude TXDIFFCTRL = 4'b0101 REFCLK Test Results Synchronous MHz 1. Refer to the ML623 Virtex-6 FPGA GTX Transceiver Characterization Board User Guide for more details on the Virtex-6 FPGA characterization platform [Ref 4]. Figure 2 shows the transmitter near-end output eye at Gb/s. 8 Virtex-6 FPGA GTX Transceiver OTU1 Interface

9 X-Ref Target - Figure 2 RPT148_02_ Figure 2: TX Near-End Output Eye (2.667 Gb/s with MHz REFCLK) ITU-T G.8251 Transmitter Output Jitter Test Methodology Transmitter output jitter data is collected using two different types of test setups. The first test setup, shown in Figure 3, uses the JDSU ONT-506 electrical interface to measure the output jitter data. The second test setup, shown in Figure 4, uses the JDSU optical interface to measure the output jitter data. A reference optical device is used in this setup. Virtex-6 FPGA GTX Transceiver OTU1 Interface 9

10 X-Ref Target - Figure 3 JDSU 506 Electrical Connection TxClk TxData RxClk MGTAVCC Power Supply Agilent E3631A 0 6V, 5A/0 ±25V, 1A Adjust Display Function Voltage / Current + 6 V 25 V COM - ON/ OFF RxData Optical Connection TxData 1550 TxData 1310 RxData RxData OC-48 STM-16 OTU-1 OC-1/3/2 STM 0/1/4 MGTAVTT Power Supply Agilent E3631A 0-6V, 5A/0 ±25V, 1A Display Function Adjust Voltage / Current + 6 V 25 V COM - ON/ OFF TX Balun Agilent 81133A 3.35 GHz Pulse/Pattern Generator ML623 Virtex-6 FPGA DUT Board Rev C TXP TXN MGTAVCC 1.0 V Display Keyboard and Miscellaneous Buttons Clock Input Start Input Trigger Out Channel 1 RX Balun RXP RXN Legend SMA Matched Pair Cables for GT Receiver SMA Matched Pair Cables for GT Transmitter SMA Matched Pair Cables for GT Clocks Cables for Reference Clocks SMA Cable Connection to RX Balun SMA Cable Connection to TX Balun DC Blocks 50Ω Termination Cable for 1.0 V Power Supply Cable for 1.2 V Power Supply Cable for Ground Power Supply Output Output CLKN CLKP Channel 1 Virtex-6 LX240T FPGA FF1156 MGTAVTT 1.2 V GND RPT148_03_ Figure 3: OTU1 Transmitter Output Jitter Test Setup Using the JDSU Electrical Interface 10 Virtex-6 FPGA GTX Transceiver OTU1 Interface

11 X-Ref Target - Figure 4 JDSU 506 Electrical Connection TxClk TxData RxClk MGTAVCC Power Supply Agilent E3631A 0 6V, 5A/0 ±25V, 1A Adjust Display Function Voltage / Current + 6 V 25 V COM - ON/ OFF RxData Optical Connection TxData 1310 OC-48 STM-16 OTU-1 Agilent 81133A 3.35 GHz Pulse/Pattern Generator 1550 OC-1/3/2 STM 0/1/4 TxData RxData RxData dbm Optical Power Monitor- Attenuator RXN RXP Xilinx SMA-SFP Rev. A TXP TXN MGTAVTT Power Supply Agilent E3631A 0 6V, 5A/0 ±25V, 1A ON/ OFF Display Function ML623 Virtex-6 FPGA DUT Board Rev. C TXP TXN Adjust Voltage / Current + 6 V 25 V COM - MGTAVCC 1.0 V Display Keyboard and Miscellaneous Buttons Clock Input Start Input Trigger Out Channel 1 RXP RXN Legend SMA Matched Pair Cables for GT Receiver SMA Matched Pair Cables for GT Transmitter SMA Matched Pair Cables for GT Clocks Cables for Reference Clocks SC to LC Fibre Cable, Single Mode SC to SC Fibre Cable, Single Mode DC Blocks 50Ω Termination Cable for 1.0 V Power Supply Cable for 1.2 V Power Supply Cable for Ground Power Supply Output Output CLKN CLKP Channel 1 Virtex-6 LX240T FPGA FF1156 MGTAVTT 1.2 V GND RPT148_04_ Figure 4: OTU1 Transmitter Output Jitter Test Setup Using the JDSU Optical Interface Because of board limitations, measurements are taken with approximately 4 to 11 inches of channel length between the TXP/TXN FPGA pins and the SMA connectors on the ML623 characterization platform. Table 7 defines the test setup and conditions. Table 7: OTU1 Transmitter Output Jitter Test Setup and Conditions Parameter Value Measurement Instrument JDSU ONT-506 optical network tester BN 3061/90.27 TX Coupling Voltage AC coupled using DC blocks V MIN, V MAX Temperature T -40, T 0, T 100 Pattern OTN bulk PRBS23 Load Board ML623 characterization platform, Revision C (FF1156) (1) Optical-to-SFP Board Optical Module Optical Power Monitor- Attenuator Xilinx HW-AFX-SMA-SFP, Revision A Fiberxon FTM-3128C-SL2G Eigenlight 410 Power Monitor-Attenuator Virtex-6 FPGA GTX Transceiver OTU1 Interface 11

12 Table 7: OTU1 Transmitter Output Jitter Test Setup and Conditions (Cont d) TX Amplitude/Post-Emphasis REFCLK Parameter Value GT transceiver attributes: TXDIFFCTRL = 4'b0101 TXBUFDIFFCTRL = 3'b100 For electrical interface: TXPOSTEMPHASIS = 5'b01011 TXPREEMPHASIS = 4'b1111 For optical interface: TXPOSTEMPHASIS = 5'b01000 TXPREEMPHASIS = 4'b0010 Synchronous divide-by-16 from JDSU bit rate clock Notes: 1. For the Virtex-6 GTX transceiver analog power supplies, MGTAVCC and MGTAVTT, power supply noise must be less than 10 mv pk-pk over the frequency range of 10 KHz to 80 MHz. Refer to the Virtex-6 FPGA GTX Transceivers User Guide [Ref 5] for more details on power supply guidelines. Test Results Figure 5, Figure 6, Figure 7, and Figure 8 show the output jitter test results using an OTN bulk PRBS23 pattern. Measurements are taken with approximately 4 to 11 inches of channel length between the TXP/TXN FPGA pins and the SMA connectors on the ML623 characterization platform. The added FR4 channel contributes additional ISI (deterministic jitter) when tested with an OTN bulk PRBS23 pattern, artificially increasing the output jitter. As a result, the data presented in the figures are pessimistic Virtex-6 FPGA GTX Transceiver OTU1 Interface

13 Figure 5 shows the output jitter test results using the OTN bulk PRBS23 pattern with the HP1 + LP SONET filter measured using the JDSU electrical interface. X-Ref Target - Figure Number of Data Points TJ (UI) RPT148_05_ Figure 5: OTU1 Transmitter Output Jitter Test Results (OTN Bulk PRBS23 with HP1 + LP) Using JDSU Electrical Interface Figure 6 shows the output jitter test results using the OTN bulk PRBS23 pattern with the HP2 + LP SONET filter measured using the JDSU electrical interface. X-Ref Target - Figure Number of Data Points TJ (UI) RPT148_06_ Figure 6: OTU1 Transmitter Output Jitter Test Results (OTN Bulk PRBS23 with HP2 + LP) Using JDSU Electrical Interface Virtex-6 FPGA GTX Transceiver OTU1 Interface 13

14 Figure 7 shows the output jitter test results using the OTN bulk PRBS23 pattern with the HP1 + LP SONET filter measured using the JDSU optical interface. X-Ref Target - Figure Number of Data Points TJ (UI) RPT148_07_ Figure 7: OTU1 Transmitter Output Jitter Test Results (OTN Bulk PRBS23 with HP1 + LP) Using JDSU Optical Interface Figure 8 shows the output jitter test results using the OTN bulk PRBS23 pattern with the HP2 + LP SONET filter measured using the JDSU optical interface. X-Ref Target - Figure 8 25 Number of Datapoints TJ (UI) RPT148_08_ Figure 8: OTU1 Transmitter Output Jitter Test Results (OTN Bulk PRBS23 with HP2 + LP) Using JDSU Optical Interface 14 Virtex-6 FPGA GTX Transceiver OTU1 Interface

15 Table 8 summarizes the results of the transmitter output jitter characterization. Table 8: Summary of OTU1 Transmitter Output Jitter Test Results Test Parameter Specification (P2P) TJ (P2P) TJ (RMS) Units Compliant ITU-T G.8251 Transmitter HP1 + LP UI Yes Jitter Generation (1) HP2 + LP UI Yes Notes: 1. Tests were run for 60 seconds in accordance with the specification. ITU-T G.8251 Receiver Jitter Tolerance Test Methodology Receiver jitter tolerance is measured using the test setup shown in Figure 9. The JDSU optical network tester generates an OTN bulk pattern using a PRBS23 pattern. The GTX transceiver under test recovers the data and transmits the pattern back to the error detector input of the JDSU optical network tester where bit errors are measured. The JDSU optical interface is used for this measurement. The test is performed in synchronous mode with the JDSU supplying the bit rate clock. To obtain the appropriate reference clock rate for the GTX transceiver under test, the bit rate clock supplied by the JDSU optical network tester is divided down to the appropriate reference clock rate using the Agilent 81133A clock generator. Virtex-6 FPGA GTX Transceiver OTU1 Interface 15

16 X-Ref Target - Figure 9 JDSU 506 Electrical Connection TxClk TxData RxClk MGTAVCC Power Supply Agilent E3631A 0 6V, 5A/0 ±25V, 1A Adjust Display Function Voltage / Current + 6 V 25 V COM - ON/ OFF RxData Optical Connection TxData 1310 OC-48 STM-16 OTU-1 Agilent 81133A 3.35 GHz Pulse/Pattern Generator 1550 OC-1/3/2 STM 0/1/4 TxData RxData RxData dbm Optical Power Monitor- Attenuator RXN RXP Xilinx SMA-SFP Rev. A TXP TXN MGTAVTT Power Supply Agilent E3631A 0 6V, 5A/0 ±25V, 1A ON/ OFF Display Function ML623 Virtex-6 FPGA DUT Board Rev. C TXP TXN Adjust Voltage / Current + 6 V 25 V COM - MGTAVCC 1.0 V Display Keyboard and Miscellaneous Buttons Clock Input Start Input Trigger Out Channel 1 RXP RXN Legend SMA Matched Pair Cables for GT Receiver SMA Matched Pair Cables for GT Transmitter SMA Matched Pair Cables for GT Clocks Cables for Reference Clocks SC to LC Fibre Cable, Single Mode SC to SC Fibre Cable, Single Mode DC Blocks 50Ω Termination Cable for 1.0 V Power Supply Cable for 1.2 V Power Supply Cable for Ground Power Supply Output Output CLKN CLKP Channel 1 Virtex-6 LX240T FPGA FF1156 MGTAVTT 1.2 V GND RPT148_09_ Figure 9: OTU1 Receiver Jitter Tolerance Test Setup 16 Virtex-6 FPGA GTX Transceiver OTU1 Interface

17 Figure 10 shows a screen capture of the jitter injected to the GTX transceiver under test. X-Ref Target - Figure 10 Figure 10: OTU1 Receiver Jitter Tolerance Setup (OTN Bulk PRBS23 Pattern with SJ Injected) Table 9 defines the receiver jitter tolerance test setup and conditions. RPT148_10_ Table 9: OTU1 Receiver Jitter Tolerance Test Setup and Conditions Parameter Value Measurement Instrument JDSU ONT-506 optical network tester BN 3061/90.27 RX Coupling Voltage AC coupled using DC blocks V MIN, V MAX Temperature T -40, T 0, T 100 Pattern OTN Bulk PRBS23 Injected Jitter SJ = Tested to failure; Frequency sweep = 10 Hz 20 MHz Load Board ML623 characterization platform, revision C (FF1156) (1) Optical-to-SFP Board Optical Module Optical Power Monitor- Attenuator Xilinx HW-AFX-SMA-SFP, Revision A Fiberxon FTM-3128C-SL2G Eigenlight 410 Power Monitor-Attenuator Virtex-6 FPGA GTX Transceiver OTU1 Interface 17

18 Table 9: OTU1 Receiver Jitter Tolerance Test Setup and Conditions (Cont d) Parameter Value Attributes REFCLK GTX attributes: PMA_CDR_SCAN = 27'h640404C PMA_RX_CFG= 25'h05CE008 RXEQMIX = 3'b111 DFE disabled Synchronous divide-by-16 from JDSU bit rate clock Notes: 1. For the Virtex-6 FPGA GTX transceiver analog power supplies, MGTAVCC and MGTAVTT, power supply noise must be less than 10 mv pk-pk over the frequency range of 10 KHz to 80 MHz. Refer to the Virtex-6 FPGA GTX Transceivers User Guide [Ref 5] for more details on power supply guidelines. Test Results Figure 11 shows the output jitter test results using an OTN bulk PRBS23 pattern. Measurements are taken with approximately 4 to 10 inches of channel length between the RXP/RXN FPGA pins and the SMA connectors on the ML623 characterization platform. The added FR4 channel contributes additional ISI (deterministic jitter) when tested with an OTN bulk PRBS23 pattern, artificially increasing injected jitter. As a result, the data presented in Figure 11 is pessimistic. X-Ref Target - Figure Amplitude (UI) Frequency (Hz) RPT148_11_ Figure 11: OTU1 Receiver JItter Tolerance Test Results (OTN Bulk PRBS23 Pattern with SJ Injected) 18 Virtex-6 FPGA GTX Transceiver OTU1 Interface

19 References Figure 12 shows the SJ tolerance at 20 MHz for OTU1. The jitter tolerance tester limit is UI. X-Ref Target - Figure Number of Data Points SJ at 20 MHz RPT148_12_ Figure 12: OTU1 Receiver Sinusoidal Jitter Tolerance at 20 MHz Test Results (OTN Bulk PRBS23 Pattern) Table 10 indicates the OTU1 minimum receiver SJ tolerance for 500 Hz and 20 MHz. Table 10: OTU1 Receiver Jitter Tolerance Test Results Parameter Test Condition Minimum SJ Tolerance Units OTU1 Receiver Jitter Tolerance 500 Hz 160 (1) UI 20 MHz UI Notes: 1. The limit of the jitter tolerance tester. References This characterization report uses the following references: 1. ITU-T Recommendation G.8251, The control of jitter and wander within the optical transport network (OTN), International Telecommunication Union 2. DS152, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics. 3. RPT120, Virtex-6 FPGA GTX Transceiver Characterization Report. 4. UG724, ML623 Virtex-6 FPGA GTX Transceiver Characterization Board User Guide. 5. UG366, Virtex-6 FPGA GTX Transceivers User Guide. Virtex-6 FPGA GTX Transceiver OTU1 Interface 19