UCB CS61C : Machine Structures

Transcription

1 inst.eecs.bekeley.edu/~cs61c UCB CS61C : Machine Stuctues Lectue SOE Dan Gacia Lectue 28 CPU Design : Pipelining to Impove Pefomance Stanfod Reseaches have invented a monitoing technique called Instuction Footpint Recoding and Analysis (IFRA) that collects info about the hadwae when it s actually unning (as opposed to vey slow simulations) to help pinpoint hadwae eos. When eos ae detected, it takes a snapshot of the cuent state to help epoduce it. It can locate 96% of bugs, 80% w/time & location.

2 Review: Single cycle datapath 5 steps to design a pocesso 1. Analyze instuction set datapath equiements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the equiements 4. Analyze implementation of each instuction to detemine setting of contol points that effects the egiste tansfe. 5. Assemble the contol logic Contol is the had pat MIPS makes that easie Instuctions same size Souce egistes always in same place Immediates same size, location Opeations always on egistes/immediates Pocesso Contol Datapath Memoy Input Output CS61C L28 CPU Design : Pipelining to Impove Pefomance I (2)

3 How We Build The Contolle opcode" func" RegDst = add + sub add" Sc = oi + lw + sw sub" MemtoReg = lw oi" RegWite = add + sub + oi + lw lw" AND logic" MemWite = sw sw" OR logic" beq" npcsel = beq jump" Jump = jump ExtOp = lw + sw ct[0] = sub + beq (assume ct is 0 ADD, 01: SUB, 10: OR) ct[1] = o whee, type = ~op 5 ~op 4 ~op 3 ~op 2 ~op 1 ~op 0, oi = ~op 5 ~op 4 op 3 op 2 ~op 1 op 0 lw = op 5 ~op 4 ~op 3 ~op 2 op 1 op 0 sw = op 5 ~op 4 op 3 ~op 2 op 1 op 0 beq = ~op 5 ~op 4 ~op 3 op 2 ~op 1 ~op 0 jump = ~op 5 ~op 4 ~op 3 ~op 2 op 1 ~op 0 add = type func 5 ~func 4 ~func 3 ~func 2 ~func 1 ~func 0 sub = type func 5 ~func 4 ~func 3 ~func 2 func 1 ~func 0 RegDst" Sc" MemtoReg" RegWite" MemWite" npcsel" Jump" ExtOp" ct[0]" ct[1]" Omigosh omigosh, do you know what this means? CS61C L28 CPU Design : Pipelining to Impove Pefomance I (3)

4 Call home, we ve made HW/SW contact! High Level Language Pogam (e.g., C)# Compile! Assembly Language Pogam (e.g.,mips)# Assemble! Machine Language Pogam (MIPS)# temp = v[k];# v[k] = v[k+1];# v[k+1] = temp;" lw lw sw sw $t0, 0($2) $t1, 4($2) $t1, 0($2) $t0, 4($2) ! Machine Intepetation! Hadwae Achitectue Desciption (e.g., block diagams) " Achitectue Implementation! Logic Cicuit Desciption (Cicuit Schematic Diagams)# CS61C L28 CPU Design : Pipelining to Impove Pefomance I (4)

5 Pocesso Pefomance Can we estimate the clock ate (fequency) of ou single-cycle pocesso? We know: 1 cycle pe instuction lw is the most demanding instuction. Assume these delays fo majo pieces of the datapath: Inst. Mem,, Data Mem : 2ns each, egfile 1ns Instuction execution equies: = 8ns 125 MHz What can we do to impove clock ate? Will this impove pefomance as well? We want inceases in clock ate to esult in pogams executing quicke. CS61C L28 CPU Design : Pipelining to Impove Pefomance I (5)

6 Gotta Do Laundy Ann, Bian, Cathy, Dave each have one load of clothes to wash, dy, fold, and put away Washe takes 30 minutes A B C D Dye takes 30 minutes Folde takes 30 minutes Stashe takes 30 minutes to put clothes into dawes CS61C L28 CPU Design : Pipelining to Impove Pefomance I (6)

7 Sequential Laundy 6 PM AM T a s k O d e A B C D Time Sequential laundy takes 8 hous fo 4 loads CS61C L28 CPU Design : Pipelining to Impove Pefomance I (7)

8 Pipelined Laundy 12 2 AM 6 PM T a s k O d e A B C D Pipelined laundy takes 3.5 hous fo 4 loads! Time CS61C L28 CPU Design : Pipelining to Impove Pefomance I (8)

9 Geneal Definitions Latency: time to completely execute a cetain task fo example, time to ead a secto fom disk is disk access time o disk latency Thoughput: amount of wok that can be done ove a peiod of time CS61C L28 CPU Design : Pipelining to Impove Pefomance I (9)

10 Pipelining Lessons (1/2) T a s k O d e 6 PM A B C D Time Pipelining doesn t help latency of single task, it helps thoughput of entie wokload Multiple tasks opeating simultaneously using diffeent esouces Potential speedup = Numbe pipe stages Time to fill pipeline and time to dain it educes speedup: 2.3X v. 4X in this example CS61C L28 CPU Design : Pipelining to Impove Pefomance I (10)

11 Pipelining Lessons (2/2) T a s k O d e 6 PM A B C D Time Suppose new Washe takes 20 minutes, new Stashe takes 20 minutes. How much faste is pipeline? Pipeline ate limited by slowest pipeline stage Unbalanced lengths of pipe stages educes speedup CS61C L28 CPU Design : Pipelining to Impove Pefomance I (11)

12 Steps in Executing MIPS 1) IFtch: Instuction Fetch, Incement PC 2) Dcd: Instuction Decode, Read Registes 3) Exec: Mem-ef: Calculate Addess Aith-log: Pefom Opeation 4) Mem: Load: Read Data fom Memoy Stoe: Wite Data to Memoy 5) WB: Wite Data Back to Registe CS61C L28 CPU Design : Pipelining to Impove Pefomance I (12)

13 Pipelined Execution Repesentation Time# IFtch#Dcd# Exec# Mem# WB# IFtch#Dcd# Exec# Mem# WB# IFtch#Dcd# Exec# Mem# WB# IFtch#Dcd# Exec# Mem# WB# IFtch#Dcd# Exec# Mem# WB# IFtch#Dcd# Exec# Mem# WB# Evey instuction must take same numbe of steps, also called pipeline stages, so some will go idle sometimes CS61C L28 CPU Design : Pipelining to Impove Pefomance I (13)

14 Review: Datapath fo MIPS PC" instuction" memoy" d" s" t" egistes" Data" memoy" +4" imm" 1. Instuction" Fetch" 2. Decode/" Registe Read" 5. Wite 3. Execute" 4. Memoy" Back" Use datapath figue to epesent pipeline IFtch#Dcd# Exec# Mem# WB# I$ Reg D$ Reg CS61C L28 CPU Design : Pipelining to Impove Pefomance I (14)

15 Gaphical Pipeline Repesentation (In Reg, ight half highlight ead, left half wite)" Time (clock cycles) I n I$ Reg D$ Reg s Load t Add I$ Reg D$ Reg. Stoe I$ Reg D$ Reg O I$ Reg D$ Reg Sub d e O I$ Reg D$ Reg CS61C L28 CPU Design : Pipelining to Impove Pefomance I (15)

16 Example Suppose 2 ns fo memoy access, 2 ns fo opeation, and 1 ns fo egiste file ead o wite; compute instuction ate Nonpipelined Execution: lw : IF + Read Reg + + Memoy + Wite Reg = = 8 ns add: IF + Read Reg + + Wite Reg = = 6 ns (ecall 8ns fo single-cycle pocesso) Pipelined Execution: Max(IF,Read Reg,,Memoy,Wite Reg) = 2 ns CS61C L28 CPU Design : Pipelining to Impove Pefomance I (16)

17 Pipeline Hazad: Matching socks in late load 12 2 AM 6 PM T a s k O d e A B C D E F bubble Time A depends on D; stall since folde tied up CS61C L28 CPU Design : Pipelining to Impove Pefomance I (17)

18 Administivia Administivia? CS61C L28 CPU Design : Pipelining to Impove Pefomance I (18)

19 Poblems fo Pipelining CPUs Limits to pipelining: Hazads pevent next instuction fom executing duing its designated clock cycle Stuctual hazads: HW cannot suppot some combination of instuctions (single peson to fold and put clothes away) Contol hazads: Pipelining of banches causes late instuction fetches to wait fo the esult of the banch Data hazads: Instuction depends on esult of pio instuction still in the pipeline (missing sock) These might esult in pipeline stalls o bubbles in the pipeline. CS61C L28 CPU Design : Pipelining to Impove Pefomance I (19)

20 Stuctual Hazad #1: Single Memoy (1/2) I n I$ Reg D$ Reg s Load t Inst 1 I$ Reg D$ Reg. Inst 2 I$ Reg D$ Reg O I$ Reg D$ Reg Inst 3 d Inst 4 I$ Reg D$ Reg e Read same memoy twice in same clock cycle# CS61C L28 CPU Design : Pipelining to Impove Pefomance I (20) Time (clock cycles)

21 Stuctual Hazad #1: Single Memoy (2/2) Solution: infeasible and inefficient to ceate second memoy (We ll lean about this moe next week) so simulate this by having two Level 1 Caches (a tempoay smalle [of usually most ecently used] copy of memoy) have both an L1 Instuction Cache and an L1 Data Cache need moe complex hadwae to contol when both caches miss CS61C L28 CPU Design : Pipelining to Impove Pefomance I (21)

22 Stuctual Hazad #2: Registes (1/2) I n s t. O d e sw Inst 1 Inst 2 Inst 3 Inst 4 Time (clock cycles) I$ Reg D$ Reg I$ Reg D$ Reg I$ I$ Reg D$ Reg Reg D$ Reg I$ Reg D$ Reg Can we ead and wite to egistes simultaneously?# CS61C L28 CPU Design : Pipelining to Impove Pefomance I (22)

23 Stuctual Hazad #2: Registes (2/2) Two diffeent solutions have been used: 1) RegFile access is VERY fast: takes less than half the time of stage Wite to Registes duing fist half of each clock cycle Read fom Registes duing second half of each clock cycle 2) Build RegFile with independent ead and wite pots Result: can pefom Read and Wite duing same clock cycle CS61C L28 CPU Design : Pipelining to Impove Pefomance I (23)

24 Pee Instuction 1) Thanks to pipelining, I have educed the time it took me to wash my one shit. 2) Longe pipelines ae always a win (since less wok pe stage & a faste clock). 12 a) FF b) FT c) TF d) TT CS61C L28 CPU Design : Pipelining to Impove Pefomance I (24)

25 Pee Instuction Answe 1) Thoughput bette, not execution time 2) longe pipelines do usually mean faste clock, but banches cause poblems! F A L S E# F A L S E# 1) Thanks to pipelining, I have educed the time it took me to wash my one shit. 2) Longe pipelines ae always a win (since less wok pe stage & a faste clock). 12 a) FF b) FT c) TF d) TT CS61C L28 CPU Design : Pipelining to Impove Pefomance I (25)

26 Things to Remembe Optimal Pipeline Each stage is executing pat of an instuction each clock cycle. One instuction finishes duing each clock cycle. On aveage, execute fa moe quickly. What makes this wok? Similaities between instuctions allow us to use same stages fo all instuctions (geneally). Each stage takes about the same amount of time as all othes: little wasted time. CS61C L28 CPU Design : Pipelining to Impove Pefomance I (26)