ATxmega32E5/16E5/8E5. XMEGA E5 Data Sheet. Introduction. Features

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1 XMEGA E5 Data Sheet ATxmega32E5/16E5/8E5 Introduction The AVR XMEGA E5 is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. The XMEGA E5 is a 32-pins device ranging from 8KB to 32KB Flash, with 1KB to 4KB SRAM, 512Bytes to 1KB EEPROM and up to 4KB boot section. The ATxmegaE5 devices operate at a maximum frequency of 32MHz. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. Features High-performance, low-power AVR XMEGA 8/16-bit Microcontroller Nonvolatile program and data memories 8K 32KB of in-system self-programmable flash 2K 4KB boot section 512Bytes 1KB EEPROM 1K 4KB internal SRAM Peripheral features Four-channel enhanced DMA controller with 8/16-bit address match Eight-channel event system Asynchronous and synchronous signal routing Quadrature encoder with rotary filter Three 16-bit timer/counters One timer/counter with four output compare or input capture channels Two timer/counter with two output compare or input capture channels High resolution extension enabling down to 4ns PWM resolution Waveform extension for control of motor, LED, lighting, H-bridge, high drives, and more Fault extension for safe and deterministic handling and/or shut-down of external driver CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator XMEGA Custom Logic (XCL) module with timer, counter and logic functions Two 8-bit timer/counters with capture/compare and 16-bit cascade mode Connected to one USART to support custom data frame length Connected to I/O pins and event system to do programmable logic functions MUX, AND, NAND, OR, NOR, XOR, XNOR, NOT, D-Flip-Flop, D Latch, RS Latch 2018 Microchip Technology Inc. Data Sheet Complete DS A-page 1

2 Two USARTs with full-duplex and single wire half-duplex configuration Master SPI mode Support custom protocols with configurable data frame length up to 256-bit System wake-up from deep sleep modes when used with internal 8MHz oscillator One two-wire interface with dual address match (I 2 C and SMBus compatible) Bridge configuration for simultaneous master and slave operation Up to 1MHz bus speed support One serial peripheral interface (SPI) 16-bit real time counter with separate oscillator and digital correction One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter with: Offset and gain correction Averaging Over-sampling and decimation One two-channel, 12-bit, 1Msps Digital to Analog Converter Two Analog Comparators with window compare function and current sources External interrupts on all general purpose I/O pins Programmable watchdog timer with separate on-chip ultra low power oscillator QTouch library support Capacitive touch buttons, sliders and wheels Special microcontroller features Power-on reset and programmable brown-out detection Internal and external clock options with PLL Programmable multilevel interrupt controller Five sleep modes Programming and debug interface PDI (Program and Debug Interface) I/O and Packages 26 programmable I/O pins 7x7mm 32-lead TQFP 5x5mm 32-lead VQFN 4x4mm 32-lead UQFN Operating Voltage V Operating frequency 0 12MHz from 1.6V 0 32MHz from 2.7V 2018 Microchip Technology Inc. Data Sheet Complete DS A-page 2

3 Table Of Content 1 Ordering Information Typical Applications Pinout and Block Diagram Overview Resources Recommended Reading Capacitive Touch Sensing CPU Features Overview Architectural Overview ALU - Arithmetic Logic Unit Program Flow Status Register Stack and Stack Pointer Register File Memories Features Overview Flash Program Memory Fuses and Lock Bits Data Memory EEPROM I/O Memory Data Memory and Bus Arbitration Memory Timing Device ID and Revision I/O Memory Protection Flash and EEPROM Page Size EDMA Enhanced DMA Controller Features Overview Microchip Technology Inc. Data Sheet Complete DS A-page 3

4 10 Event System Features Overview System Clock and Clock options Features Overview Clock Sources Power Management and Sleep Modes Features Overview Sleep Modes System Control and Reset Features Overview Reset Sequence Reset Sources WDT Watchdog Timer Features Overview Interrupts and Programmable Multilevel Interrupt Controller Features Overview Interrupt Vectors I/O Ports Features Overview Output Driver Input Sensing Alternate Port Functions Timer Counter Type 4 and Features Overview WeX Waveform Extension Features Microchip Technology Inc. Data Sheet Complete DS A-page 4

5 18.2 Overview Hi-Res High Resolution Extension Features Overview Fault Extension Features Overview RTC 16-bit Real-Time Counter Features Overview TWI Two-Wire Interface Features Overview SPI Serial Peripheral Interface Features Overview USART Features Overview IRCOM IR Communication Module Features Overview XCL XMEGA Custom Logic Module Features Overview CRC Cyclic Redundancy Check Generator Features Overview ADC 12-bit Analog to Digital Converter Features Overview DAC Digital to Analog Converter Features Microchip Technology Inc. Data Sheet Complete DS A-page 5

6 29.2 Overview AC Analog Comparator Features Overview Programming and Debugging Features Overview Pinout and Pin Functions Alternate Pin Function Description Alternate Pin Functions Peripheral Module Address Map Instruction Set Summary Packaging Information A Z MA Electrical Characteristics Absolute Maximum Ratings General Operating Ratings Current Consumption Wake-up Time from Sleep Modes I/O Pin Characteristics ADC Characteristics DAC Characteristics Analog Comparator Characteristics Bandgap and Internal 1.0V Reference Characteristics External Reset Characteristics Power-on Reset Characteristics Flash and EEPROM Characteristics Clock and Oscillator Characteristics SPI Characteristics Two-Wire Interface Characteristics Typical Characteristics Current Consumption Microchip Technology Inc. Data Sheet Complete DS A-page 6

7 37.2 I/O Pin Characteristics ADC Characteristics DAC Characteristics AC Characteristics Internal 1.0V Reference Characteristics BOD Characteristics External Reset Characteristics Power-on Reset Characteristics Oscillator Characteristics Two-wire Interface Characteristics PDI Characteristics Errata ATxmega32E5 / ATxmega16E5 / ATxmega8E Rev. B Rev. A Revision History Rev A 08/ K 08/ J 11/ I 08/ H 07/ G 10/ F 08/ E 06/ D 06/ C 05/ B 04/ A 04/ Microchip Technology Inc. Data Sheet Complete DS A-page 7

8 1. Ordering Information Ordering Code Package (1)(2)(3) [Bytes] Flash EEPROM [Bytes] SRAM [Bytes] Speed [MHz] Power supply [V] Temp. [ C] ATxmega8E5-AU ATxmega8E5-AUR (4) ATxmega8E5-MU ATxmega8E5-MUR (4) ATxmega8E5-M4U ATxmega8E5-M4UR (4) ATxmega16E5-AU ATxmega16E5-AUR (4) ATxmega16E5-MU ATxmega16E5-MUR (4) ATxmega16E5-M4U ATxmega16E5-M4UR (4) ATxmega32E5-AU ATxmega32E5AUR (4) ATxmega32E5-MU ATxmega32E5-MUR (4) ATxmega32E5-M4U ATxmega32E5-M4UR (4) ATxmega8E5-AN ATxmega8E5-ANR (4) ATxmega8E5-MN ATxmega8E5-MNR (4) ATxmega8E5-M4UN ATxmega8E5-M4UNR (4) ATxmega16E5-AN ATxmega16E5-ANR (4) ATxmega16E5-MN ATxmega16E5-MNR (4) ATxmega16E5-M4UN ATxmega16E5-M4UNR (4) 32A (7x7mm TQFP) 32Z (5x5mm VQFN) 32MA (4x4mm UQFN) 32A (7x7mm TQFP) 32Z (5x5mm VQFN) 32MA (4x4mm UQFN) 32A (7x7mm TQFP) 32Z (5x5mm VQFN) 32MA (4x4mm UQFN) 32A (7x7mm TQFP) 32Z (5x5mm VQFN) 32MA (4x4mm UQFN) 32A (7x7mm TQFP) 32Z (5x5mm VQFN) 32MA (4x4mm UQFN) 8K + 2K 512 1K K + 4K 512 2K K + 4K 1K 4K K + 2K 512 1K K + 4K 512 2K Microchip Technology Inc. Data Sheet Complete DS A-page 8

9 Ordering Code Package (1)(2)(3) [Bytes] Flash EEPROM [Bytes] SRAM [Bytes] Speed [MHz] Power supply [V] Temp. [ C] ATxmega32E5-AN ATxmega32E5ANR (4) ATxmega32E5-MN ATxmega32E5-MNR (4) ATxmega32E5-M4UN ATxmega32E5-M4UNR (4) 32A (7x7mm TQFP) 32Z (5x5mm VQFN) 32MA (4x4mm UQFN) 32K + 4K 1K 4K Notes: 1. This device can also be supplied in wafer form. Please contact your local Microchip sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see Packaging Information on page Tape and Reel. Package Type 32A 32Z 32MA 32-lead, 7x7mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 32-lead, 0.5mm pitch, 5x5mm Very Thin quad Flat No Lead Package (VQFN) Sawn 32-lead, 0.4mm pitch, 4x4x0.60mm Ultra Thin Quad No Lead (UQFN) Package 2. Typical Applications Board controller Sensor control Motor control User interface Industrial control Ballast control, Inverters Communication bridges Battery charger Utility metering Appliances 2018 Microchip Technology Inc. Data Sheet Complete DS A-page 9

10 3. Pinout and Block Diagram Power Programming, debug, test Ground External clock / Crystal pins Digital function General Purpose I/O Analog function / Oscillators AVCC PA5 PA6 PA7 PD0 PD1 PD2 PD3 Port D GND 1 AREF ADC TC5 USART0 XCL 24 PD4 PA4 2 EVENT ROUTING NETWORK 23 PD5 DATA BUS PA3 3 Power Supervision TEMPREF Watchdog Oscillator Reset Controller 22 PD6 PA2 4 Port A Real Time Counter Event System Controller VREF Interrupt Controller Sleep Controller OCD OSC/CLK Control Prog/Debug Interface 21 PD7 PA1 5 Watchdog Timer CRC CPU EDMA Controller BUS Controller 20 PR0 PA0 6 EEPROM FLASH SRAM 19 PR1 PDI 7 DATA BUS 18 GND 8 17 VCC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC AREF ADC DAC AC0:1 Port R PDI / RESET TC4:5 USART0 SPI TWI Port C IRCOM Notes: 1. For full details on pinout and alternate pin functions refer to Pinout and Pin Functions on page Microchip Technology Inc. Data Sheet Complete DS A-page 10

11 4. Overview The AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The AVR XMEGA E5 devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel enhanced DMA (EDMA) controller; eight-channel event system with asynchronous event support; programmable multilevel interrupt controller; 26 general purpose I/O lines; CRC-16 (CRC- CCITT) and CRC-32 (IEEE 802.3) generators; one XMEGA Custom Logic module with timer, counter and logic functions (XCL); 16-bit real-time counter (RTC) with digital correction; three flexible, 16-bit timer/counters with compare and PWM channels; two USARTs; one two-wire serial interface (TWI) allowing simultaneous master and slave; one serial peripheral interface (SPI); one sixteen-channel, 12-bit ADC with programmable gain, offset and gain correction, averaging, over-sampling and decimation; one 2-channel 12-bit DAC; two analog comparators (ACs) with window mode and current sources; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The AVR XMEGA E5 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, EDMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. In each power save, standby or extended standby mode, the low power mode of the internal 8MHz oscillator allows very fast startup time combined with very low power consumption. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode and low power mode of the internal 8MHz oscillator can be enabled. Microchip offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section can continue to run. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. All AVR XMEGA devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits Microchip Technology Inc. Data Sheet Complete DS A-page 11

12 5. Resources A comprehensive set of development tools, application notes and datasheets are available for download on Recommended Reading XMEGA E Manual XMEGA Application Notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA E Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. All documentations are available from 6. Capacitive Touch Sensing The QTouch library provides a simple to use solution to realize touch sensitive interfaces on most AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression (AKS ) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate QTouch library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API s to retrieve the channel information and determine the touch sensor states. The QTouch library is FREE and downloadable from the Microchip website at the following location For implementation details and other information, refer to the QTouch library user guide also available for download from the Microchip website Microchip Technology Inc. Data Sheet Complete DS A-page 12

13 7. CPU 7.1 Features 8/16-bit, high-performance AVR RISC CPU 142 instructions Hardware multiplier 32x8-bit registers directly connected to the ALU Stack in RAM Stack pointer accessible in I/O memory space Direct addressing of up to 16MB of program memory and 16MB of data memory True 16/24-bit access to 16/24-bit I/O registers Efficient support for 8-, 16-, and 32-bit arithmetic Configuration change protection of system-critical features 7.2 Overview All AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to Interrupts and Programmable Multilevel Interrupt Controller on page Architectural Overview In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to Microchip Technology Inc. Data Sheet Complete DS A-page 13

14 Figure 7-1. Block Diagram of the AVR CPU Architecture The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. The memory spaces are linear. The data memory space and the program memory space are two different memory spaces. The data memory space is divided into I/O registers, SRAM, and memory mapped EEPROM. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data addresses 0x1000 to 0x1FFF are reserved for EEPROM. The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-programming of the application flash memory must reside in the boot program section. The application section contains an application table 2018 Microchip Technology Inc. Data Sheet Complete DS A-page 14

15 section with separate lock bits for write and read/write protection. The application table section can be used for save storing of nonvolatile data in the program memory. 7.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: Multiplication of unsigned integers Multiplication of signed integers Multiplication of a signed integer with an unsigned integer Multiplication of unsigned fractional numbers Multiplication of signed fractional numbers Multiplication of a signed fractional number with an unsigned one A multiplication takes two CPU clock cycles. 7.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash program memory 0. The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 7.6 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software. The status register is accessible in the I/O memory space Microchip Technology Inc. Data Sheet Complete DS A-page 15

16 7.7 Stack and Stack Pointer The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction. The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. 7.8 Register File The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes: One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory Microchip Technology Inc. Data Sheet Complete DS A-page 16

17 8. Memories 8.1 Features Flash program memory One linear address space In-system programmable Self-programming and boot loader support Application section for application code Application table section for application code or data storage Boot section for application code or bootloader code Separate read/write protection lock bits for all sections Built in fast CRC check of a selectable flash program memory section Data memory One linear address space Single-cycle access from CPU SRAM EEPROM Byte and page accessible Memory mapped for direct load and store I/O memory Configuration and status registers for all peripherals and modules Four bit-accessible general purpose registers for global variables or flags Bus arbitration Deterministic handling of priority between CPU, EDMA controller, and other bus masters Separate buses for SRAM, EEPROM, and I/O memory Simultaneous bus access for CPU and EDMA controller Production signature row memory for factory programmed data ID for each microcontroller device type Serial number for each device Calibration bytes for factory calibrated peripherals User signature row One flash page in size Can be read and written from software Content is kept after chip erase 8.2 Overview The AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. The available memory size configurations are shown in Ordering Information on page 8. In addition, each device has a Flash memory signature row for calibration data, device identification, serial number etc. 8.3 Flash Program Memory The AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device Microchip Technology Inc. Data Sheet Complete DS A-page 17

18 All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 8-1. Flash Program Memory (hexadecimal address) Word Address ATxmega32E5 ATxmega16E5 ATxmega8E Application Section (32K/16K/8K) 37FF / 17FF / BFF 3800 / 1800 / C00 Application Table Section... 3FFF / 1FFF / FFF (4K/4K/2K) 4000 / 2000 / 1000 Boot Section 47FF / 27FF / 13FF (4K/4K/2K) Application Section The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section Application Table Section The application table section is a part of the application section of the flash memory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here Boot Loader Section While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. When programming, the CPU is halted, waiting for the flash operation to complete. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the 2018 Microchip Technology Inc. Data Sheet Complete DS A-page 18

19 corresponding peripheral registers from software. For details on calibration conditions, refer to Electrical Characteristics on page 78. The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 8-1. The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 8-1. Device ID Bytes for AVR XMEGA E5 Devices Device Device ID bytes Byte 2 Byte 1 Byte 0 ATxmega32E5 4C 95 1E ATxmega16E E ATxmega8E E User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 8.4 Fuses and Lock Bits The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, etc. The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. An un-programmed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. Both fuses and lock bits are reprogrammable like the flash program memory Microchip Technology Inc. Data Sheet Complete DS A-page 19

20 8.5 Data Memory The data memory contains the I/O memory, internal SRAM and EEPROM. The data memory is organized as one continuous memory section, see Table 8-2 on page 21. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all XMEGA devices. Figure 8-2. Data Memory Map (hexadecimal value) Byte Address ATxmega32E5 Byte Address ATxmega16E5 Byte Address ATxmega8E I/O Registers (4K) I/O Registers (4K) FFF FFF FFF EEPROM (1K) EEPROM (512B) 13FF 11FF 11FF I/O Registers (4K) EEPROM (512B) RESERVED RESERVED RESERVED Internal SRAM (4K) Internal SRAM (2K) 2FFF 27FF 27FF Internal SRAM (2K) 8.6 EEPROM AVR XMEGA E5 devices have EEPROM for nonvolatile data storage. It is memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. EEPROM will always start at hexadecimal address 0x I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00-0x1F, single-cycle instructions for manipulation and checking of individual bits are available. The I/O memory address for all peripherals and modules in XMEGA E5 is shown in the Peripheral Module Address Map on page General Purpose I/O Registers The lowest four I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 8.8 Data Memory and Bus Arbitration Since the data memory is organized as three separate sets of memories, the different bus masters (CPU, EDMA controller read and EDMA controller write, etc.) can access different memory sections at the same time. 8.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (EDMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing Microchip Technology Inc. Data Sheet Complete DS A-page 20

21 8.10 Device ID and Revision Each device has a three-byte device ID. This ID identifies the manufacturer of the device and the device type. A separate register contains the revision number of the device I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they cannot be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 8-2 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z- pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. Table 8-2. Number of Words and Pages in the Flash Devices PC size Flash size Page Size FWORD FPAGE Application Boot bits bytes words Size No. of pages Size No. of pages ATxmega32E K+4K 64 Z[6:0] Z[14:7] 32K 256 4K 32 ATxmega16E K+4K 64 Z[6:0] Z[13:7] 16K 128 4K 32 ATxmega8E5 13 8K+2K 64 Z[6:0] Z[12:7] 8K 64 2K 16 Table 8-3 shows EEPROM memory organization for the AVR XMEGA E5 devices. EEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 8-3. Number of Words and Pages in the EEPROM Devices EEPROM Page Size E2BYTE E2PAGE No. of Pages Size bytes ATxmega32E5 1K 32 ADDR[4:0] ADDR[10:5] 32 ATxmega16E5 512Bytes 32 ADDR[4:0] ADDR[10:5] 16 ATxmega8E5 512Bytes 32 ADDR[4:0] ADDR[10:5] Microchip Technology Inc. Data Sheet Complete DS A-page 21

22 9. EDMA Enhanced DMA Controller 9.1 Features The EDMA Controller allows data transfers with minimal CPU intervention from data memory to data memory from data memory to peripheral from peripheral to data memory from peripheral to peripheral Four peripheral EDMA channels with separate: transfer triggers interrupt vectors addressing modes data matching Two peripheral channels can be combined to one standard channel with separate: transfer triggers interrupt vectors addressing modes data search Programmable channel priority From 1byte to 128KB of data in a single transaction Up to 64K block transfer with repeat 1 or 2 bytes burst transfers Multiple addressing modes Static Increment Optional reload of source and destination address at the end of each Burst Block Transaction Optional Interrupt on end of transaction Optional connection to CRC Generator module for CRC on EDMA data 9.2 Overview The four-channel enhanced direct memory access (EDMA) controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The four EDMA channels enable up to four independent and parallel transfers. The EDMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the EDMA controller can handle automatic transfer of data to/from communication modules. The EDMA controller can also read from EEPROM memory. Data transfers are done in continuous bursts of 1 or 2 bytes. They build block transfers of configurable size from 1 byte to 64KB. Repeat option can be used to repeat once each block transfer for single transactions up to 128KB. Source and destination addressing can be static or incremental. Automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events can trigger EDMA transfers. The four EDMA channels have individual configuration and control settings. This includes source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction is complete or when the EDMA controller detects an error on an EDMA channel Microchip Technology Inc. Data Sheet Complete DS A-page 22

23 To enable flexibility in transfers, channels can be interlinked so that the second takes over the transfer when the first is finished. The EDMA controller supports extended features such as double buffering, data match for peripherals and data search for SRAM or EEPROM. The EDMA controller supports two types of channel. Each channel type can be selected individually Microchip Technology Inc. Data Sheet Complete DS A-page 23

24 10. Event System 10.1 Features System for direct peripheral-to-peripheral communication and signaling Peripherals can directly send, receive, and react to peripheral events CPU and EDMA controller independent operation 100% predictable signal timing Short and guaranteed response time Synchronous and asynchronous event routing Eight event channels for up to eight different and parallel signal routing and configurations Events can be sent and/or used by most peripherals, clock system, and software Additional functions include Quadrature decoder with rotary filtering Digital filtering of I/O pin state with configurable filter Simultaneous synchronous and asynchronous events provided to peripheral Works in all sleep modes 10.2 Overview The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts, CPU, or EDMA controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It allows for synchronized timing of actions in several peripheral modules. The event system enables also asynchronous event routing for instant actions in peripherals. A change in a peripheral s state is referred to as an event, and usually corresponds to the peripheral s interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software. Figure 10-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication module (IRCOM), and XMEGA Custom Logic (programmable logic) block (XCL). It can also be used to trigger EDMA transactions (EDMA controller). Events can also be generated from software and peripheral clock Microchip Technology Inc. Data Sheet Complete DS A-page 24

25 Figure Event System Overview and Connected Peripherals CPU / Software EDMA Controller ADC AC Event Routing Network Event System Controller clk PER Prescaler Real Time Counter Timer / Counters DAC XMEGA Custom Logic IRCOM Port Pins The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow up to eight parallel event configurations and routing. The maximum routing latency of an external event is two peripheral clock cycles due to re-synchronization, but several peripherals can directly use the asynchronous event without any clock delay. The event system works in all power sleep modes, but only asynchronous events can be routed in sleep modes where the system clock is not available Microchip Technology Inc. Data Sheet Complete DS A-page 25

26 11. System Clock and Clock options 11.1 Features Fast start-up time Safe run-time clock switching Internal Oscillators: 32MHz run-time calibrated and tuneable oscillator 8MHz calibrated oscillator with 2MHz output option and fast start-up kHz calibrated oscillator 32kHz Ultra Low Power (ULP) oscillator with 1kHz output External clock options MHz Crystal Oscillator 32kHz crystal oscillator with digital correction External clock input in selectable pin location PLL with MHz output frequency Internal and external clock options and 1 to 31x multiplication Lock detector Clock Prescalers with 1x to 2048x division Fast peripheral clocks running at two and four times the CPU clock frequency Automatic Run-Time Calibration of the 32MHz internal oscillator External oscillator and PLL lock failure detection with optional non maskable interrupt 11.2 Overview AVR XMEGA E5 devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the 32MHz internal oscillator to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails. When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz output of the 8MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time. Figure 11-1 on page 27 presents the principal clock system in the XMEGA E5 family of devices. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in Power Management and Sleep Modes on page Microchip Technology Inc. Data Sheet Complete DS A-page 26

27 Figure The Clock System, Clock Sources, and Clock Distribution Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clk PER clk PER2 clk CPU clk PER4 clk RTC Brown-out Detector Watchdog Timer System Clock Prescalers clk SYS RTCSRC System Clock Multiplexer (SCLKSEL) DIV32 DIV32 DIV32 PLL PLLSRC XOSCSEL DIV4 32 khz Int. ULP khz Int. OSC khz TOSC MHz XTAL 32 MHz Int. Osc 8MHz Int. Osc TOSC1 TOSC2 XTAL1 XTAL2 PC[4] DIV Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz output of the 8MHz internal oscillator. The other clock sources, DFLL and PLL, are turned off by default. The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC Microchip Technology Inc. Data Sheet Complete DS A-page 27

28 kHz Calibrated Internal Oscillator This oscillator provides an approximate kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a kHz output and a 1.024kHz output kHz Crystal Oscillator A kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock MHz Crystal Oscillator This oscillator can operate in four different modes optimized for different frequency ranges, all within MHz MHz Calibrated Internal Oscillator The 8MHz calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency, e.g. to compensate for temperature induced frequency drift or when running at a different supply voltage than the oscillator is calibrated at in production. The oscillator employs a built-in prescaler, with 2MHz output. The default output frequency at start-up and after reset is 2MHz. A low power mode option can be used to enable fast system wake-up from power-save mode. In all other modes, the low power mode can be enabled to significantly reduce the power consumption of the internal oscillator MHz Run-time Calibrated Internal Oscillator The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30 and 55MHz External Clock Sources The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 or pin 4 of port C (PC4) can be used as input for an external clock signal. The TOSC1 and TOSC2 pins are dedicated to driving a kHz crystal oscillator PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources Microchip Technology Inc. Data Sheet Complete DS A-page 28