Fredrick M. Cady. Assembly and С Programming forthefreescalehcs12 Microcontroller. шт.

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1 SECOND шт. Assembly and С Programming forthefreescalehcs12 Microcontroller Fredrick M. Cady Department of Electrical and Computer Engineering Montana State University New York Oxford Oxford University Press 2008 EDITION

Preface xiü 3 Structured Program Design 1 1.1 1.2 1.3 1.4 1.5 1.6 1.

2 Preface xiü 3 Structured Program Design Some Basic Definitions Computers, Microprocessors, Microcomputers, Microcontrollers Motorola/Freescale Developments Leading to the HCS12 Embedded Systems Notation General Principles of Microcontrollers A Typical Microcontroller The Program Memory The Central Processor Unit The I/O Interface The Address, Data, and Control Buses Timing 2.3 Software/Firmware Development 2.4 The Software Development Tool Set Absolute Assemblers Relocatable Assemblers Compilers The Linker Creating a Relocatable Program 2.5 Remaining Questions The Need for Software Design 3.2 The Software Development Process 3.3 Тор-Down Design Understand the Problem Completely Design in Levels Ensure Correctness at Each Level Postpone Details Successively Refine Your Design Design Without Using a Programming Language 3.4 Design Partitioning 3.5 Bottom-Up Design 3.6 The Real-World Approach 3.7 Types of Design Activity 3.8 Design Tools Structured Programming Pseudocode Using Pseudocode Structured Elements as i Design Tool Top-Down Debugging and Testing Structured Programming in Assembly Language Software Documentation Software Requirements Specification (SRS) Software Design Document (SDD) Software Code Software Verification Plan (SVP) User Manuals A Top Down Design Example Seat Belt Alarm Problem Statement The Top Down Design v

vi 4 to the HCS12 Hardware 50 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.

3 vi 4 to the HCS12 Hardware The CPU, Registers, and Condition Code Bits 52 The Programmer's CPU Model 52 Control Registers 53 Operating Modes 54 Normal Single-Chip Mode 54 Normal Expanded Mode 55 Background Debug Mode 55 Memory Map 56 Addressing Modes 56 Inherent Addressing 56 Immediate Addressing 57 Direct and Extended Addressing 58 Indexed Addressing 59 Relative Addressing 63 Reset 64 Causes of Reset 65 Reset Summary An Assembler Program Assembly Language Example 68 CodeWarrior HC12 Assembler 70 Assembler Source Code Fields 70 Label Field 70 Opcode or Operation Field 71 Operand Field 71 Comment Field 77 Assembler Control 77 Assembler Directives 79 Section Definition 79 Constant Definition 82 Reserving or Allocating Memory Locations 83 Defining Constants in Memory 83 Export or Import Global Symbols 87 Assembly Control 88 Repetitive Assembly 90 Listing Control 91 Macros 93 Conditional Assembly 96 Assembler Files 100 Assembler Listing 100 Debug Listing 101 Object Files 101 Absolute Files 101 Freescale S Files Remaining Questions The Linker Assumptions Code Development Why Use a Relocatable Assembler/ Compiler and a Linker? Memory Types, Sections, and Section Types Code Section Constant Data Section Variable Data Section Stack Section Linker Operation Locating in Proper Memory Linking the Code The Linker Parameter File Parameter File Commands The Linker Output Files The Linker Map File Absolute Files Remaining Questions 7 HCS12 Instruction Set HCS12 Instruction Set 122 HCS12 Instruction and Operand Syntax 126 Addressing Modes 126 Instruction Categories 128 Move Data Instructions 128 Modify Data Instructions 130 Decision Making Instructions 133 Flow Control Instructions 134 Other Instructions 135 Load and Store Register Instructions 136 Eight-Bit Load and Store Instructions 136 Sixteen-Bit Load and Store Instructions 139 Stack Instructions 140 Load Effective Address Instructions 144 Transfer Register Instructions 145 Move Instructions 145 Decrement and Increment Instructions 148

vii 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.

4 vii Clear and Set Instructions Shift and Rotate Instructions Arithmetic Instructions Add and Subtract Decimal Arithmetic Negating and Sign Extension Multiplication Fractional Number Arithmetic Division Logic Instructions Data Test Instructions Conditional Branch Instructions Signed and Unsigned Conditional Branches Bit Test Conditional Branching Loop Primitive Instructions Unconditional Jump and Branch Instructions Branches to Subroutines Condition Code Register Instructions Interrupt Instructions Fuzzy Logic Instructions Miscellaneous Instructions I DO Debugging HCS12 Programs Program Debugging Code Walkthroughs The Debugging Plan Debugging Tools Debugging Demonstration Program Debugging Program Flow and Logic Debugging Data Elements The Source Code Listing Typical Assembly Language Program Bugs Stack Register Condition Code Register Test Data Strategies Other Debugging Techniques 10 Program Development Using С Assembly Language Programs for the HCS Assembly Language Programming Style 179 Source Code Style 179 To Indent or Not to Indent 186 Uppercase and Lowercase 186 Use Equates, Not Magic Numbers 186 Using Include Files 187 Commenting Style Structured Assembly Language Programming 188 Sequence 189 IF-THEN-ELSE Decision 189 WHILE-DO Repetition 192 DO-WHILE Repetition Interprocess Communication 195 Information in Registers 195 Information in Global Data Areas 196 Information in Local Data Areas 198 Information on the Stack 199 Using Addresses Instead of Values 202 Passing Boolean Information Assembly Language Tricks of the Trade Making It Look Pretty Major Differences Between С for Embedded and С for Desktop Applications 226 ANSI С Versus Microcontroller Implementations Architecture of а С Program 229 Startup Code 229 Void Main(Void); 230 Variables Assembly Language Interface 231 Compiler Produced Assembly Language Code 231 Using Assembly Language in С 232 In-line Assembly Bits and Bytes Accessing I/O Registers 239 Byte Addressing 239 Bit Addressing 241 Byte and Bit Addressing 2 CodeWarrior Bytes and Bits 244 Caution on Compiler Implementation Dependent Bit Addressing Interrupts 245 The Interrupt Service Routine or Interrupt Handler 245 Locating the Interrupt Service Routine 246

viii 10.7 10.8 10.9 Remaining Questions 10.10 11 HCS12 Parallel I/O 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.

5 viii Remaining Questions HCS12 Parallel I/O Families of HCS12 Processors The Register Base Address The Port Integration Module (PIM) Bidirectional I/O Ports HCS12 Parallel I/O Ports Ports A and В Port AD Port E Port J PortM PortP Ports PortT Data Direction Registers I/O Port Bit Electronics Reduced Drive Control Pull-up or Pull-down Control Polarity Selection Wired-OR Input Registers Parallel I/O Programming Parallel I/O Software Checklist Parallel I/O Software Examples More Parallel I/O Programming and Interfacing Examples Remaining Questions Parallel I/O Register Address Summary 12 HCS12 Interrupts General Interrupt System Specifications Asynchronous Events and Internal Processor Timing Enabling the Interrupts Pending Interrupts Multiple Sources of Interrupts HCS12 Interrupts The Interrupt Process The Interrupt Enable The Interrupt Disable The Interrupt Request The Interrupt Sequence The Interrupt Return Interrupt Vectors HCS12 System Vectors Initializing the Interrupt Vectors Interrupt Priorities Hardware Prioritization Software Prioritization Nonmaskable Interrupts System Reset Clock Monitor Reset Computer Operating Properly (COP) Reset Unimplemented Instruction Opcode Trap Software Interrupt (SWI) Nonmaskable Interrupt Request XIRQ_L External Interrupt Sources IRQ J. PortP Port J Interrupt Flags Resetting Interrupt Flags Resetting Interrupt Flags in С Multiple Flags with a Single Interrupt Vector Internal Interrupt Sources 12.9 Advanced Interrupts Selecting Edge or Level Triggering What to Do While Waiting for an Interrupt Initializing Unused Interrupt Vectors Other Interrupt Registers The Interrupt Service Routine or interrupt Handier Interrupt Service Routine Hints Interprocess Communication An Interrupt Program Template Remaining Question Interrupt System Register Address Summary conclusion ana unapter summary Komts HCS12 Memories Flash and EEPROM Remapping Memory Resources MC9S12C32 Memory Map Remapping Registers and Memory Locations Remapping RAM

6 ix Remapping I/O Registers 338 Remapping EEPROM 339 Memory Priorities 341 Memory Expansion 341 Programming and the Program Page Window 3 Other Memory Mapping Registers 3 Remaining Question 346 Memory System Register Address Summary HCS12Timer Basic Timer 349 Prescaler 349 Sixteen-Bit Free-Running TCNT Register 350 Timer Overflow Flag 352 Basic Timer Overflow Programming Timer Overflow Interrupts Output Compare 364 Output Compare Time Delays 366 Output Compare Interrupts 371 Output Compare Bit Operation 377 One Output Compare Controlling Up to Eight Outputs 382 Very Short Duration Pulses 388 Forced Output Compares 390 Output Compare Software Checklist Input Capture 391 Input Capture Software Checklist Pulse Accumulator 396 Pulse Accumulator Interrupts Plain and Fancy Timing Clearing Timer Flags 400 Clearing Timer Flags in С 402 Fast Timer Flag Clearing Real-Time Interrupt Pulse-Width Modulator 411 Pulse-Width Modulator Clock Control 413 Pulse-Width Modulator Control Registers 415 Using Port T Outputs for PWM Waveforms 1 Choosing Pulse-Width Modulation Counter Prescaler and Scaler Values 2 Pulse-Width Modulation Software Checklist Timer System Register Address Summary Timer Features HCS12 Serial I/O SCI and SPI Asynchronous Serial Communications Interface (SCI) SCI Data SCI Initialization SCI Status Flags SCI Flag Clearing SCI Interrupts SCI Wake-up SCI Break Character Port S SCI I/O SCI Programming Examples SCI Interfacing Synchronous Serial Peripheral Interface (SPI) Interprocessor Serial Communications SPI Data Register SPI Initialization SPI Master and Slave Modes SPI Data Rate and Clock Formats SPI Status Register SPI Interrupts SPI Programming Examples SCI and SPI Register Address Summary 16 HCS12 Serial I/O MSCAN Motorola Scalable Controller Area Network Interface (MSCAN) 469 CAN Definitions 469 CAN Serial Communications 470 MSCAN Initialization and Control Registers 476 Initialization Mode 476 CAN Bus Timing 480 MSCAN Identifiers 484 Programmer's Model of Message Storage 491 MSCAN Initialization 496 MSCAN Data Transmitter 499 CAN Transmitter Buffers 499 Transmission Aborts 502

x Remote Transmission Request and Substitute Remote Request 503 MSCAN Transmitting 503 16.5 MSCAN Data Receiver 505 MSCAN Receiving 506 16.6 MSCAN Interrupts 508 MSCAN Sleep Mode and Wake-up 508 16.

7 x Remote Transmission Request and Substitute Remote Request 503 MSCAN Transmitting MSCAN Data Receiver 505 MSCAN Receiving MSCAN Interrupts 508 MSCAN Sleep Mode and Wake-up MSCAN Errors 512 Error Detection 512 Error Signaling 512 MSCAN Error Indicators MSCAN Programming Examples 514 Explanation of Example Explanation of Example MSCAN Register Address Summary HCS12 Analog Input HCS12 A/D Converter 526 A/D Power Up 528 A/D Conversion Sequence ATDCTL3 530 A/D Resolution, Sampling Time, and Clock Selection ATDCTL4 532 A/D Input Multiplexer and Input Scanning ATDCTL5 536 A/D Operation 537 Digital Results from the A/D 540 A/D Input Synchronization 5 Polling A/D Conversion Complete 5 Clearing Status Flags 545 A/D Interrupts 545 A/D Low Power Modes 546 Digital Input to the A/D 546 Miscellaneous A/D Registers 548 A/D Programming Summary 549 Example ATD Programs 549 Remaining Questions Single-Chip Microcontroller Interfacing Techniques The Single-Chip Microcontroller 18.2 Simple Input Devices Input Switches Arrays of Switches Simple Display Devices Parallel I/O Expansion Parallel I/O Electronics Serial I/O Devices Serial Communications Interface Serial Peripheral Interface The Analog-to-Digital Converter Interface I/O Software Real-Time Synchronization Polled I/O Handshaking I/O HCS12 Fuzzy Logic Our Digital Heritage 616 How Is Fuzzy Logic Different? 617 What Is Fuzzy About Fuzzy Logic? 618 Structure of a Fuzzy Logic Inference Program 619 Fuzzification 621 Rule Evaluation 624 Defuzzification 628 Putting It All Together 630 The Complete Fuzzy Inference System 632 Fuzzy Logic 640 Fuzzy Logic Instructions 640 Minimum and Maximum Instructions 6 Table Lookup Instructions Debugging Systems Software and Hardware Breakpoints 647 Development Related Features of the MC9S12C Background Debug Module (BDM) 650 Single-Wire Physical Interface 651 Special Mode Select Function 651 Tagging Function 651 Background Communication Function 652 Application Uses for BDM 652 Nonvolatile Memory Programming 652

xi Target System Calibration 652 Field Diagnostics and Code Changes 653 Data Logging Applications 653 20.

8 xi Target System Calibration 652 Field Diagnostics and Code Changes 653 Data Logging Applications On-Chip Real-Time ICE System 653 Real-Time Bus Capture Versus Breakpoints and Single-Instruction Trace 654 Traditional External ICE 654 Benefits of On-Chip ICE 655 Features of HCS12 On-Chip ICE 656 On-Chip ICE Concepts 657 CodeWarrior User Interface to the On-Chip ICE System 660 A Simple Trace Example 661 A Practical Example of a Trace Run Designing a System Using an MC9S12C Family Microcontroller Clock Generator System Register Address Summary Appendix A: Binary Codes Appendix B: HCS12 Instruction Set Appendix C: CodeWarrior Assembler Advanced HCS12 Hardware Clocks and Reset Generator System Clock Generator System Clocks Clock Generator Control Registers External Oscillator Phase Locked Loop Oscillator PLL External Connections PLL Programming HCS12 Operating Modes Clock Generator Modes Modes at Reset Wait and Stop Modes Appendix D: HCS12 I/O Registers Appendix E: Include File Listings Appendix F: HCS12 Interrupt Vector Assignments Index 7

Design of Embedded Systems Using 68HC12/11 Microcontrollers

Design of Embedded Systems Using 68HC12/11 Microcontrollers Richard E. Haskell Table of Contents Preface...vii Chapter 1 Introducing the 68HC12...1 1.1 From Microprocessors to Microcontrollers...1 1.2