MODEL No: MTD0075AROG

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1 MODEL No: MTD0075AROG TEL: TIPS (8477) FAX: (407) WEB: Page 1

2 . Record of Revision Date Revision No. Summary Rev 1.0 was issued Page 2 of 19

3 1. Scope This data sheet is to introduce the specification of MTD0075AROG,active matrix OLED module. It is composed of an OLED panel, driver ICs and FPC. The 0.75 display area contains 128 x 128 dots. 2. Application Digital equipments which need display, instrumentation, remote control, electronic product.. 3. General Information Item Contents Unit Size 0.75 inch Dot Matrix dot Display Color Interface White / 16 gray scale SPI, I 2 C Outline Dimension 23.15x x 1.21 mm Active Area 19.18x19.18 mm Driver IC SSD1327Z Weight TBD g Operating Temperature -40 ~+70 Storage Temperature -40 ~+85 Page 3 of 19

4 4. Outline Drawing MTD Page 4 of 19

5 5. Interface signals PIN NO. PIN NAME DESCRIPTION 1 VSS Ground pin. 2 VCC Power supply for panel driving voltage. 3 VDD Power supply pin for core logic operation. VDD can be supplied externally (within the range of 2.4V to 2.6V) or regulated internally from VCI. A capacitor should be connected between VDD and VSS under all circumstances. 4 BS1 MCU bus interface selection pins. I 2 C(BS1=1);SPI(BS1=0). 5 VSS Ground pin. 6 IREF This pin is the segment output current reference pin. A resistor should be connected between this pin and VSS. 7 CS# This pin is the chip select input connecting to the MCU. The chip is enabled for MCU communication only when CS# is pulled LOW (active LOW). 8 RES# This pin is reset signal input. When the pin is pulled LOW, initialization of the chip is executed. 9 D/C# This pin is Data/Command control pin connecting to the MCU. 10 D0 When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will be 11 D1 the serial data input: SDIN and D2 should be kept NC. When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAin in application and D0 is the serial 12 D2 clock input, SCL. 13 VCI Low voltage power supply and power supply for interface logic level. It should match with the MCU interface voltage level and must be connected to external source. (Regulated internally from VCI when VCI is >2.6V) 14 VCOMH COM signal deselected voltage level. A capacitor should be connected between this pin and VSS. 15 VCC Power supply for panel driving voltage. 6. Environment Conditions 6.1 Electrical Absolute max. ratings Ta=25 Parameter Symbol MIN MAX Unit Remark Supply Voltage VCC 8 19 V Supply Voltage VCI V 6.2 Environment Conditions Item Symbol MIN MAX Unit Remark Operating Temperature TOPR Storage Temperature TSTG Page 5 of 19

6 7. Electrical Specifications 7.1 Electrical characteristics Item Symbol MIN TYP MAX Unit Remark Driver power supply VCC V Ta=25 Low voltage power VCI V Ta=25 Logic Supply Voltage VDD V High logic output level VOH 0.9*VCI -- VCI V Iout=100uA Low logic output level e VOL *VCI V Iout=100uA High logic input level VIH 0.8*VCI -- VCI V Iout=100uA Low logic input level VIL *VCI V Iout=100uA 7.2 PANEL ELECTRICAL SPECIFICATIONS PARAMETER MIN TYP. MAX UNITS COMMENTS Normal mode current consumption (ICC) Standby mode current consumption (ICC) Normal mode power consumption Standby mode power consumption ma All pixels on (1) ma 20% pixels on (1) ma Standby mode 10% pixels on (2) mw All pixels on (1) mw 20% pixels on (1) mw Standby mode 10% pixels on (2) ICI sleep mode current (Enable Internal VDD) ua Sleep mode Current (3) ICI sleep mode current (Disable Internal VDD) ua Sleep mode Current (3) ICC sleep mode current ua Sleep mode Current (3) Pixel Luminance cd/m2 Display Average Standby Luminance 20 cd/m2 CIEx (White) CIE1931 CIEy (White) CIE1931 Dark Room Contrast 2000:1 Viewing Angle 160 degree Page 6 of 19

7 Response Time 10 μs (1) Normal mode condition : - Driving Voltage : 14V - Contrast setting : 0x53 - Frame rate : 105Hz - Duty setting : 1/128 (2) Standby mode condition : - Driving Voltage : 14V - Contrast setting : 0x10 - Frame rate : 105Hz - Duty setting : 1/128 (3) Sleep mode condition : When send 0xae command OLED display off and memory data will be maintained (Disable Internal VDD during Sleep mode). (4) Wake up condition : When send 0xaf command OLED will be turned on. 7.3 LIFETIME SPECIFICATION ITEM MIN UNIT Condition Remark Life Time 10,000 Hrs 100 cd/m2, 50% checkerboard Note (1) Life Time 12,000 Hrs 80 cd/m2, 50% checkerboard Note (2) Life Time 16,000 Hrs 60 cd/m2, 50% checkerboard Note (3) Note: (A) Under Vcc = 14V, Ta = 25 C, 50% RH. (B) Life time is defined the amount of time when the luminance has decayed to less than 50% of the initial measured luminance. (1) Setting of 100 cd/m2 : - Contrast setting : 0x6d - Frame rate : 105Hz - Duty setting : 1/128 (2) Setting of 80 cd/m2 : - Contrast setting : 0x53 - Frame rate : 105Hz - Duty setting : 1/128 (3) Setting of 60 cd/m2 : - Contrast setting : 0x3a - Frame rate : 105Hz - Duty setting : 1/128 Page 7 of 19

8 7.4 FUNCTION BLOCK DIAGRAM PANEL LAYOUT DIAGRAM Page 8 of 19

9 8. Command/AC Timing 8.1 INTERFACE TIMING CHART Serial Interface Timing Characteristics (4-wire SPI) Page 9 of 19

8.2 GRAPHIC DISPLAY DATA RAM ADDRESS MAP The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128x128x4 bits.

10 8.2 GRAPHIC DISPLAY DATA RAM ADDRESS MAP The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128x128x4 bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. The GDDRAM address maps below tables show some examples on using the command Set Re-map A0h to re-map the GDDRAM. In the following tables, the lower nibble and higher nibble of D0, D1, D2 D8189, D8190, D8191 represent the 128x128 data bytes in the GDDRAM. The GDDRAM map under the following condition: Command Set Re-map A0h is set to: Disable Column Address Re-map (A[0]=0) Disable Nibble Re-map (A[1]=0) Enable Horizontal Address Increment (A[2]=0) Disable COM Re-map (A[4]=0) Display Start Line=00h Data byte sequence: D0, D1, D2 D8191 The GDDRAM map under the following condition: Command Set Re-map A0h is set to: Disable Column Address Re-map (A[0]=0) Disable Nibble Re-map (A[1]=0) Enable Vertical Address Increment (A[2]=1) Disable COM Re-map (A[4]=0) Display Start Line=00h Data byte sequence: D0, D1, D2 D8191 Page 10 of 19

11 The GDDRAM map under the following condition: Command Set Re-map A0h is set to: Enable Column Address Re-map (A[0]=1) Enable Nibble Re-map (A[1]=1) Enable Horizontal Address Increment (A[2]=0) Disable COM Re-map (A[4]=0) Display Start Line=00h Data byte sequence: D0, D1, D2 D8191 The example in which the display start line register is set to 10h with the following condition: Command Set Re-map A0h is set to: Disable Column Address Re-map (A[0]=0) Disable Nibble Re-map (A[1]=0) Enable Horizontal Address Increment (A[2]=0) Enable COM Re-map (A[4]=1) Display Start Line=78h (corresponds to COM119) Data byte sequence: D0, D1, D2 D8191 The GDDRAM map under the following condition: Command Set Re-map A0h is set to: Disable Column Address Re-map (A[0]=0) Disable Nibble Re-map (A[1]=0) Enable Horizontal Address Increment (A[2]=0) Disable COM Re-map (A[4]=0) Page 11 of 19

12 Display Start Line=00h Column Start Address=01h Column End Address=3Eh Row Start Address=01h Row End Address=7Eh Data byte sequence: D0, D1, D2 D POWER ON / OFF SEQUENCE Power ON sequence: 1. Power ON VCI. 2. After VCI becomes stable, set wait time at least 1ms (t0) for internal VDD become stable. Then set RES# pin LOW (logic low) for at least 100us (t1) (4) and then HIGH (logic high). 3. After set RES# pin LOW (logic low), wait for at least 100us (t2). Then Power ON VCC.(1) 4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after200ms(taf). Power OFF sequence: 1. Send command AEh for display OFF. 2. Power OFF VCC.(1), (2), (3) 3. Wait for toff. Power OFF VCI.(where Minimum toff=80ms (5), Typical toff=100ms) Page 12 of 19

13 Note: (1) Since an ESD protection circuit is connected between VCI and VCC, VCC becomes lower than VCI whenever VCI is ON and VCC is OFF as shown in the dotted line of VCC in above figures. (2) VCC should be kept disable when it is OFF. (3) Power pins (VCI, VCC) can never be pulled to ground under any circumstance. (4) The register values are reset after t1. (5) VCI should not be Power OFF before VCC Power OFF 8.4 APPLICATION CIRCUIT (Internal VDD: VCI =2.6V~3.5V) Recommend components: C1, C4: 4.7uF/35V(Tantalum type) or VISHAY (572D475X0025A2T) C2, C3: 1uF/16V(0603) R1: 1M ohm 1%(0603) This circuit is for SPI interface. Page 13 of 19

14 9. Optical Specification Item Symbol Condition Min Typ. Max. Unit Remark Contrast Ratio CR θ=0 2000:1 - - Note1 Note2 View Angles ΘT Degree Note 4 Response Time us Chromaticity White Red Green Blue x y x y Brightness x is on y x y Luminance L cd/m2 Note1 Note3 Note5, Note1 Note1 Note6 Note 1: Definition of optical measurement system. Temperature = 25 (±3 ) LED back-light: ON, Environment brightness < 150 lx Page 14 of 19

15 Note 2: Contrast ratio is defined as follow: Contrast Ratio = Surface Luminance with all white pixels Surface Luminance with all black pixels Note 3: Response time is defined as follow: Response time is the time required for the display to transition from black to white (Rise Time, Tr) and from white to black(decay Time, Tf). Note 4: Viewing angle range is defined as follow: Viewing angle is measured at the center point of the LCD. Page 15 of 19

16 Note 5: Color chromaticity is defined as follow: (CIE1931) Color coordinates measured at center point of LCD. area of RGB triangle S = 100% area of NTSC triangle Note 6: Luminance is defined as follow: Luminance is defined as the brightness of all pixels White at the center of display area on optimum contrast. Note 7: Uniformity. Refer to figure as below Bp = Bp (Min.) / Bp (Max.) 100 (%) Bp (Max.) = Maximum brightness in 5 measured spots Bp (Min.) = Minimum brightness in 5 measured spots. Note 8: Gamma spec. is based on Gray level 255, 250, 244, 240, 232, 224, 206, 192, 160, 128, 95, 63, 47 & 31. Page 16 of 19

Note 9: Flicker The flicker level is defined using Fast Fourier Transformation (FTT) as follows: where ffftc(n) is the nth FFT coefficient, and ffftc(0) is the 0th FFT coefficient which is DC

17 Note 9: Flicker The flicker level is defined using Fast Fourier Transformation (FTT) as follows: where ffftc(n) is the nth FFT coefficient, and ffftc(0) is the 0th FFT coefficient which is DC component. FS(Hz) is the flicker sensitivity as a function of frequency. The flicker level shall be measured with the test pattern in below. The gray leves of test pattern is 128. Note 10: Cross-talk There should be no visible cross-talk in normal direction of the display when the two Cross-talk Test Patterns below are loaded. Measurement equipment: DMS-803 or similar equipments The point should be marked is, the background of Cross-talk Test Pattern- gray are defined as middle gray scale. For example, RGB 24bit gray defined as below: Bpn = Bpn (gray) / Bpn (white) Which n means the dot No. In the Cross-talk Test Pattern ; Bpn (gray) means the brightness of the No.n spots in Cross-talk Test Pattern A and B; Bpn (white) means the brightness of the No.n spots in Full white Test Pattern; Bp (Max.) = Maximum value in A1~A4 and B1~B4. Bp (Min.) = Minimum value in A1~A4 and pb1~b4. CT=Bp (Max.)/Bp(Min.). CT must be less than 1.10 Page 17 of 19

18 10. Environmental / Reliability Tests No Test Item Condition Judgment criteria 1 High Temp Operation Ts=+70, 120hrs Per table in below 2 Low Temp Operation Ta=-40, 120hrs Per table in below 3 High Temp Storage Ta=+85, 120hrs Per table in below 4 Low Temp Storage Ta=-30, 120hrs Per table in below 5 6 High Temp & High Humidity Storage Ta=+65, 90% RH 96 hours Thermal Shock -40 C ~85 C,Dwell for 30 min. 100 (Non-operation) cycles Per table in below (polarizer discoloration is excluded) Per table in below 7 ESD (Operation) Air discharge model, ±8kV, 10 times Per table in below 8 Vibration 9 Package Drop Test Frequency : 5~50HZ, 0.5G Scan rate : 1 oct/min Time : 2 hrs/axis Test axis : X, Y, Z Height: 80cm Sequence : 1 angleǵ 3 edges and 6 faces Per table in below Per table in below INSPECTION Appearance Alignment of OLED Panel Electrical current Function / Display CRITERION(after test) No Crack on the FPC, on the OLED Panel No Bubbles in the OLED Panel No other Defects of Alignment in Active area Within device specifications Current consumption: within 50% of initial value. No Broken Circuit, No Short Circuit or No Black line No Other Defects of Display Page 18 of 19

19 11. Precautions for Use of OLED Modules 11.1 Safety The liquid crystal in the OLED is poisonous. Do not put it in your mouth. If the liquid crystal touches your skin or clothes, wash it off immediately using soap and water Handling A. The OLED and touch panel is made of plate glass. Do not subject the panel to mechanical shock or to excessive force on its surface. B. Do not handle the product by holding the flexible pattern portion in order to assure the reliability C. Transparency is an important factor for the touch panel. Please wear clear finger sacks, gloves and mask to protect the touch panel from finger print or stain and also hold the portion outside the view area when handling the touch panel. D. Provide a space so that the panel does not come into contact with other components. E. To protect the product from external force, put a covering lens (acrylic board or similar board) and keep an appropriate gap between them. F. Transparent electrodes may be disconnected if the panel is used under environmental conditions where dew condensation occurs. G. Property of semiconductor devices may be affected when they are exposed to light, possibly resulting in IC malfunctions. H. To prevent such IC malfunctions, your design and mounting layout shall be done in the way that the IC is not exposed to light in actual use Static Electricity A. Ground soldering iron tips, tools and testers when they are in operation. B. Ground your body when handling the products. C. Power on the OLED module before applying the voltage to the input terminals. D. Do not apply voltage which exceeds the absolute maximum rating. E. Store the products in an anti-electrostatic bag or container. 11.4Storage A. Store the products in a dark place at +25 ±10 with low humidity (40% RH to 60% RH). Don't expose to sunlight or fluorescent light. B. Storage in a clean environment, free from dust, active gas, and solvent Cleaning A. Do not wipe the touch panel with dry cloth, as it may cause scratch. B. Wipe off the stain on the product by using soft cloth moistened with ethanol. Do not allow ethanol to get in between the upper film and the bottom glass. It may cause peeling issue or defective operation. Do not use any organic solvent or detergent other than ethanol Cautions for installing and assembling Bezel edge must be positioned in the area between the Active area and View area. The bezel may press the touch screen and cause activation if the edge touches the active area. A gap of approximately 0.5mm is needed between the bezel and the top electrode. It may cause unexpected activation if the gap is too narrow. There is a tolerance of 0.2 to 0.3mm for the outside dimensions of the touch panel and tail. A gap must be made to absorb the tolerance in the case and connector. Page 19 of 19

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ASI-T-430FB2AN/D. Item Contents Unit. Size 4.3 inch. Resolution 480 (RGB) x 272 / Interface RGB / Technology type a-si TFT /

ASI-T-430FB2AN/D. Item Contents Unit. Size 4.3 inch. Resolution 480 (RGB) x 272 / Interface RGB / Technology type a-si TFT / Item Contents Unit Size 4.3 inch Resolution 480 (RGB) x 272 / Interface RGB / Technology type a-si TFT / Pixel pitch 0.198x0.198 mm Pixel Configuration RGB stripes Outline Dimension (W x H x D) 105.50x67.20x3.00