Compliance test method and detailed spec for - USB2.0. Tektronix Korea YJ.PARK

Transcription

1 Compliance test method and detailed spec for - USB2.0 Tektronix Korea YJ.PARK 1

2 Agenda Introduction to USB2.0 Architecture Overview Frame Work and Data Transfer USB2.0 Spec. and Compliance testing Tektronix Solution Conclusion 2

3 Brief Introduction to USB 2.0 USB2.0 is an industry standard extension to the PC architecture with it s focus on PC peripherals. USB 2.0 extends the speed from 12 Mbps on USB 1.1 to 480 Mbps providing an attachment point for next-generation peripherals which complement higher-performance PCs Full backward compatibility with existing USB 1.1 implementations 0Common Cabling 0All high speed devices must support full speed operation Easy to use connectivity 0Designed for consumer acceptance (hot-plugable) 3

4 Brief Introduction to USB 2.0 Four wire system (D+, D-, VBUS, GND) USB2.0 provides the following speed selections Data Rate Rise Time Low Speed 1.5 Mbps 75 to 300 ns Full Speed 12 Mbps 4 20 ns High Speed 480 Mbps 500 ps High speed and full speed devices may support isochronous transfers Self powered and Bus powered devices VBUS supplies power to devices that derive their primary power from the host or hub. The USB-IF has instituted a certification and marking program 0 Persuade developers to fully test their USB devices. 0 New USB trademark logo that indicates a device is certified and conforms to all applicable USB 2.0 specifications. 4

5 Architecture Overview Sample USB2.0 Topology Client Driver System S/W 5

6 Architecture Overview USB Physical Device: - A piece of hardware on the end of a USB cable that performs some useful end user function. Client Software : - Software that executes on the host, corresponding to a USB device. This client software is typically supplied with the operating system or provided along with the USB device. USB System Software: - Software that supports the USB in a particular operating system. The USB System Software is typically supplied with the operating system, independently of particular USB devices or client software. < USB Implementation Areas > USB Host Controller (Host Side Bus Interface): - The hardware and software that allows USB devices to be attached to a host. 6

7 Frame Work Powered: - USB devices may obtain power from an external source or from the USB through the hub to which they are attached. Default: - After the device has been powered, it must not respond to any bus transactions until it has received a reset from the bus. < STATE DIAGRAM > Address: - All USB devices use the default address when initially powered or after the device has been reset. Each USB device is assigned a unique address by the host after attachment or after reset. A USB device maintains its assigned address while suspended. 7

8 Frame Work Configured: - Before a USB device s function may be used, the device must be configured. The host typically requests configuration information from the USB device to determine the device s capabilities. Suspended: - In order to conserve power, USB devices automatically enter the Suspended state when the device has observed no bus traffic for a specified period. 8

9 Data Transfer DATA Transfer Types Control Transfers: - Burst, non-periodic, host software-initiated request/response communication, typically used for command/status operations. Isochronous Transfers: - Periodic, continuous communication between host and device, typically used for time-relevant information. This transfer type also preserves the concept of time encapsulated in the data. This does not imply, however, that the delivery needs of such data is always time-critical. < various characteristics > Data format imposed by the USB Direction of communication flow Packet size constraints Bus access constraints Latency constraints Required data sequences Error handling Interrupt Transfers: - Low-frequency, bounded-latency communication. Bulk Transfers: - Non-periodic, large-packet burst communication, typically used for data that can use any available bandwidth and can also be delayed until bandwidth is available. 9

10 Diagram for High Speed DC output voltage and resistance specifications ZHSDRV (including the contribution of RS), is required to be between 40.5Ω and 49.5Ω. Capacitance to Ground on each line : CHSLOAD 10 pf Matching of Capacitances to Ground : 1.0 pf 10

11 USB2.0 Compliance Testing What is Compliance testing? - Hundreds of USB2.0 devices available - The devices must conform to a strict regime of tests - Allows a developer to affix USB-IF logo Physical layer Compliance testing includes: USB2.0 Legacy tests - Signal Quality Test - Inrush current test - Drop & Droop test HS Specific tests - Packet Parameter - Receiver Sensitivity test - Timing (Suspend, Resume, Reset, Chirp test) - Monotonicity test - Impedance Measurement test 11

12 USB2.0 Compliance Testing Equipment Needed Digital Storage Oscilloscope GHz and above Differential, SE and Current Probes 0 P6248,P6245,TCP0030(TCP202) Automated Test Software & Test Fixture Data Generator (AWG) TDR (DSA8200 with 80E04) 12

13 USB2.0 Compliance Testing HS Electrical Test Tool 13

14 14 High Speed Signal Quality

15 High Speed Signal Quality High Speed Signal Quality testing includes: Eye-Diagram testing Signal Rate End of Packet Width Monotonicity test Rise and Fall times 15

16 High Speed Signal Quality SETUP HS Electrical Test Tool SETUP (Test_Packet) - A port must repetitively transmit the test packet until the exit action is taken. - This enables the testing of rise and fall times, eye patterns, jitter, and any other dynamic waveform specifications. 16

17 High Speed Signal Quality TEST RESULT & SPEC. Signal Rate Mb/s ± 0.05% Template - Eye-diagram EOP width - 7~9bit (1bit per 2.08nsec) Rise, Fall slew rate Monotonic Property - A transmitted signal should smoothly increases or decreases in amplitude without deviation in the opposite direction. 17

18 High Speed Signal Quality How is Eye-diagram Created From USB2.0 Signal - The whole waveform is spliced into 1-bit intervals - Each bit interval is aligned with the eye-mask Waveform Plot - The waveform plot gives more information by providing annotations 18

19 High Speed Signal Quality TEST PACKET FORMAT - A port in Test_Packet mode must send this packet repetitively. 19

20 20 Packet Parameter

21 Packet Parameter SETUP HS Electrical Test Tool SETUP - FOR HOST :SINGLE STEP GET DEV DESC - FOR DEVIICE : SINGLE STEP SET FEATURE 21

22 Packet Parameter Sync Field HOST SIGNAL Inter-Packet Gap DEVICE RESPONSE TEST RESULT & SPEC. Sync Field in bits: - 32 and USB Limits: 32 - Count both rising and falling edges until the first two consecutive 1 s and includes the first 1 Inter-Packet Gap in bits: - 88 ~ 192 bit (1bit per 2.08nsec) The second packet is from the host and the third is a device s response 22

23 Packet Parameter TEST RESULT & SPEC. EOP WIDTH IN SECOND PACKET EOP Width in bits: - 7~9bit (1bit per 2.08nsec) The EOP could appear as a negative,or positive going pulse on differential measurement. 23

24 24 Chirp Timing

25 Example High-speed Capable Transceiver Circuit Example High-speed Capable Transceiver Circuit 25

26 Chirp Timing SETUP Connect HS host controller to test fixture Connect DUT to test fixture Verify DUT Enumerated Connect single ended probe on D+ and D- signal lines Set up oscilloscope HS Electrical Test Tool SETUP - Enumerate Bus 26

27 Chirp Timing TEST RESULT & SPEC HOST D+ Pull-up state 2.Reset Duration 2.5us to 6 ms Disconnect the D+ pull-up resistor in the HOST 1. Chirp K Duration 1ms to 7 ms DEVICE D+ Pull-up state 5. HS terminations required < 500us after KJKJKJ : from the beginning of the last J in the Chirp KJKJKH To the time when the D+ pull-up resistor is disconnected IN THE DEVICE K(D-) J(D+) 400mV 800mV the high-speed terminations disabled HS terminations applied 27

28 Chirp Timing TEST RESULT & SPEC 3. Twtrstfs< 100uS 4. 3 KJ pairs required : 40uS< TDCHBIT<60uS 28

29 Chirp Timing High-speed Detection Handshake - In the following handshake, both the host and device are required to detect Chirp J s and K s of specified minimum durations. Chirp K 1. DEVICE s CHIRP K DURATION 2.08 (1.0 ms ms to 7.0ms) 3 JK pairs The high-speed device leaves the D+ pull-up resistor connected, and drives the highspeed signaling current into the D- line. This creates a Chirp K on the bus. The device chirp must last no less than 1.0 ms and must end no more than 7.0ms after high-speed Reset: Reset time T0. 456us 2. HIIGH SPEED TERMMINATION DISABLE (From the host) HS terminations (2.5us to 6ms) - The hub must detect the device chirp after it has seen applied assertion of the Chirp K for no less than 2.5 µs (TFILT). 3. HOST CHIRP RESPONSE TIMING ( < 100uS ) - No more than 100 µs (TWTDCH) after the bus leaves the Chirp K state, the hub must begin to send an alternating sequence of Chirp K s and Chirp J s. 29

30 Chirp Timing High-speed Detection Handshake (cont ) 4. Chirp J,K DURATION (40us to 60us) - Each individual Chirp K and Chirp J must last no less than 40 µs and no more than 60 µs. 5. HOST TERMINATION REQUIRED (From the device) ( < 500us ) - If the device detects the sequence Chirp K-J-K-J-K-J, then no more than 500 µs (TWTHS) after detection, the device is required to disconnect the D+ pull-up resistor, enable the high-speed terminations, and enter the high-speed Default state. 30

31 31 Suspend, Resume, Reset

32 Suspend, Resume, Reset SETUP Connect HS host controller to test fixture Connect DUT to test fixture Verify DUT Enumerated Connect single ended probe on D+ and D- signal lines Set up oscilloscope HS Electrical Test Tool SETUP - Suspend,Resume, Reset 32

33 Suspend TEST RESULT & SPEC SOF packet issued by HOST 0.7V revert to the full-speed configuration - by disconnecting its termination resistors - reconnecting its D+ pull-up resistor. K(D-) J(D+) 3~3.125ms 3.3V 33

34 Resume TEST RESULT & SPEC Suspend state : D+ pull up < 3ms First SOF packet issued by HOST CONCEPT If a device is in the Suspend state, its operation is resumed when any non-idle signaling is received on its upstream facing port. Resume signaling is used by the host or a device to bring a suspended bus segment back to the active condition. After resuming the bus, the host must begin sending bus traffic (at least the SOF token) within 3 ms of the start of the idle state to keep the system from going back into the Suspend state. 34

35 Reset (reset from High Speed) TEST RESULT & SPEC The last SOF packet issued by HOST 3.1~6ms SE0 RESET DEVICE D+ Pull-up state CONCEPT A hub signals reset to a downstream port by driving an extended SE0 at the port. After the reset is removed, the device will be in the Default state D+ pull-up resistor is disconnected IN THE DEVICE (HS terminations Applied) If the device is being reset from a nonsuspended high-speed state, then the device must wait no less than 3.0 ms and no more than 6 ms before reverting to full-speed. The device should transmit a chirp handshake following the reset. 35

36 Reset (reset from Suspend) TEST RESULT & SPEC suspend RESET DEVICE D+ Pull-up state 2.5us~6ms D+ pull-up resistor is disconnected IN THE DEVICE (HS terminations Applied) CONCEPT Reset must wake a device from the Suspend state. It is required that a high-speed capable device can be reset while in the Powered, Default, Address, Configured, or Suspended states The device should transmit a chirp handshake following the reset. Time between the falling edge of the D+ and the start of the device chirp-k : 2.5us ~6ms 36

37 37 Receiver Sensitivity

38 Receiver Sensitivity Test description 0Verify that the DUT responds with a SE0 NAK to an IN packet with a minimum 150 mv peak 0Verify that DUT does not respond when balanced peak amplitude is less than or equal to 100 mv 0Verify that DUT responds to a IN packet with a 12 bit sync field 38

39 Receiver Sensitivity SETUP EC HI Por t AWG5012 or above(with 14dB attenuator) 39

40 Receiver Sensitivity Receiver Sensitivity Procedure Connect Data Generator to SMA connectors on receiver sensitivity segment of compliance test fixture Data generator outputs IN_packets at >250 mv peak Connect DUT to DUT connection on compliance test fixture Connect Host Controller to Host connection on test fixture Verify DUT enumerated Place DUT into SE0_NAK test mode (bus contention visible on scope) Switch test fixture to Test position Verify DUT responds to IN_packet from data generator Gradually reduce and balance data generator peak to peak amplitude to the DUT until DUT no longer responds with SE0_NAK Record peak amplitude. Reduce amplitude to 100 mv peak, verify no response from DUT Repeat with Short sync IN_packet 40

41 Receiver Sensitivity Tests the minimum amplitude the DUT will respond to a legal message. Screenshot illustrates AWG generating IN packet to cause DUT to respond. Semi-Automated test records minimum amplitude 41

42 Receiver Sensitivity (Squelch Test) Verifies that the DUT does not respond to an illegal message Illustrates AWG generated IN packet with illegal amplitude (too low) Shows the DUT does not respond Semi-Automated measurement records amplitude level 42

43 43 Inrush Current

44 Inrush Current SETUP Connect current probe (Tektronix TCP202) to wire loop in series with V bus of the DUT Perform a hot attach of the DUT to the Host through the compliance test fixture Observe inrush current spike on oscilloscope Note: devices present a wide range of inrush phenomenon in terms of trigger level, current spike amplitude, bus powered & self powered. Modification of scope setups is to be expected. 44

45 Inrush Current TEST RESULT & SPEC Edge rate must not exceed 100A/us. Charge :< 51.5uC. MAX load Capacitance : <10uF Inrush Current is calculated by recording all the current values above the 100 ma current level throughout the signal. This signal is integrated to get the total charge greater than 100 ma. This is the charge in Coulombs and is calculated using the equation Where: C is the capacitance. Q is the charge. V is the voltage. The supply voltage is one of the inputs to Inrush measurement. 45

46 46 Droop Testing

47 Droop Test SETUP Connect single ended probe to to V bus of port under test (USB-IF recommends the Tektronix P6245) Connect switching (2 Hz) dynamic load to adjacent Connect 100 ma loads to remaining ports of bus powered DUT or 500 ma loads to self powered DUT Evaluate voltage droop with oscilloscope 47

48 Droop Test TEST RESULT & SPEC < 330mV The maximum droop in the VBUS is 330 mv A high-power bus-powered device that is switching from a lower power configuration to a higher power configuration must not cause droop > 330 mv on the VBUS at its upstream hub. The device can meet this by ensuring that changes in the capacitive load it presents do not exceed 10 µf. 48

49 Impedance Measurement Termination Impedance (80 Ohms < ZHSTERM < 100 Ohms ) The connector reference time is determined by disconnecting the TDR connection from the port connector and noting the time of the open circuit step. For an A connector, the measurement time is 8 ns after the connector reference location. For a B connector, the measurement time is 4 ns after the connector reference location. Through Impedance (70 Ohms < ZHSTHRU < 110 Ohms) Through Impedance (ZHSTHRU) is the impedance measured from 500 ps before the connector reference location until the time governed by the Termination impedance specification. 49

50 Impedance Measurement TEST RESULT & SPEC Termination Impedance Through Impedance 50

51 Tektronix Solution & Conclusion Fully compliant with USB-IF tests for USB2.0 Compliance testing Automated Eye-diagram analysis Statistical result details for In-depth analysis Auto oscilloscope set-ups eliminate time consuming manual set-ups Report generation formats Automatic Report Generation On-line help provides assistance TDSUSB2 helps to ensure that your device achieves USB-IF compliance TDSUSB2 takes the complexity out of USB electrical testing 51

52 Thank you and Questions? 52