Today s Schedule. USB 2.0 Overview. USB 2.0 Compliance Testing. Demo of the Agilent Solution Q&A
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1 N5416A Automated USB 2.0 Pre-Compliance Test Solutions
2 Today s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Q&A
3 USB 2.0 Overview USB Integrators Forum Created by Compaq, Hewlett- Packard, Intel, Lucent, Microsoft, NEC and Philips The USB-IF ( governs the specification and use of USB, and resolves any issues that arise
4 USB 2.0 Overview Data Rates USB Peripherals can be Host, Device or Hub The USB-IF combined all USB 1.1 and 2.0 speed buses into the USB 2.0 specification USB 2.0 consists of 3 modes-- Data Rates Rise Times Low-speed (LS) 1.5 Mb/s 75ns 300ns Full-speed (FS) 12 Mb/s 4ns 20ns High-speed (HS) 480 Mb/s 500ps USB 2.0 now offer Host/Device Dual Role Peripherals This capability is referred as OTG
5 USB 2.0 Overview Physical Characteristics Cables can be up to 5m long; hubs up to 5 levels deep Downstream data flows from PC to peripherals Upstream data flows from peripherals to PC USB Cable + Shield VBUS D+ D- Ground
6 USB 2.0 Overview Signal Levels Signal Level Transfer Full/Low Speed 3.3V, 12/1.5Mbps High Speed 400mV, 480Mbps Required bandwidth BW = 0.35/T r = ~1 GHz (T r = ~400 ps)
7 USB 2.0 Overview Path Impedances Characteristic measurements during mechanical test (High/Full speed cables Characteristic Impedance Differential 90 15% Common Mode 30 30% Cable Attenuation Propagation Delay 400MHz 26ns D+/D- Propagation Skew 100ps
8 USB 2.0 Overview Transmission Modes Full Speed and Low Speed modes are determined by the location of the R pu resistor (on D+ or D-). The bus starts in full speed mode using the R pu resistor After Chirp Handshake, if high speed mode is available, the R pu resistor is disconnected and bus changes to high speed mode.
9 USB 2.0 Overview Full Speed Packet Makeup Packet 1 Packet 2 Packet 3 SYNC PID(SOF) Frame No. CRC EOP SYNC PID(IN) ADDR ENDP CRC EOP SYNC frame PID(NAK) EOP
10 USB 2.0 Overview High Speed Packet Makeup Signal Amplitude 400mV SYNC: 32(Minimum 12) bit Idle : SE0 EOP re-definition: NRZ w/o bit stuffing (SOF EOP is 40 bit) SYNC PID(IN) ADDR ENDP CRC EOP
11 Today s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
12 USB 2.0 Compliance Testing Involves a set of test procedures (available from performed in a specific order The USB 2.0 HS test procedure (v1.0) has been available since December 2001 The USB-IF performs the official compliance testing
13 USB 2.0 Compliance Testing Interoperability Test
14 USB 2.0 Compliance Testing Electrical Tests Full/Low speed signal quality In-rush current Droop/Drop Backdrive voltage High speed test OTG Specific Tests FS/LS HS
15 USB 2.0 Compliance Testing Required Test Software INTEL HS Electrical Test Tool In order to place your USB 2.0 Device in Test Modes you will need Intel HS Electrical Test Tool installed on a Windows based PC. Full Speed Tests requires Loop Descriptor Mode High Speed Test requires HS Test Packets Mode
16 USB 2.0 Compliance Testing Full/Low Speed Tests Signal quality In-rush current Droop/Drop Backdrive voltage
17 USB 2.0 Compliance Testing Full/Low Speed Signal Quality USB Test Process 1. Connect Probe to Test Fixture 2. Connect device to Test Fixture 3. Place Device in Loop Descriptor test Mode 3. Select Proper Test in N5416A Script 4. Run Test
18 USB 2.0 Compliance Testing DEVICE Upstream Host / System Up stream USB System (PC) Oscilloscope Hub Devices HUB HUB HUB HUB Adjacent Device In FS tests, connect D+ of the adjacent device to scope ch 3 Connect D+ to ch 2 Connect D- to ch 1 HUB SQiDD 5m cable DUT
19 USB 2.0 Compliance Testing Full/Low Downstream Setup
20 USB 2.0 Compliance Testing Upstream Trigger Setup The logic trigger occurs when the EOP is reached and the Adjacent device is idle (Trigger Setup is done automatically)
21 USB 2.0 Compliance Testing Measurement Data Automated Measurement Setup & Result
22 USB 2.0 Compliance Testing Full Speed Test Results Example Signal eye: *** eye failure! (14 data points violate eye) *** *** waiver granted. *** EOP width: ns EOP width passes Consecutive jitter range: ps to ps RMS jitter ps Paired KJ jitter range: ps to 0.00ps, *** jitter failure *** *** waiver granted ***
23 USB 2.0 Compliance Testing Understanding Full Speed Test Results Measurement Items: D+ green D- blue common mode voltage purple crossover location yellow eye diagram ref. eye violation diamond yellow circle red dots
24 USB 2.0 Compliance Testing Device Inrush Current Test Types of Devices Tested Bus powered devices Self-powered devices V bus attach >120µf <10µf GND
25 USB 2.0 Compliance Testing Device Inrush Current Test Bus or self-powered USB devices Protects upstream devices from damage 50.0 µc limit Required Tests Overall result: fail! Inrush at 5.000V: 503C *** inrush failure! *** (at 5.000V, maximum compliant inrush is 50C)
26 USB 2.0 Compliance Testing HOST/HUB Droop/Drop The HUB/Host Test: When a adjacent device is connected, the V BUS droop voltage must be within 330mV
27 USB 2.0 Compliance Testing DEVICE Backdrive Voltage Voltage measured on D+, D-, and VBUS upon power-up After enumeration, USB plug is disconnected and voltage is measured on D+, D-, and VBUS Both measured with 15 kω resistor to ground Voltages must not exceed 0.4 V under any of these conditions
28 USB 2.0 Compliance High Speed Testing Required Test Equipment Scope BW >=2GHz
29 USB 2.0 Compliance Testing High Speed Test High Speed Signal Quality Time Domain Reflectometry( TDR ) Reciever Sensitivity and Squelch J and K Voltage CHIRP Packet Parameters Suspend/Resume
30 USB 2.0 Compliance Testing HS Electrical Test Tools The test mode can be any of the following: Test J Test K Test _SE0_NAK Test Packet Test Force Enable
31 USB 2.0 Compliance Testing HS Signal Integrity Test packet output by HS Electrical Test Tool The signal is isolated from the host by the HS Test Fixture Waveform is measured through a 90 ohm differential termination Differential Probe HS Relay 90Ω Device
32 USB 2.0 Compliance Testing Measuring High Speed Signal Quality Test packet output
33 USB 2.0 Compliance Testing HS Signal Quality Test Results Required Tests Overall result: pass! Signal eye: eye passes EOP width: 7.98 bits EOP width passes Receivers: reliable operation on tier 6 receivers pass Measured signaling rate: MHz signal rate passes
34 USB 2.0 Compliance Testing Device HS Signal Quality EL_2 Data rate specification (480 Mb/s 0.05%) EL_4 TP3 eye pattern requirement EL_5 TP2 eye pattern requirement (device with captive cable) EL_ % differential rise/fall times (longer than 500ps) EL_7 Monotonic data transitions for high speed drivers in the eye pattern template
35 USB 2.0 Compliance Testing HS Packet Parameters The device is controlled by the Electrical Test Tool on the PC The reply packet from the device is received and evaluated for: Sync EOP Spacing between packets
36 USB 2.0 DEVICE Compliance Testing HS Packet Parameters Sync Field : 32 bit EOP : 8 bit
37 USB 2.0 DEVICE Compliance Testing CHIRP, SUSPEND/RESUME/RESET Timing USB Test Fixture Probe Probe 90Ω Device
38 USB 2.0 DEVICE Compliance Testing CHIRP Test Reset duration CHIRP K Duration HS termination assertion Device s Chip Latency (2.5us <-> 3ms) Chirp KJKJKJ (500us ) Device turns on HS termination CHIRP K (1ms <-> 7ms)
39 USB 2.0 DEVICE Compliance Testing CHIRP Test Device s Chip Latency (2.5us <-> 3ms) Enable High Speed Termination After Chirp KJKJKJ (within 500us)
40 USB 2.0 DEVICE Compliance Testing Suspend Timing Suspend : 3.000ms <-> 3.125ms D+ Voltage > 2.7V
41 USB 2.0 DEVICE Compliance Testing Resume Timing Resume : < 2 bit time
42 USB 2.0 DEVICE Compliance Testing Reset Timing Device CHIRP K Reset : 3.1ms <-> 6ms
43 USB 2.0 DEVICE Compliance Testing Reset Timing Reset from Suspend : 2.5us <-> 3.000ms
44 USB 2.0 DEVICE Compliance Testing High Speed Receiver Sensitivity Automated control Pulse Generator SMA Device HS Relay In SE0_NAK test mode, pulse generator outputs IN token; device must not respond to tokens <100mV and must respond to tokens >150mV
45 USB 2.0 DEVICE Compliance Testing High Speed Receiver Sensitivity Data generator Packet Device response Packet
46 USB 2.0 DEVICE Compliance Testing High Speed Receiver Sensitivity Note: A waiver may be granted if the receiver does not indicate squelch at +/-50mV of 150mV differential amplitude
47 USB 2.0 DEVICE Compliance Testing Time Domain Reflectometry Confirm the signal is less than 10mV TDR Use TDR to measure impedance of connector, circuit board, and active termination SMA DEVICE HS Relay
48 USB 2.0 DEVICE Compliance Testing TDR Test Results 70 Z HSTHRU Z HSTERM 100 Differential impedance USB Connector Termination impedance Thru impedance D- odd impedance D+ odd impedance
49 Today s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
50 Examples of Compliance Tests Test Example 1: Impedances The effects of source and termination impedances A(w H(w) Z S Z 0 T(w) R 1 (w) H(w) Z S Z 0 Z L R 2 (w) Unregulated output impedance of a driver could cause significant overshoot or undershoot
51 Examples of Compliance Tests Test Example 2: Full Speed *** Overall result: fail! *** Signal eye: *** eye failure! *** (33 data points violate eye)
52 USB OTG Compliance Testing Get Completely Automated Certification of USB OTG Peripherals N5416A Software provides Automated control of: N5417A USB OTG Test Fixture to sequence tests E3631A Power Supply 34401A Voltmeter. Equipment list for complete Automation: Agilent Oscilloscope with >=2GHz BW N5416A USB Compliance software 2 High Impedance Passive Probes 82357B USB->GPIB Adapter or equiv. Agilent E3631A Powersupply or equiv. Agilent 34401A Multimeter or equiv. GPIB Cable 10833B or equiv.
53 Examples of Compliance Tests Test Example 2: A Detailed Look Coupling between D+ and D-
54 Examples of Compliance Tests Cautions with USB 2.0 Measurements Hub quality can affect full/low speed upstream measurements For identical measurements to those in compliance tests, use Intel s CHUB For high speed signal quality measurements, take care in handling low level signals. Be careful of: Adjusting the offset and performing calibration Effects of fixturing impedance on signal quality The bandwidth of the probe
55 Today s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
56 Today s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
57 Conclusion Summary Compliance testing is a requirement Compliance testing involves framework layer evaluation and physical layer evaluation In physical layer evaluation, signal quality is influenced by components, circuit layout, and driver circuitry An easy-to-use oscilloscope is an important factor in efficiently performing compliance testing
58 Conclusion Reference Material Universal Serial Bus Specification Rev 2.0 (USB-IF) USB-IF Signal Integrity Test Description (USB-IF) USB Design by Example (John Hyde, John Wiley & Sons INC) Universal Serial Bus System Architecture (Don Anderson, MINDSHARE INC) USB 2.0 High Speed Electrical Test Procedure v1.0
59 Recommanded USB 2.0 Test Configurations DSO90254A Agilent 2.5GHz Oscilloscope (or DSO80204A/B or 54852A) N5416A USB 2.0 Compliance test Application High Speed Tests: 5 Self Powered High Speed USB Hubs + 5m USB Cables E2649B USB 2.0 HS Test Fixtures 1130A 1.5GHz Differential Probe +E2678A Socket-in Probe Head 81134A Pulse Pattern Generator (optional for Squelch Test) OTG Tests: N5417A USB 2.0 OTG Automated Test Fixture 82357A/B USB to GPIB Interface (Optional) 34401A Voltmeter (Optional) E3631A Power Supply (Optional) 10833B GPIB Cable (Optional) Low/Full Speed Tests: 1 Self Powered FULL Speed USB Hub 4 Self Powered High Speed USB Hubs + 5m USB Cables E2646A LS/FS USB Test Fixture 3 High Impedance Passive Probes or 3 Single Ended Active Probes USB Powered Devices/HUB Inrush Current -> N2774A Current Probe +N2775A Probe PSU
60 Today s Schedule USB 2.0 Overview USB 2.0 Compliance Testing Examples of Compliance Tests Demo of the Agilent Solution Conclusion Q&A
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