Application Note Features A[31:28] GLUE LOGIC (PLD) A[2] [Gnd:Vcc] Figure 1. TMS320C6202 to PCI Subsystem

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1 PCI 9054/C6202 AN July 31, 2000 Texas Instruments TMS320C6202 DSP to PCI 9054 Version 2.0 Application Note Features Preliminary Application Note for designing a PCI adapter or embedded system based on the TI TMS320C6202 DSP processor and the PLX PCI 9054 Superior PCI performance based on PCI 9054 bus master interface chip which supports: PCI burst master, DMA and slave cycles PCI configuration cycles I 2 O Messaging Unit General Description This application note describes how to interface the Texas Instruments TMS320C6202 digital signal processor to the PCI bus using the PLX PCI 9054, 32-bit, I/O Accelerator Device using the host-port interface (HPI.) The information can be used to build either a PCI adapter or a host. The PCI 9054 has a Direct Master, DMA and Direct Slave data transfer capabilities. The Direct Master mode allows a device (TMS320C6202) on the Local bus to perform memory, I/O, and configuration cycles to the PCI bus. The Direct Slave gives a master device on the PCI bus the ability to access memory on the Local bus. The PCI 9054 allows the Local bus to run asynchronously to the PCI bus through the use of bi-directional FIFOs. In this design example, the PCI bus runs at 33 MHz while the Local bus can be clocked at up to 50 MHz. PCI 9054 TI C6202 PCI BUS AD[31:0] PAR CBE[3:0] FRAME# IRDY# TRDY# STOP# DEVSEL# IDSEL PERR# SERR# REQ# GNT# RST# CLK LAD[31:0] LBE[3:0] LSERR# WAIT# BLAST# LW/R# BREQo ADS# CCS# LINT# READY# BTERM# LHOLDA LHOLD LRESETo# MODE[1:0] BIG_END LCLK A[31:28] GLUE LOGIC (PLD) [Gnd:Vcc] A[2] XD[31:0] XBE_[3:0] EXT_INT4 XWAIT_ XBLAST_ XW/_R XBOFF XAS_ TOUT EXT_INT5 XCNTL XCS_ XRDY_ XHOLDA XHOLD RESET_ CLKO Enhanced DMA Controller Memory Controller Bus Arbitration EMIF Vcc Serial EEPROM Clock Oscillator Figure 1. TMS320C6202 to PCI Subsystem ª PLX Technology, Inc., 2000 PLX Technology, Inc, 390 Potrero Avenue, Sunnyvale, CA 94085, Phone , Fax Products and Company names are trademarks/registered trademarks of their respective holders.

2 TABLE OF CONTENTS 1. INTRODUCTION ARCHITECTURE PCI 9054 BUS MODE USED CONTROL SIGNAL CONNECTIONS PROGRAMMABLE LOGIC ASSUMPTIONS REFERENCES... 6 TABLE OF FIGURES Figure 1. TMS320C6202 to PCI Subsystem... 1 Figure 2. PCI 9054 to 'C6202 PLD PLX Technology, Inc. All rights reserved. i

3 1. INTRODUCTION This brief application note will describe the interconnect between the TI TMS320C6202 and the PCI bus using the PLX PCI 9054 PCI to Local bus bridge IC. This application note can be used as a basis to build either a PCI adapter or host to plug into a PCI bus backplane, or for building an embedded system. The interconnect between the two LSI ICs also requires the use of extra logic, usually in the form of a PLD or other programmable logic, to provide decode, etc. Figure 1. TMS320C6202 to PCI Subsystem, shows the connections between the PCI 9054, the TI C6202 and the PLD. Figure 2 shows the detail in the PLD. The interconnect between the PCI 9054 and the TI C6202 is simplified by the HPI bus included in the C6202. This is an improvement on the earlier HPI bus included in TI DSP s in that it is a 32-bit, instead of a 16-bit, bus interface, which makes the C6202 s 32-bit HPI bus look like a J-mode interface to the PCI This interface optimizes the data rate between the two devices for high-speed burst transfers. The Direct Master mode allows the TI C6202 to perform memory, I/O and configuration cycles to the PCI bus. The PCI 9054 also contains a powerful chaining DMA controller. Although it is not discussed in this design example, it can be used with no changes to the hardware. For long and efficient burst transfers between a PCI host and an adapter s memory, the DMA mode should be considered. The Direct Slave mode gives a master device on the PCI bus the ability to access the TI C6202 s configuration registers or memory on the Local bus. This allows for burst or single cycle direct slave transfers. The PCI 9054 allows the Local bus to run asynchronously to the PCI bus through the use of bidirectional FIFOs. The PCI bus runs at 33 MHz while the Local bus is clocked up to 50 MHz. Although the PCI 9054 by itself can run up to 50 MHz on the Local bus, it is limited by the C6202 timing. For example, when the C6202 is the bus master, the sum of the set-up time and the clock-toout delay for the LBE[3:0]# signals is Tsu(of PCI 9054) + Tco(of C6202) = 9ns ns = 25.5 ns. The result is a Local bus that is running at 39 MHz. Another example is when the PCI 9054 is a bus master. The sum of the set-up time, the combinatorial logic time of PLD, and clock-to-out delay of the READY# signal is Tsu(of PCI 9054) + Tcomb(of PLD) +Tco(of C6202) = 9.5 ns + Tcomb ns. Therefore, the Local bus clock frequency would depend on the value of Tcomb delay of the PLD. 2. ARCHITECTURE The PCI 9054 to C6202 interconnect is rather straightforward, with the exception of a single PLD that is used to translate a few signals between the two devices. One function that is performed in the PLD is to decode the XBISA and XBD registers of the C6202. These registers are used for transferring data into the C6202 from an expansion bus master. Another function that must be performed is decoding the PCI 9054 s internal registers, when the C6202 is the expansion bus master. 256 locations are shown being decoded, but that number can be changed if desired. Another function that has to be controlled by the PLD is the local interrupt line from the C6202 to the PCI This line is a shared line between the LINT# output and the LINT# input. The way it works, or the way to think of it, is like an open drain output, being pulled high with a current source (about 100K Ohms equivalent), and the input tied to the open drain output. The only issue with this type of a single pin operation is to make sure the interrupting device does not service its own interrupt. So if a PCI device interrupts the local processor (the C6202), it will have to mask the return interrupt seen on the LINT# input. This is accomplished by disabling the LINT# input in the INTCSR register. Additionally, the C6202 has to somehow tie two interrupt lines, EXT_INT5 (the interrupt input used) and TOUT (a timer output line used to generate interrupts). We cannot simply tie both lines together to the PCI 9054 s LINT#, as the C6202 will generate an interrupt to itself when it assets TOUT. The PLD shows a method to separate the single line interrupt with tri-state buffers and inverters in a PLD. Another method of doing this would be to simply delete the TOUT signal and generate a software interrupt with a write to the INTCSR register. The only drawback to this would be the C6202 would have to wait for the Local bus to become free if the PCI 9054 had control of it. Finally, there is a circuit in the PLD to cue the C6202 when a PCI Master or Target abort occurs. When this happens, data on the bus is not valid, so the DSP must be alerted to take appropriate action. This circuit gates READY# output with BTERM# output PLX Technology, Inc. All rights reserved. 2

4 2.1 PCI 9054 Bus Mode Used To connect the PCI 9054 to the TI C6202, the J-bus mode was chosen. This is due to the fact that the 32-bit HPI interface is essentially a J-mode interface. Although a small amount of glue logic is necessary to split some of the dual-function pins on the 9054 apart, it is vastly superior than the 16-bit HPI interface used on earlier 620X DSP processors. 2.2 Control Signal Connections Below is a list of the PCI 9054 signals, (their corresponding C6202 signals), and a brief description of what they do: LAD[31:0] (XD[31:0]) Multiplexed 32-bit address and data bus. LBE[3:0] (XBE_[3:0]) Byte enables for the different byte-wide lanes on the 32-bit bus. Used by the expansion bus for write only. LSERR# - (EXT_INT4) Local bus system error interrupt output, used to interrupt the C6202 in case of a Master or Target abort. LHOLD (XHOLD) bus arbitration signal used by the PCI 9054 to arbitrate for the local HPI interface bus. BLAST# - (XBLAST_) Burst last signal driven by the current Local bus Master to indicate the last transfer in a bus access. LW/R# - (XW/R_) Local read/write line. BREQo (XBOFF) bus request output, used to signal the C6202 that the PCI 9054 is in need of the Local bus for a PCI-to-Local bus access while the C6202 has control of the Local bus. ADS# - (XAS_) Address strobe, used to signal the start of a physical address transfer, and to latch the address value into the PLD to decode various register address spaces. LHOLDA (XHOLDA) Acknowledge signal for the Local bus arbitrator in the C6202. CCS# Chip select used by the Local bus to access all of the registers in the PCI bytes are decoded in the PLD, at least 16B hex needed. LINT# (TOUT, EXT_INT5) Local interrupt input/output. Used to signal an incoming or outgoing interrupt for the Local bus. Since the C6202 doesn t have an interrupt output on the HPI interface, a timer is used to generate an interrupt at a given frequency. The interrupt input is handled by the EXT_INT5 pin. READY# - (XRDY_) Ready line, indicating data on the Local bus is valid. Gated by the BTERMo signal when used in the PCI 9054 output mode. BTERM# Used to gate READY# in PCI 9054 output mode in the event of a Master or Target abort. A[2] (XCNTL) Used as a select between the XBD and the XBISA register in the C6202 in conjunction with decoding the address locations of these two registers. (XCS_) Chip select for the C6202 s HPI register. The PLD decodes the appropriate address locations, here set to 0040_000 for the XBD register, and 0040_0004 for the XBISA register. WAIT# - (XWAIT_) Wait line signaling the PCI 9054 that the C6202 is not ready. LRESETo# - RESET_ - Reset generated from the PCI bus to the Local bus to reset the DSP in the event of a system reset. BIGEND Used to select between Big and Little Endian bus numbering. J-mode interfaces are all Little Endian. MODE0, MODE1 Used to select between the three different interface modes on the PCI Shown is the mode for J-mode. The C6202 is a 1.8 Volt core, 3.3 Volt I/O device, while the PCI 9054 is a straight 3.3 Volt device with 5 Volt tolerant I/O. Therefore, no level translators are necessary between the two devices. LCLK (XCLK) Local bus clock input. Can be either a separate clock oscillator, or a dividend of the C6202 s master clock (as long as it is under 50 MHz.) 2000 PLX Technology, Inc. All rights reserved. 3

6 2.3 Programmable Logic Although both the PCI 9054 and the C6202 have J-mode interfaces, there are enough small differences between the two devices to warrant a PLD to fix-up some of the signals. The PLD accomplishes several tasks: 1. Decodes the address locations of the HPI registers XBD and XBISA. 2. Decodes 256 locations for access to the PCI 9054 s configuration registers by the C Splitting the dual-purpose interrupt line LINT# on the PCI 9054 into two signals that the C6202 can handle. 4. Splitting and gating the dual-purpose signal READY# on the 9054 to allow for ignoring data on the Local bus during a Master or Target abort. For this a PLD with at least 43 I/Os is needed, of this at least 35 inputs are necessary for decoding the address spaces of the two devices. The PAL or Verilog equations for the decoder should be fairly straightforward, needing to decode 0040_0000 and 0040_0004 respectively for the HPI registers, and from 0030_0000 to 0030_01FF for the PCI registers. These address locations are completely arbitrary, and can be changed to suit a particular design. The handling of the LINT# line is a bit more complicated. The LINT# line is an open-drain output, with about a 100K pull-up, and an input stage tied to the same node. The LINT# line can be driven low by the PCI 9054 for an interrupt incoming to the Local bus, or it can be driven low by the C6202 (since it is open-drain) for an interrupt outgoing from the Local bus. Unfortunately, the C6202 doesn t have dualpurpose interrupt lines. Therefore, the LINT# line needs to be broken into a discrete input and output to connect to EXT_INT5 (for the incoming interrupt) and TOUT (for the outgoing interrupt.) TOUT is actually a timer output that is brought into interrupt duty by setting a fixed time in the C6202 and allowing it to interrupt the PCI bus on occasion. Care must be taken when designing the PLD such that glitches are not generated when the TOUT line toggles from low-to-high and vice-versa. In this example the timer has priority over interrupts coming from the PCI bus. So if a PCI interrupt has priority over the DSP, the interrupt service routine must first reset the TOUT timer, then fetch the remainder of the interrupt. A bit more complicated is the READY# line in case of a Master or Target abort. If a Master/Target abort occurs, data on the Local bus is either bad or we don t care about it. Therefore, we have to gate it with BTREM#, since after a Master or Target abort, BTERM# will be asserted. When this happens, the gated READY# line is false, signifying that the data on the bus is not valid. The buffers to split READY# are enabled by HOLDA, which is the arbiter acknowledge from the C ASSUMPTIONS This application note is based on the following assumptions: 1. The fact that the PCI 9054 uses a bi-functional line for local interrupts (LINT#) is a bit of an inconvenience, especially since the C6202 does not have an external interrupt output. Therefore, the logic has to be set up such that when you switch the LINT# logic around in the PLD from input-to-output, the circuitry doesn t generate any glitches. Also, the only way to generate an interrupt on the Local bus from the C6202 is to set a timer and let it generate an interrupt at certain intervals. This will have to be set such that it doesn t occur too frequently, but happens often enough. 2. The circuitry to switch the READY# line polarity is similar to the LINT# circuitry. This logic has to be set up to provide glitch-free operation when turning this circuitry around. Additionally, you have to be sure that the C6202 isn t performing hidden arbitration cycles to the PCI 9054, since this would make the PCI 9054 look like it owned the Local bus when in fact the C6202 does. In this case, data could be missed by either the PCI 9054 or the C A deadlock situation can occur if the C6202 wants access to the PCI bus, and a PCI Master wants access to the Local bus at the same time. In this case, the C6202 has an XBOFF signal, that when flagged, will suspend the current access on the Local bus and force the C6202 to release ownership. This signal is driven by the PCI 9054 s BREQo line when the PCI 9054 suspects a deadlock situation exists PLX Technology, Inc. All rights reserved. 5

7 4. REFERENCES The following is a list of additional documentation to provide the reader with further information about the TI C6202. PLX PCI 9054 Data Book PLX Technology, Inc. 390 Potrero Avenue Sunnyvale, CA USA Tel: , Fax: Texas Instruments TMS320C6200 Peripheral Reference Guide, SPRU190C Texas Instruments, Inc. P.O. Box , MS 8681 Dallas, TX Texas Instruments TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204 Fixed-Point Digital Signal Processor Datasheet Product Preview, SPRS104A Texas Instruments, Inc. P.O. Box 1443 Houston, TX PLX Technology, Inc. All rights reserved. 6 Doc. #: AN-PCI 9054/C

The PCI 9054 has Direct Master, DMA and Direct Slave Hitachi SH bit RISC Processor

The PCI 9054 has Direct Master, DMA and Direct Slave Hitachi SH bit RISC Processor PCI 9054/SH7709 AN July 2, 1999 SH7709 to PCI 9054 Version 1.0 Application Note Features General Description PLX Technology PCI 9054, PCI v2.2 compliant 32 bit, 33MHz PCI bus Master I/O Accelerator with