ECE 485/585 Microprocessor System Design

Transcription

1 Microprocessor System Design Lecture 16: PCI Bus Serial Buses Zeshan Chishti Electrical and Computer Engineering Dept. Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F.

2 PCI Bus Peripheral Component Interconnect Introduced by Intel (1992) Turned over to the PCI SIG Not specific to Intel microprocessors Most common contemporary PC bus but being replaced by PCI Express

3 Early PCI System Architecture

4 PCI Transactions Every transaction involves two agents * Initiator (bus master) Target (bus slave) A device can snoop without participating in a transaction Transactions: Three types (I/O, Memory, Configuration) Three phases One Arbitration phase One Address phase One or more Data phase(s) All transactions are essentially bursts (1/2/4 bytes/phase via BE s) * Except special cycles which are broadcast cycles

5 Simplified PCI Pin Out

6 PCI Commands

7 Read Transaction DEVSEL# must be asserted by Target within 1-3 cycles after address phase TRDY# must be asserted by target within 16 cycles of address phase

8 Read Transaction (cont d)

9 Write Transaction

10 Write Transaction (cont d)

11 PCI Arbitration Details of arbitration policy not specified Factors in priority and device latency times Hidden arbitration reduces latency Located in PC Chipset (e.g. Southbridge)

12 PCI Arbitration (cont d) Device a has bus (and continues to assert REQ#-a because it anticipates wanting to do further transactions) Device b requests bus by asserting REQ#-b Coincidentally device a is through with the first of its transactions

13 PCI Arbitration (cont d) Each device (capable of being a bus master) maintains a programmable latency counter. When a device is initiator it decrements the counter for each cycle after asserting FRAME#. If it loses its GNT# signal during the transfer and the counter has reached its limit then the device must de-assert FRAME# and yield the bus to another device. If the limit has not been reached the current bus master can continue until it has reached its limit During configuration each device capable of being a bus master reports its maximum permissible bus access grant delay (Max_Lat) and the minimum time it must have control over the bus (Min_Gnt). These are taken into account by the arbiter (in an unspecified manner)

14 Termination by Target Retry STOP# is asserted before target ever asserts TRDY# (before any data is transmitted). Typically because Target is unable to present data within the allotted time period (16 cycles) Results in delayed transaction Disconnect Typically used by slower devices The target terminates the transaction with the initiator but continues to process the request internally, storing the results in a buffer When the initiator retries the transaction the target provides the requested data from the buffer STOP# is asserted by the target during or after the first data phase. Master will repeat the transaction but with modified start address Target Abort STOP# is asserted simultaneously with deactivation of DEVSEL#. Typically an unrecoverable error

15 PCI Enumeration and Configuration Enumeration determines which devices and which functions are connected and gets their key characteristics including amount of address space they require Each PCI device has a set of registers referred to as configuration space. Device drivers have access to this space through the OS Each device (capable of being a master) reports its maximum permissible bus access grant delay (Max_Lat) and the minimum time it must have control over the bus (Min_Gnt). These are taken into account by the arbiter The BIOS or OS also sets the base address range the device will respond to

16 PCI Devices Device Enumeration Bus:Device:Function Buses numbered sequentially from 0 to 255 Each bus can have up to 32 devices Every device has Function 0 (1 7 are optional) Access to PCI Devices enabled by mapping them to: Memory space or I/O space Upon reset, OS (or BIOS) programs the mapped addresses into BARs (base address registers)

17 PCI Bus Parking Arbiter can park the bus on a device when the bus is idle (no other devices are requesting the bus) Device s GNT# is asserted (even though device has not asserted its REQ# signal) The parked device can gain ownership of the bus immediately without arbitrating (saves a cycle of delay) The bus is usually parked on the last device to be an initiator Bus Parking improves throughput by eliminating unnecessary arbitration cycles

18 PCI-X Bus Enhancements Problem: Delayed transactions consume bus bandwidth Retry signaling Repeated retry requests by initiator w/o knowing if target is ready to return the data Solution: Split Transactions If Target will take >16 cycles to complete request it can signal a Split Transaction instead of terminating the transaction To do this the initiator (requestor) must provide additional information: Requester ID (Bus:Device:Function) A Transaction Number (Tag) Target (completer) initiates its own completion transaction when it has the data ready Uses Sequence ID as the Address Sequence ID

19 PCI-X Bus Enhancements (cont d) Problem: PCI transactions were indeterminate length bursts of DWORDS (32-bit) PCI X transaction are determinant length Byte count sent as part of the request Problem: In PCI both the Initiator and the Target could insert wait states PCI-X prohibits Initiators from inserting wait states PCI-X Targets can only insert wait states prior to first data item Problem: PCI error detection limited to parity on some of the signals (AD and C/BE#) PCI-X implements single-bit correction, multi-bit detection

20 PCI-X and PCI Compatibility PCI-X transactions have 4-phases instead of 2 Address Phase Attribute Phase Response Phase Data Phase But they use the same connector Only one pin (B38) definition changes (GND -> PCIXCAP) If a PCI-X device detects PCI devices on the same bus Drops speed to match least capable device Drops back to PCI signaling Achieves both forward and backwards compatibility wow! But dropping back is a heavy penalty so enter PCI Bridges Increase number of devices that can be connected Divides PCI devices into segments so devices with similar capabilities (PCI-X vs. PCI) and speed (133MHz vs. 66MHz) are on the same segment Balances bandwidth requirements

21 Bus Trends Parallel to Serial Lower Voltage Can t accomplish large voltage swings at high speed Power consumption Differential Signaling Clock Forwarding and Clock Embedding Encoding Line codes: 8b/10b

22 Why Serial? Parallel Serial + - Device A Device B Device A + - Device B 10 bidirectional wires at 250Mbps pair unidirectional wires at 2500Mbps (2.5Gbps)

23 Traditional Parallel Bus Device A Device B Used in low to medium 100 MHz range Issues Board trace length mismatch effects skew at a device Clock skew across devices Faster data rate squeezes eye t SU CLK t H EYE

24 Source Synchronous Bus Device A Device B Used in 200MHz to 1.6GHz range Clock signal is forwarded with data Design impact: Board layout track length mismatch still adds to skew Eliminates skew error term caused by clock domain skew Allows faster cycle times than parallel

25 Source Synchronous - Clock Forward Clock Data 1 Data 2 Data 3 Data 4 Clock is transmitted continuously from Tx to Rx Removes clock distribution skew Examples HyperTransport Parallel RapidIO

26 Embedded Clock Data Clock Clock signal is embedded with data Edge density guaranteed by encoding scheme Examples Edge density?...well, you have to have enough transitions to recover the clock PCI Express USB Serial RapidIO Infiniband Clock signal embedded with data

27 SerDes (Serial/Deserializer) Serialize Tx 10 x 250Mbps Low Speed Parallel Data 1 x 2.5Gbps High Speed Serial Data Deserialize Rx

28 SerDes - Parallel and Serial Conversion 10-bit Parallel Interface Serializer TxP TxN SysClk XmitClk Rx Parallel Interface 10-bit Clock Recovery and Data Deserializer RxP RxN Recovered Clock

29 Differential Signaling Differential, point to point Complementary signals transmitted Receiver detects voltage difference between lines Low amplitudes (200mV - 400mV typical), high speeds Good noise immunity Pair routed together noise cancels out EX: LVDS Low Voltage Differential Signaling Gbps, +/- 350mV Gbps at mws -- High speed & low power consumption FibreChannel, Gigabit Ethernet, HDMI, DVI

30 Clock Recovery for Embedded Clock Data Clock Problem: When clock signal is embedded with data, need enough transitions to recover the clock from the data (high edge density) Solution: Line codes Use codes which ensure that there are always enough transitions (0->1 and 1->0) in short amount of time, so that the clock signal can be easily recovered from the embedded clock/data signal Other advantage: avoid DC bias Clock signal embedded with data

31 Ensuring Edge Density: m-of-n codes Some 8-bit code words have too few 1s (or 0s) to ensure edge density sufficient to recover clock 8b10 encoding (developed by IBM in 1983) Use a subset of 10-bit code words having a balanced number of 0s and 1s Benefits Ensure edge density Avoid DC bias at receiver from imbalance 8 bit byte 10 bit code Table lookup Device A Device B Parallel Data TX FIFO 8B/10B Encoder Serializer + _ Deserializer 8B/10B Decoder RX FIFO Parallel Data Parallel Data RX FIFO 8B/10B Decoder Deserializer + _ Serializer 8B/10B Encoder TX FIFO Parallel Data

32 8b/10b Transmission Code Name 8-bit binary 10-bit Encode D D D D Reasons for using 8B/10B encoding/decoding Guarantees transition density to ensure correct PLL operation Error correction to detect signaling errors Ensures signal is DC balanced no DC offset develops over time Support of special characters that can be used as delimiters for control, such as sync or framing, or other generalized commands