PART MAX3397EELA+ Maxim Integrated Products 1

Transcription

1 19-771; Rev ; 4/7 EVALUATION KIT AVAILABLE General Description The ±15kV ESD-protected bidirectional level tralator provides level shifting for data trafer in a multivoltage system. Externally applied voltages, and, set the logic levels on either side of the device. A logic-low signal present on the side of the device appears as a logic-low signal on the side of the device, and vice versa. The utilizes a tramission-gate-based design to allow data tralation in either direction ( ) on any single data line. The accepts from +1.2V to +5.5V and from +1.65V to +5.5V, making the device ideal for data trafer between low-voltage ASICs/PLDs and higher voltage systems. The features a shutdown mode that reduces supply current to less than 1µA, thermal short-circuit protection, and ±15kV ESD protection on the side for greater protection in applicatio that route signals externally. The operates at a guaranteed data rate of 8Mbps over the entire specified operating voltage range. Within specific voltage domai, higher data rates are possible. See the Timing Characteristics table. The is available in an 8-pin µdfn package and specified over the extended -4 C to +85 C operating temperature range. Applicatio Cell Phones, MP3 Players Telecommunicatio Equipment SPI, MICROWIRE, and I 2 C Level Tralation Portable POS Systems, Smart Card Readers Low-Cost Serial Interfaces, GPS Features Bidirectional Level Tralation Guaranteed Data Rate 8Mbps (+1.2V +5.5V) 16Mbps (+1.8V +3.3V) Extended ESD Protection on the I/O Lines ±15kV Human Body Model ±15kV Air-Gap Discharge per IEC ±8kV Contact Discharge per IEC Enable/Shutdown Ultra-Low 1µA Supply Current in Shutdown Mode 8-Pin µdfn Package PART ELA+ TEMP RANGE -4 C to +85 C +Denotes a lead-free package. Ordering Information PIN- PACKAGE 8 µdfn (2mm x 2mm) TOP MARK PKG CODE ABU L822-1 Pin Configuration SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Typical Application Circuit appears at end of data sheet. + I/O VCC I/O VCC2 VCC GND 6 5 VL μdfn (2mm x 2mm) I/O VL2 I/O VL1 4 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.),...-.3V to +6V I/O _...-.3V to ( +.3V) I/O _...-.3V to ( +.3V)...-.3V to +6V Short-Circuit Duration I/O _, I/O _ to GND...Continuous Continuous Power Dissipation (T A = +7 C) 8-Pin µdfn (derate 4.8mW/ C above +7 C) mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( = +1.65V to +5.5V, = +1.2V to 5.5V, I/O _, and I/O _ are unconnected, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = +3.3V, = +1.8V, T A = +25 C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Supply Range V Supply Range V Supply Current from I QVCC 13 3 µa Supply Current from I QVL 1 1 µa Shutdown-Mode Supply Current Shutdown-Mode Supply Current I/O _ and I/O _ Shutdown- Mode Leakage Current I SHUTDOWN-VCC T A = +25 C, = GND.3 1 µa I SHUTDOWN-VL T A = +25 C, = GND.3 1 µa I SHUTDOWN-LKG T A = +25 C, = GND.2 1 µa Input Leakage T A = +25 C.2 1 µa Tri-State Threshold Low V TH_L falling (Note 3) 1.5 V Tri-State Threshold High V TH_H rising (Note 3) 1 V ESD PROTECTION I/O Human Body Model (Note 4) ±15 kv LOGIC-LEVEL THRESHOLDS I/O _ Input-Voltage High V IHL -.2 I/O _ Input-Voltage Low V ILL.15 V I/O _ Input-Voltage High V IHC -.4 I/O _ Input-Voltage Low V ILC.15 V I/O _ Output-Voltage High V OHL I/O _ source current = 2µA, I/O _ > -.4V I/O _ Output-Voltage Low V OLL I/O _ sink current = 1mA, I/O _ <.15V.67 x V V V.4 V 2

3 ELECTRICAL CHARACTERISTICS (continued) ( = +1.65V to +5.5V, = +1.2V to 5.5V, I/O _, and I/O _ are unconnected, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = +3.3V, = +1.8V, T A = +25 C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I/O _ Output-Voltage High V OHC I/O _ source current = 2µA, I/O _ > -.2V I/O _ Output-Voltage Low V OLC I/O _ sink current = 1mA, I/O _ <.15V.67 x Input-Voltage High V IH- -.2 V.4 V Input-Voltage Low V IL-.15 V RISE/FALL-TIME ACCELERATOR STAGE Traition-Detect Threshold I/O side.8 I/O side.8 Accelerator Pulse Duration = 1.2V, = 1.65V 27 I/O _ Output-Accelerator = 1.2V, = 1.65V 4 Source Impedance = 5V, = 5V 9 I/O _ Output-Accelerator = 1.2V, = 1.65V 3 Source Impedance = 5V, = 5V 12 V V Ω Ω TIMING CHARACTERISTICS ( = +1.65V to +5.5V, = +1.2V to +5.5V, R LOAD = 1MΩ, C LOAD = 15pF, driver output impedance 5Ω, I/O test signal of Figure 1, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = +3.3V, = +1.8V, T A = +25 C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +1.2V +5.5V Push-pull driving (Figure 1a) 7 25 I/O _ Rise Time t RVCC Open-drain driving (Figure 1c) 17 4 Push-pull driving (Figure 1a) 6 37 I/O _ Fall Time t FVCC Open-drain driving (Figure 1c) 6 37 Push-pull driving (Figure 1b) 8 3 I/O _ Rise Time t RVL Open-drain driving (Figure 1d) 18 4 Push-pull driving (Figure 1b) 3 3 I/O _ Fall Time t FVL Open-drain driving (Figure 1d) 3 3 Propagation Delay Push-pull driving (Figure 1a) 5 3 t PD-VL-VCC Driving I/O _ Open-drain driving (Figure 1c) 17 8 Push-pull driving (Figure 1b) 4 3 t PD-VCC-VL Driving I/O _ Open-drain driving (Figure 1d) 19 Each tralator Push-pull driving 2 Channel-to-Channel Skew t SKEW equally loaded Open-drain driving 5 Maximum Data Rate Push-pull driving 8 Mbps Open-drain driving 5 kbps 3

4 TIMING CHARACTERISTICS (continued) ( = +1.65V to +5.5V, = +1.2V to +5.5V, R LOAD = 1MΩ, C LOAD = 15pF, driver output impedance 5Ω, I/O test signal of Figure 1, T A = T MIN to T MAX, unless otherwise noted. Typical values are at = +3.3V, = +1.8V, T A = +25 C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +1.8V +3.3V I/O _ Rise Time t RVCC Figure 1a (Note 5) 15 I/O _ Fall Time t FVCC Figure 1a (Note 6) 15 I/O _ Rise Time t RVL Figure 1b (Note 5) 15 I/O _ Fall Time t FVL Figure 1b (Note 6) 15 Propagation Delay t PD-VL-VCC Driving I/O _ 15 t PD-VCC-VL Driving I/O _ 15 Channel-to-Channel Skew t SKEW Each tralator equally loaded 1 Maximum Data Rate 16 Mbps Note 1: All units are % production tested at T A = +25 C. Limits over the operating temperature range are guaranteed by design and not production tested. Note 2: For normal operation, eure VL < ( +.3V). Note 3: When is below by more than the tri-state threshold, the device tur off its pullup resistors and I/O_ enters tri-state. The device is not in shutdown. Note 4: To eure maximum ESD protection, place a 1µF capacitor between and GND. See the Typical Application Circuit. Note 5: 1% of input to 9% of output. Note 6: 9% of input to 1% of output. Typical Operating Characteristics ( = +3.3V, = +1.8V, R LOAD = 1MΩ, C LOAD = 15pF, T A = +25 C, data rate = 8Mbps, unless otherwise noted.) VL SUPPLY CURRT (μa) SUPPLY CURRT vs. SUPPLY VOLTAGE (DRIVING ONE I/O _ ) SUPPLY VOLTAGE (V) toc1 VL SUPPLY CURRT (μa) SUPPLY CURRT vs. SUPPLY VOLTAGE (DRIVING ONE I/O _ ) SUPPLY VOLTAGE (V) toc2 VCC SUPPLY CURRT (μa) SUPPLY CURRT vs. SUPPLY VOLTAGE (DRIVING ONE I/O _ ) SUPPLY VOLTAGE (V) toc3 4

5 Typical Operating Characteristics (continued) ( = +3.3V, = +1.8V, R LOAD = 1MΩ, C LOAD = 15pF, T A = +25 C, data rate = 8Mbps, unless otherwise noted.) VCC SUPPLY CURRT (μa) SUPPLY CURRT vs. SUPPLY VOLTAGE (DRIVING ONE I/O _ ) SUPPLY VOLTAGE (V) toc4 VL SUPPLY CURRT (μa) SUPPLY CURRT vs. TEMPERATURE (DRIVING ONE I/O _ ) TEMPERATURE ( C) toc5 VL SUPPLY CURRT (μa) SUPPLY CURRT vs. TEMPERATURE (DRIVING ONE I/O _ ) TEMPERATURE ( C) toc6 VL SUPPLY CURRT (μa) SUPPLY CURRT vs. CAPACITIVE LOAD (DRIVING ONE I/O _ ) toc7 VCC SUPPLY CURRT (μa) SUPPLY CURRT vs. CAPACITIVE LOAD (DRIVING ONE I/O _ ) toc8 RISE/FALL TIME () RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING ONE I/O _ ) t FVCC t RVCC toc CAPACITIVE LOAD (pf) CAPACITIVE LOAD (pf) CAPACITIVE LOAD (pf) PROPAGATION DELAY () PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING ONE I/O _ ) toc1 RISE/FALL TIME () RISE/FALL TIME vs. CAPACITIVE LOAD (DRIVING ONE I/O _ ) t RVL t FVL toc11 PROPAGATION DELAY () PROPAGATION DELAY vs. CAPACITIVE LOAD (DRIVING ONE I/O _ ) toc CAPACITIVE LOAD (pf) CAPACITIVE LOAD (pf) CAPACITIVE LOAD (pf) 5

6 Typical Operating Characteristics (continued) ( = +3.3V, = +1.8V, R LOAD = 1MΩ, C LOAD = 15pF, T A = +25 C, data rate = 8Mbps, unless otherwise noted.) I/O _ RAIL-TO-RAIL DRIVING (DRIVING ONE I/O _ ) toc13 1V/div I/O _ I/O _ EXITING SHUTDOWN MODE toc14 1V/div 2V/div I/O _ 1V/div 1V/div 2/div 2μs/div PIN NAME FUNCTION 1 I/O 2 Input/Output 2. Referenced to. 2 GND Ground Pin Description Logic-Input Voltage. The supply voltage range is +1.2V +5.5V. Bypass this supply with a.1µf capacitor 3 located as close as possible to the input. 4 I/O 2 Input/Output 2. Referenced to. 5 I/O 1 Input/Output 1. Referenced to. 6 Enable Input. Drive high to enable the device. Drive low to put the device in shutdown mode. Input Voltage. The supply voltage range is +1.65V +5.5V. Bypass this supply with a.1µf capacitor 7 located as close as possible to the input. A 1µF ceramic capacitor is recommended for full ESD protection. 8 I/O 1 Input/Output 1. Referenced to. Detailed Description The bidirectional, ESD-protected level tralator provides the level shifting necessary to allow data trafer in a multivoltage system. Externally applied voltages, and, set the logic levels on either side of the device. A logic-low signal present on the side of the device appears as a logic-low signal on the side of the device, and vice versa. The device uses a tramission-gate-based design (see the Functional Diagram) to allow data tralation in either direction ( ) on any single data line. The accepts from +1.2V to +5.5V and from +1.65V to +5.5V, making the device ideal for data trafer between low-voltage ASICs/PLDs and higher voltage systems. The features a shutdown mode that reduces the supply current to less than 1µA, thermal short-circuit protection, and ±15kV ESD protection on the side for greater protection in applicatio that route signals externally. The device operates at a guaranteed data rate of 8Mbps over the entire specified operating voltage range. Within specific voltage domai, higher data rates are possible. See the Timing Characteristics table. 6

7 I/O _ I/O _ GND DATA R LOAD C LOAD C LOAD R LOAD DATA I/O _ I/O _ GND I/O _ (t RISE, t FALL < 1) I/O _ (t RISE, t FALL < 1) t PD-VL-VCC tpd-vl-vcc t PD-VCC-VL tpd-vcc-vl I/O _ I/O _ t RVCC t FVCC t RVL t FVL Figure 1a. Rail-to-Rail Driving I/O Figure 1b. Rail-to-Rail Driving I/O Level Tralation For proper operation, eure that +1.65V +5.5V and +1.2V +5.5V. During power-up sequencing, ( +.3V) does not damage the device. The speed-up circuitry limits the maximum data rate for the to 16Mbps. The maximum data rate also depends heavily on the load capacitance (see the Typical Operating Characteristics), output impedance of the driver, and the operational voltage range (see the Timing Characteristics table). Rise-Time Accelerators The has an internal rise-time accelerator, allowing operation up to 16Mbps. The rise-time accelerators are present on both sides of the device and act to speed up the rise time of the input and output of the device, regardless of the direction of the data. The triggering mechanism for these accelerators is both level and edge seitive. To prevent false triggering of the rise-time accelerators, signal fall times of less than 2/V are recommended for both the inputs and outputs of the device. Under less noisy conditio, longer signal fall times are acceptable. Note: To guarantee operation of the rise time, accelerators the maximum parasitic capacitance should be less than pf on the I/O lines. Shutdown Mode Drive low to place the in shutdown mode. Connect to or (logic-high) for normal operation. Activating the shutdown mode disconnects the internal 1kΩ pullup resistors on the I/O and I/O lines. This forces the I/O lines to a high-impedance state, and decreases the supply current to less than 1µA. The high-impedance I/O lines in shutdown mode allow for use in a multidrop network. The effectively has a diode from each I/O to the corresponding supply rail and GND. Therefore, when in shutdown mode, do not allow the voltage at I/O _ to exceed ( +.3V), or the voltage at I/O _ to exceed ( +.3V). 7

8 I/O _ I/O _ GND DATA R LOAD C LOAD C LOAD R LOAD DATA I/O _ I/O _ GND I/O _ I/O _ t PD-VL-VCC t PD-VL-VCC t PD-VCC-VL t PD-VCC-VL I/O _ I/O _ t RVCC t FVCC t RVL t FVL Figure 1c. Open-Drain Driving I/O Figure 1d. Open-Drain Driving I/O Operation with One Supply Disconnected Certain applicatio require sectio of circuitry to be disconnected to save power. When is connected and is disconnected or connected to ground, the device enters shutdown mode. In this mode, I/O can still be driven without damage to the device; however, data does not tralate from I/O to I/O. If falls more than.8v (typ) below, the device disconnects the pullup resistors at I/O and I/O. To achieve the lowest possible supply current from when is disconnected, it is recommended that the voltage at the supply input be approximately equal to GND. Note: When is disconnected or connected to ground, I/O must not be driven more than +.3V. When is connected and is less than.7v (typ), the device enters shutdown mode. In this mode, I/O can still be driven without damage to the device; however, data does not tralate from I/O to I/O. Note: When is disconnected or connected to ground, I/O must not be driven more than +.3V. Thermal Short-Circuit Protection Thermal-overload detection protects the from short-circuit fault conditio. In the event of a short-circuit fault, when the junction temperature (T J ) reaches +15 C, a thermal seor signals the shutdown mode logic to force the device into shutdown mode. When the T J has cooled to +14 C, normal operation resumes. ±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pi to protect agait electrostatic discharges encountered during handling and assembly. The I/O lines have extra protection agait static electricity. Maxim s engineers have developed state-of-the-art structures to protect these pi agait ESD of ±15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown mode, and powered down. After an ESD event, Maxim s E versio keep working without 8

9 PU1 ONE-SHOT BLOCK TRIGGER ONE-SHOT BLOCK Functional Diagram PU2 GATE BIAS I/O _ N I/O _ GND latchup, whereas competing products can latch and must be powered down to remove latchup. ESD protection can be tested in various ways. The I/O lines of the are characterized for protection to the following limits: R C 1MΩ CHARGE-CURRT- LIMIT RESISTOR R D 15Ω DISCHARGE RESISTANCE 1) ±15kV using the Human Body Model 2) ± 8kV using the Contact Discharge method specified by IEC HIGH- VOLTAGE DC SOURCE Cs pf STORAGE CAPACITOR DEVICE UNDER TEST 3) ±15kV using the Air-Gap Discharge method specified by IEC ESD Test Conditio ESD performance depends on a variety of conditio. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 2a shows the Human Body Model, and Figure 2b shows the current waveform it generates when discharged into a low-impedance state. This model coists of a pf capacitor charged to the ESD voltage of interest that is then discharged into the test device through a 1.5kΩ resistor. IEC The IEC standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The helps Figure 2a. Human Body ESD Test Model AMPERES I P % 9% 36.8% 1% t RL Ir TIME t DL CURRT WAVEFORM Figure 2b. Human Body Current Waveform PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) 9

10 to design equipment that meets Level 4 of IEC without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC is higher peak current in IEC because series resistance is lower in the IEC model. Hence, the ESD withstand voltage measured to IEC is generally lower than that measured using the Human Body Model. Figure 3a shows the IEC model, and Figure 3b shows the current waveform for the ±8kV, IEC 6-4-2, Level 4, ESD contact-discharge test. The Air-Gap test involves approaching the device with a charged probe. The contact-discharge method connects the probe to the device before the probe is energized. HIGH- VOLTAGE DC SOURCE R C 5MΩ to MΩ CHARGE-CURRT- LIMIT RESISTOR Cs 15pF R D 33Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Machine Model The Machine Model for ESD tests all pi using a pf storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. Of course, all pi require this protection during manufacturing, not just inputs and outputs. Therefore, after PCB assembly, the Machine Model is less relevant to I/O ports. Applicatio Information Power-Supply Decoupling To reduce ripple and the chance of tramitting incorrect data, bypass and to ground with a.1µf capacitor (see the Typical Application Circuit). To eure full ±15kV ESD protection, bypass to ground with a 1µF capacitor. Place all capacitors as close as possible to the power-supply inputs. I 2 C Level Tralation The level-shifts the data present on the I/O lines between +1.2V and +5.5V, making them ideal for level tralation between a low-voltage ASIC and an I 2 C device. A typical application involves interfacing a low-voltage microprocessor to a 3V or 5V D/A converter, such as the MAX517. Figure 3a. IEC ESD Test Model I Push-Pull vs. Open-Drain Driving The can be driven in a push-pull configuration and include internal 1kΩ resistors that pull up I/O _ and I/O _ to their respective power supplies, allowing operation of the I/O lines with open-drain devices. See the Timing Characteristics table for maximum data rates when using open-drain drivers. % 9% PROCESS: BiCMOS Chip Information IPEAK 1% tr =.7 to 1 3 t 6 Figure 3b. IEC ESD Generator Current Waveform 1

11 +1.8V.1μF +1.8V SYSTEM CONTROLLER Typical Application Circuit +3.3V SYSTEM.1μF 1μF +3.3V I/O 1 I/O 1 DATA I/O 2 I/O 2 DATA 11

12 Package Information (The package drawing(s) in this data sheet may not reflect the most current specificatio. For the latest package outline information, go to D XXXX XXXX XXXX E A e b N SOLDER MASK COVERAGE PIN 1.1x45 6, 8, 1L UDFN.EPS L L1 PIN 1 INDEX AREA SAMPLE MARKING 7 A A (N/2-1) x e) 1 C L C L A b L L A2 e e A1 EV TERMINAL ODD TERMINAL PACKAGE OUTLINE, 6, 8, 1L udfn, 2x2x.8 mm -DRAWING NOT TO SCALE A

13 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specificatio. For the latest package outline information, go to COMMON DIMSIONS SYMBOL MIN. NOM. MAX. A A A D E L L1.1 REF. PACKAGE VARIATIONS PKG. CODE N e b L BSC.3±.5 L822-1 L BSC.4 BSC.25±.5.2±.3 (N/2-1) x e 1.3 REF. 1.5 REF. 1.6 REF. PACKAGE OUTLINE, 6, 8, 1L udfn, 2x2x.8 mm -DRAWING NOT TO SCALE A 2 2 Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. Springer