Low Voltage 1.15 V to 5.5 V, Single-Channel Bidirectional Logic Level Translator ADG3301

Transcription

1 Low Voltage.5 V to 5.5 V, Single-Channel Bidirectional Logic Level Translator DG33 FETURES Bidirectional level translation Operates from.5 V to 5.5 V Low quiescent current < 5 µ No direction pin FUNCTIONL BLOCK DIGRM PPLICTIONS SPI, MICROWIRE level translation Low voltage SIC level translation Smart card readers Cell phones and cell phone cradles Portable communication devices Telecommunications equipment Network switches and routers Storage systems (SN/NS) Computing/server applications GPS Portable POS systems Low cost serial interfaces Figure. DG GERL DESCRIPTION The DG33 is a single-channel, bidirectional logic level translator. It can be used in multivoltage digital system applications such as data transfer between a low voltage DSP/controller and a higher voltage device. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. PRODUCT HIGHLIGHTS. Bidirectional level translation.. Fully guaranteed over the.5 V to 5.5 V supply range. 3. No direction pin.. Compact -lead SC7 package. The voltage applied to VCC sets the logic levels on the side of the device, while VCC sets the levels on the side. For proper operation, VCC must always be less than VCC. The VCCcompatible logic signals applied to the pin appear as VCCcompatible levels on the pin. Similarly, VCC-compatible logic levels applied to the pin appear as VCC-compatible logic levels on the pin. The enable pin () provides three-state operation on both the pin and the pin. When the device enable pin is pulled low, the terminals on both sides of the device are in the high impedance state. The pin is referred to the VCC supply voltage and driven high for normal operation. The DG33 is available in a compact -lead SC7 package and is guaranteed to operate over the.5 V to 5.5 V supply voltage range and extended C to +85 C temperature range. Rev. Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, M -9, U.S.. Tel: Fax: nalog Devices, Inc. ll rights reserved.

2 DG33 TBLE OF CONTTS Features... pplications... Functional Block Diagram... General Description... Product Highlights... Specifications... 3 bsolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics... 8 Test Circuits... Theory of Operation... Level Translator rchitecture... Input Driving Requirements... Output Load Requirements... Enable Operation... Power Supplies... Data Rate... 7 pplications... 8 Layout Guidelines... 8 Outline Dimensions... 9 Ordering Guide... 9 Terminology... 5 REVISION HISTOR /5 Revision : Initial Version Rev. Page of

3 SPECIFICTIONS VCC =.5 V to 5.5 V, VCC =.5 V to VCC, = V. ll specifications TMIN to TMX, unless otherwise noted. DG33 Table. Parameter Symbol Conditions Min Typ Max Unit LOGIC INPUTS/OUTPUTS Side Input High Voltage 3 VIH VCC =.5 V VCC.3 V VIH VCC =. V to 5.5 V.5 VCC Input Low Voltage 3 VIL.35 VCC V Output High Voltage VOH V = VCC, IOH = µ, see Figure 7 VCC. V Output Low Voltage VOL V = V, IOL = µ, see Figure 7. V Capacitance 3 C f = MHz, =, see Figure 3 9 pf Leakage Current IL, HiZ V = V/VCC, =, see Figure 9 ± µ Side Input High Voltage 3 VIH.5 VCC V Input Low Voltage 3 VIL.35 VCC V Output High Voltage VOH V = VCC, IOH = µ, see Figure 8 VCC. V Output Low Voltage VOL V = V, IOL = µ, see Figure 8. V Capacitance 3 C f = MHz, =, see Figure 33 pf Leakage Current IL, HiZ V = V/VCC, =, see Figure 3 ± µ Enable () Input High Voltage 3 VIH VCC =.5 V VCC.3 V VIH VCC =. V to 5.5 V.5 VCC V Input Low Voltage 3 VIL.35 VCC V Leakage Current IL V = V/VCC, V = V, see Figure 3 ± µ Capacitance 3 C 3 pf Enable Time 3 t RS = RT = 5 Ω, V = V/VCC ( ), V = V/VCC ( ), see Figure 3.8 µs SWITCHING CHRCTERISTICS V ±.3 V VCC VCC, VCC = 5 V ±.5 V Level Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 35 Propagation Delay tp, ns Rise Time tr, 3.5 ns Fall Time tf, 3.5 ns Maximum Data Rate DMX, 5 Mbps Part-to-Part Skew tppskew, 3 ns Level Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, 7 ns Rise Time tr, 3 ns Fall Time tf, 3 7 ns Maximum Data Rate DMX, 5 Mbps Part-to-Part Skew tppskew, ns.8 V ±.5 V VCC VCC, VCC = 3.3 V ±.3 V Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 35 Propagation Delay tp, 8 ns Rise Time tr, 5 ns Fall Time tf, 5 ns Maximum Data Rate DMX, 5 Mbps Part-to-Part Skew tppskew, ns Rev. Page 3 of

4 DG33 Parameter Symbol Conditions Min Typ Max Unit Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, 5 8 ns Rise Time tr, 3.5 ns Fall Time tf, 3.5 ns Maximum Data Rate DMX, 5 Mbps Part-to-Part Skew tppskew, 3 ns.5 V to.3 V VCC VCC, VCC = 3.3 V ±.3 V Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 35 Propagation Delay tp, 9 8 ns Rise Time tr, 3 5 ns Fall Time tf, 5 ns Maximum Data Rate DMX, Mbps Part-to-Part Skew tppskew, ns Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, 5 9 ns Rise Time tr, ns Fall Time tf, ns Maximum Data Rate DMX, Mbps Part-to-Part Skew tppskew, ns.5 V to.3 V VCC VCC, VCC =.8 V ±.3 V Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 35 Propagation Delay tp, 5 ns Rise Time tr, 7 ns Fall Time tf, 3 5 ns Maximum Data Rate DMX, 5 Mbps Part-to-Part Skew tppskew, 5 ns Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, 35 ns Rise Time tr, 5 ns Fall Time tf,.5.5 ns Maximum Data Rate DMX, 5 Mbps Part-to-Part Skew tppskew, 3.5 ns.5 V ±. V VCC VCC, VCC = 3.3 V ±.3 V Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 35 Propagation Delay tp, 7 ns Rise Time tr,.5 ns Fall Time tf, 5 ns Maximum Data Rate DMX, Mbps Part-to-Part Skew tppskew, ns Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, 5 8 ns Rise Time tr, ns Fall Time tf, 3 5 ns Maximum Data Rate DMX, Mbps Part-to-Part Skew tppskew, 3 ns Rev. Page of

5 DG33 Parameter Symbol Conditions Min Typ Max Unit POWER REQUIREMTS Power Supply Voltages VCC VCC VCC V VCC V Quiescent Power Supply Current ICC V = V/VCC, V = V/VCC,.7 5 µ VCC = VCC = 5.5 V, = ICC V = V/VCC, V = V/VCC,.7 5 µ VCC = VCC = 5.5 V, = Three-State Mode Power Supply Current IHiZ VCC = VCC = 5.5 V, =. 5 µ IHiZ VCC = VCC = 5.5 V, =. 5 µ Temperature range for the B version is C to +85 C. ll typical values are at T = 5 C, unless otherwise noted. 3 Guaranteed by design, not subject to production test. Rev. Page 5 of

6 DG33 BSOLUTE MXIMUM RTINGS T = 5 C, unless otherwise noted. Table. Parameter Rating VCC to.3 V to +7 V VCC to VCC to +7 V Digital Inputs ().3 V to VCC +.3 V Digital Inputs ().3 V to VCC +.3 V to.3 V to +7 V Operating Temperature Range Industrial (B Version) C to +85 C Storage Temperature Range 5 C to +5 C Junction Temperature 5 C θj Thermal Impedance (-Layer Board) -Lead SC7 9. C/W Lead Temperature, Soldering ( sec) 3 C IR Reflow, Peak Temperature (< sec) (+/ 5) C Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. lthough this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. Page of

7 DG33 PIN CONFIGURTION ND FUNCTION DESCRIPTIONS 3 DG33 TOP VIEW (Not to Scale) Figure. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description VCC Power Supply Voltage Input for the I/O Pin (.5 V VCC VCC). Input/Output. Referenced to VCC. 3 Ground ( V). ctive High Enable Input. 5 Input/Output. Referenced to VCC. VCC Power Supply Voltage Input for the I/O Pin (.5 V VCC 5.5V). Rev. Page 7 of

8 DG33 TPICL PERFORMNCE CHRCTERISTICS I CC (m) C L = 5pF = 3.3V, = 5V =.8V, = 3.3V I CC (m) C L = 5pF = 3.3V, = 5V.. =.V, =.8V DT RTE (Mbps) =.V, =.8V DT RTE (Mbps) =.8V, = 3.3V 557- Figure 3. ICC vs. Data Rate ( Level Translation) Figure. ICC vs. Data Rate ( Level Translation) I CC (m) C L = 5pF = 3.3V, = 5V =.8V, = 3.3V =.V, =.8V I CC (m) T =5 C =.V =.8V Mbps Mbps 5Mbps Mbps DT RTE (Mbps) Figure. ICC vs. Data Rate ( Level Translation) Figure 7. ICC vs. Capacitive Load at Pin for (. V.8 V) Level Translation C L = 5pF = 3.3V, = 5V =.V =.8V I CC (m) DT RTE (Mbps) =.8V, = 3.3V =.V, =.8V I CC (m) Mbps Mbps 5Mbps Mbps Figure 5. ICC vs. Data Rate ( Level Translation) Figure 8. ICC vs. Capacitive Load at Pin for (.8 V. V) Level Translation Rev. Page 8 of

9 DG =.8V = 3.3V 5Mbps 7 5 = 3.3V = 5V 5Mbps I CC (m) 5 3 5Mbps Mbps Mbps Mbps I CC (m) 3 5Mbps Mbps Mbps Mbps 557- Figure 9. ICC vs. Capacitive Load at Pin for (.8 V 3.3 V) Level Translation Figure. ICC vs. Capacitive Load at Pin for (5 V 3.3 V) Level Translation =.8V = 3.3V 9 8 DT RTE = 5kbps =.V, =.8V I CC (m) Mbps 3Mbps RISE TIME (ns) 5 =.8V, = 3.3V.5..5 Mbps Mbps 3 = 3.3V, = 5V 5Mbps Figure. ICC vs. Capacitive Load at Pin for (3.3 V.8 V) Level Translation Figure 3. Rise Time vs. Capacitive Load at Pin ( Level Translation) = 3.3V = 5V 5Mbps DT RTE = 5kbps =.V, =.8V I CC (m) 8 3Mbps Mbps Mbps FLL TIME (ns) =.8V, = 3.3V = 3.3V, = 5V 5Mbps Figure. ICC vs. Capacitive Load at Pin for (3.3 V 5 V) Level Translation Figure. Fall Time vs. Capacitive Load at Pin ( Level Translation) Rev. Page 9 of

10 DG DT RTE = 5kbps DT RTE = 5kbps =.V, =.8V RISE TIME (ns) =.V, =.8V =.8V, = 3.3V = 3.3V, = 5V PROPGTION DEL (ns) 8 =.8V, = 3.3V = 3.3V, = 5V Figure 5. Rise Time vs. Capacitive Load at Pin ( Level Translation) Figure 8. Propagation Delay (tphl) vs. Capacitive Load at Pin ( Level Translation). 3.5 DT RTE = 5kbps 9 8 DT RTE = 5kbps FLL TIME (ns) =.V, =.8V =.8V, = 3.3V = 3.3V, = 5V PROPGTION DEL (ns) =.8V, = 3.3V =.V, =.8V.5 = 3.3V, = 5V Figure. Fall Time vs. Capacitive Load at Pin ( Level Translation) Figure 9. Propagation Delay (tplh) vs. Capacitive Load at Pin ( Level Translation) PROPGTION DEL (ns) 8 DT RTE = 5kbps =.8V, = 3.3V =.V, =.8V = 3.3V, = 5V PROPGTION DEL (ns) DT RTE = 5kbps =.8V, = 3.3V =.V, =.8V = 3.3V, = 5V Figure 7. Propagation Delay (tplh) vs. Capacitive Load at Pin ( Level Translation) Figure. Propagation Delay (tphl) vs. Capacitive Load at Pin ( Level Translation) Rev. Page of

11 DG33 DT RTE = 5Mbps C L = 5pF DT RTE = 5Mbps C L = 5pF mv/div 5ns/DIV 557- mv/div 3ns/DIV 557- Figure. Eye Diagram at Output (. V to.8 V Level Translation, 5 Mbps) Figure. Eye Diagram at Output (3.3 V to.8 V Level Translation, 5 Mbps) DT RTE = 5Mbps C L = 5pF DT RTE = 5Mbps CL = 5pF mv/div 5ns/DIV 557- V/DIV 3ns/DIV Figure. Eye Diagram at Output (.8 V to. V Level Translation, 5 Mbps) Figure 5. Eye Diagram at Output (3.3 V to 5 V Level Translation, 5 Mbps) DT RTE = 5Mbps C L = 5pF DT RTE = 5Mbps C L = 5pF 5mV/DIV 3ns/DIV mV/DIV 3ns/DIV 557- Figure 3. Eye Diagram at Output (.8 V to 3.3 V Level Translation, 5 Mbps) Figure. Eye Diagram at Output (5 V to 3.3 V Level Translation, 5 Mbps) Rev. Page of

12 DG33 TEST CIRCUITS DG33.µF.µF DG33 K.µF.µF K K I OH I OL Figure 7. VOH/VOL Voltages at Pin Figure 3. Three-State Leakage Current at Pin DG33.µF.µF DG33 K.µF.µF K I OH I OL K Figure 8. VOH/VOL Voltages at Pin Figure 3. Pin Leakage Current DG33 DG33.µF.µF K CPCITNCE METER Figure 9. Three-State Leakage Current at Pin Figure 3. Capacitance at Pin DG33 CPCITNCE METER Figure 33. Capacitance at Pin Rev. Page of

13 DG33.µF DG33 MΩ SIGNL SOURCE R S 5Ω V V DIRECTION + µf +.µf µf K Z = 5Ω 5pF V K MΩ R T 5Ω DIRECTION.µF + µf DG33 +.µf µf MΩ SIGNL SOURCE R S 5Ω K MΩ Z = 5Ω V V 5pF V K RT 5Ω V V /V 9% V /V t V / V / V V V /V t V / V /V % V / V NOTE: t IS THE LRGEST OF t ND t IN BOTH ND DIRECTIONS Figure 3. Enable Time Rev. Page 3 of

14 DG33 SIGNL SOURCE R S 5Ω Z = 5Ω V +.µf µf DG33 +.µf µf V +.µf µf V DG33 +.µf µf V Z = 5Ω SIGNL SOURCE R S 5Ω R T 5Ω 5pF 5pF R T 5Ω V V 5% 5% 9% 5% % V t P, t F, t P, t R, % 5% % V t P, t F, t P, t R, Figure 35. Switching Characteristics ( Level Translation) Figure 3. Switching Characteristics ( Level Translation) Rev. Page of

15 DG33 TERMINOLOG VIH Logic input high voltage at Pin. VIL Logic input low voltage at Pin. VOH Logic output high voltage at Pin. VOL Logic output low voltage at Pin. C Capacitance measured at Pin ( = ). IL, HiZ Leakage current at Pin when = (Pin three-stated). VIH Logic input high voltage at Pin. VIL Logic input low voltage at Pin. VOH Logic output high voltage at Pin. VOL Logic output low voltage at Pin. C Capacitance measured at Pin ( = ). IL, HiZ Leakage current at pin and when = (Pin three-stated). VIH Logic input high voltage at the pin. VIL Logic input low voltage at the pin. C Capacitance measured at pin. IL Enable () pin leakage current. t Three-state enable time for Pin and Pin. tr, Rise time when translating logic levels in the direction. tf, Fall time when translating logic levels in the direction. DMX, Guaranteed data rate when translating logic levels in the direction under the driving and loading conditions specified in Table. tppskew, Difference in propagation delay between any one channel and the same channel on a different part (under same driving/loading conditions) when translating in the direction. tp, Propagation delay when translating logic levels in the direction. tr, Rise time when translating logic levels in the direction. tf, Fall time when translating logic levels in the direction. DMX, Guaranteed data rate when translating logic levels in the direction under the driving and loading conditions specified in Table. tppskew, Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the direction. ICC VCC supply current. ICC VCC supply current. IHiZ VCC supply current during three-state mode ( = ). IHiZ VCC supply current during three-state mode ( = ). tp, Propagation delay when translating logic levels in the direction. Rev. Page 5 of

16 DG33 THEOR OF OPERTION The DG33 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCC and VCC (VCC VCC). These supplies set the logic levels on each side of the device. When driving the pin, the device translates the VCC-compatible logic levels to VCC-compatible logic levels available at the pin. Similarly, because the device is capable of bidirectional translation, when driving the pin the VCC-compatible logic levels are translated to VCC-compatible logic levels available at the pin. When =, the pin and the pin are three-stated. When is driven high, the DG33 goes into normal operation mode and performs level translation. LEVEL TRNSLTOR RCHITECTURE The DG33 consists of a single bidirectional channel that can translate logic levels in either the or the direction. It uses a one-shot accelerator architecture that ensures excellent switching characteristics. Figure 37 shows a simplified block diagram of the DG33 level translator. T T kω U kω P ONE-SHOT GERTOR N U U U3 Figure 37. Simplified Block Diagram of an DG33 Channel The logic level translation in the direction is performed using a level translator (U) and an inverter (U), while the translation in the direction is performed using the inverters U3 and U. The one-shot generator detects a rising or falling edge present on either the side or the side of the channel. It sends a short pulse that turns on the PMOS transistors (T and T) for a rising edge, or the NMOS transistors (T3 and T) for a falling edge. This charges/discharges the capacitive load faster, which results in fast rise and fall times. T T INPUT DRIVING REQUIREMTS To ensure correct operation of the DG33, the circuit that drives the input of an DG33 channel must have an output impedance of less than or equal to 5 Ω and a minimum peak current driving capability of 3 m. OUTPUT LOD REQUIREMTS The DG33 level translator is designed to drive CMOScompatible loads. If current driving capability is required, it is recommended to use buffers between the DG33 outputs and the load. BLE OPERTION The DG33 provides three-state operation at the I/O pin and I/O pin by using the enable () pin as shown in Table. Table. Truth Table I/O Pin I/O Pin Hi-Z Hi-Z Normal operation Normal operation High impedance state. In normal operation, the DG33 performs level translation. While =, the DG33 enters into tri-state mode. In this mode, the current consumption from both the VCC and VCC supplies is reduced, allowing the user to save power, which is critical especially on battery-operated systems. The input pin can be driven with either VCC- or VCC-compatible logic levels. POWER SUPPLIES For proper operation of the DG33, the voltage applied to the VCC must be always less than or equal to the voltage applied to VCC. To meet this condition, the recommended power-up sequence is VCC first and then VCC. The DG33 operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where, during power-up, VCC may be greater than VCC due to a significant increase in the current taken from the VCC supply For optimum performance, the VCC and VCC pins should be decoupled to, and placed as close as possible to the device. Rev. Page of

17 DG33 DT RTE The maximum data rate at which the device is guaranteed to operate is a function of the VCC and VCC supply voltage combination and the load capacitance. It represents the maximum frequency of a square wave that can be applied to the I/O pins, which ensures that the device operates within the datasheet specifications in terms of output voltage (VOL and VOH) and power dissipation (the junction temperature does not exceed the value specified under the bsolute Maximum Ratings section). Table 5 shows the guaranteed data rates at which the DG33 can operate in both directions ( or level translation) for various VCC and VCC supply combinations. Table 5. Guaranteed Data Rate (Mbps) VCC.8 V (.5 V to.95 V).5 V (.3 V to.7 V) VCC 3.3 V (3. V to 3. V) 5 V (.5 V to 5.5 V). V (.5 V to.3 V) V (.5 V to.95 V) V (.3 V to.7 V) V (3. V to 3. V) 5 5 V (.5 V to 5.5 V) The load capacitance used is 5 pf when translating in the direction and 5 pf when translating in the direction. Rev. Page 7 of

18 DG33 PPLICTIONS The DG33 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the pin, and the higher voltage logic signals are connected to the pin. The DG33 can provide level translation in both directions from or, eliminating the need for a level translator IC for each direction. The internal architecture allows the DG33 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made. This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation. Figure 38 shows an application where a.8 V microprocessor transfers data to or from a 3.3 V peripheral device using the DG33 level translator. LOUT GUIDELINES s with any high speed digital IC, the printed circuit board layout is important for the overall performance of the circuit. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCC and VCC) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCC and VCC pins. The parasitic inductance of the high-speed signal track might cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. solid copper plane for the return path () is also recommended. nf nf.8v DG33 3.3V I/O L 5 I/O H MICROPROCESSOR/ MICROCONTROLLER/ DSP 3 PERIPHERL DEVICE Figure 38.8 V to 3.3 V Level Translation Circuit Rev. Page 8 of

19 DG33 OUTLINE DIMSIONS PIN.3 BSC.5 BSC MX.3.5. COPLNRIT SETING PLNE COMPLINT TO JEDEC STNDRDS MO-3-B Figure 39. -Lead Thin Shrink Small Outline Transistor Package [SC7] (KS-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Branding Package Option DG33BKSZ-REEL C to +85 C -Lead Thin Shrink Small Outline Transistor Package SH KS- DG33BKSZ-REEL7 C to +85 C -Lead Thin Shrink Small Outline Transistor Package SH KS- Branding on this package is limited to three characters due to space constraints. Z = Pb-free part. Rev. Page 9 of

20 DG33 NOTES 5 nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D557--/5() Rev. Page of