Vector Engine Processor of SX-Aurora TSUBASA

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1 Vector Engine Processor of SX-Aurora TSUBASA Shintaro Momose, Ph.D., NEC Deutschland GmbH 9 th October, 2018 WSSP 1 NEC Corporation 2018

2 Contents 1) Introduction 2) VE Processor Architecture 3) Performance 4) 2 Dimensional Vector Function

3 SX-Aurora TSUBASA

4 SX-Aurora TSUBASA 4 NEC Corporation 2018

5 Design Strategy 1.22TB/s / processor, 150GB/s / core Fortran/C/C++ programing, OpenMP Automatic vectorization/parallelization High sustained performance on x86/linux environment 5 NEC Corporation 2018

6 Scalable Vector Supercomputer Supercomputer Model For large scale configurations DLC with 40 C/104 F water A500 series Rack Mount Model Flexible configuration Air Cooled A300 series 64VE- 2VE 4VE 8VE Tower Model For developer/programmer Personal supercomputer A100 series 1VE 6 NEC Corporation 2018

water cooling available Active Cooling Type For Tower/Workstation 40

7 Vector Engine Card Air Cooled Card Two types of packages Passive Cooling Type For Server Water Cooled Card Direct liquid cooling Hot water cooling available Active Cooling Type For Tower/Workstation 40 C/104 F water Direct Liquid Cooling Type For Supercomputer 7 NEC Corporation 2018

8 Vector Engine

Vector Engine Card Implementation POWER [WATT] Standard PCIe card PCIe Gen3 x16 interface Full-length full-height card Dual slot <300W power Vector engine processor

9 Vector Engine Card Implementation POWER [WATT] Standard PCIe card PCIe Gen3 x16 interface Full-length full-height card Dual slot <300W power Vector engine processor module AUX power inlet Power consumption under benchmark workloads PCIe Gen3 x16 interface Voltage regulator 0 DGEMM STREAM HPCG 9 NEC Corporation 2018

10 Vector Engine Processor Module 2.5D implementation A VE processor and six 8Hi or 4Hi modules on a silicon interposer VE processor Silicon interposer Lidless package to minimize thermal resistance Package size: 60mm x 60mm Interposer size: 32.5mm x 38mm VE processor size: 15mm x 33mm VE processor Silicon interposer Stiffener Organic substrate Stiffener Organic substrate 10 NEC Corporation 2018

Vector Engine Processor Overview I/F I/F LLC 8MB I/F core core core core core core core core I/F I/F LLC 8MB I/F Components 8 vector cores 16MB LLC 2D mesh network on chip DMA engine 6 controllers

11 Vector Engine Processor Overview I/F I/F LLC 8MB I/F core core core core core core core core I/F I/F LLC 8MB I/F Components 8 vector cores 16MB LLC 2D mesh network on chip DMA engine 6 controllers and interfaces DMA Engine PCI Express Gen3 x16 interface Specs Core frequency Core performance CPU performance Memory bandwidth Memory capacity Technology 16nm FinFET process 1.6GHz 307GF(DP) 614GF(SP) 2.45TF(DP) 4.91TF(SP) 1.2TB/s 24/48GB PCIe I/F 11 NEC Corporation 2018

12 Vector Core Vector Processing Unit (VPU) Powerful computing capability 307.2GFLOPS DP / 614.4GFLOPS SP performance High bandwidth memory access 409.6GB/sec Load and Store Scalar Processing Unit (SPU) Provides the basic functionality as a processor Fetch, decode, branch, add, exception handling, etc Controls the status of complete core Address translation and data forwarding crossbar To support contiguous vector memory access 16 elements/cycle vector address generation and translation, 17 requests/cycle issuing 409.6GB/sec load and 409.6GB/sec store data forwarding Scalar Processing Unit Vector Processing Unit Address generation and translation Request/Reply crossbar 64 Scalar Registers 1 Inst. / cycle 1 Inst. / cycle 64 Vector Registers, 256 words Address Translation Buffer 17 Requests / cycle 16 Vector Mask Registers 32 elements / cycle Memory network 32 elements / cycle 12 NEC Corporation 2018

Vector Processing Unit Four pipelines, each 32-way parallel FMA0: FP fused multiply-add, integer multiply FMA1: FP fused multiply-add, integer multiply ALU0/FMA2: Integer add, multiply, mask, FP FMA

13 Vector Processing Unit Four pipelines, each 32-way parallel FMA0: FP fused multiply-add, integer multiply FMA1: FP fused multiply-add, integer multiply ALU0/FMA2: Integer add, multiply, mask, FP FMA ALU1/Store: Integer add, store, complex operation Doubled SP performance by 32bit x 2 packed vector data support Vector register (VR) renaming with 256 physical VRs 64 architectural VRs are renamed Enhanced preload capability Avoidance of WAR and WAW dependencies OoO scheduling Dedicated complex operation pipeline to prevent pipeline stall Vector sum, divide, mask population count, etc. Total 96 FMAs 13 NEC Corporation 2018

14 Scalar Processing Unit General enhancements 4 instructions / cycle fetch and decode Sophisticated branch prediction OoO scheduling 8-level speculative execution Four scalar instruction pipes Two 32kB L1 caches + unified 256kB L2 cache Hardware prefetch Support for contiguous vector operation Dedicated vector instruction pipe 16 elements / cycle coherency control for vector store Vector coherence control Vector address 32kB L1 I cache Predecode 32kB L1 O cache 256kB L2 cache Load miss queue Memory reply Fetch Decode Unified scheduler Scalar register (64 architectural + 48 renaming) Memory Branch Integer/FP Memory request Integer/FP Vector Branch prediction Prefetch Controller Vector instruction 14 NEC Corporation 2018

15 Memory Subsystem High bandwidth 409.6GB/s x2 core bandwidth Over 3TB/s LLC bandwidth 1.2TB/s memory bandwidth Caches Scalar L1/L2 caches in each core 16MB shared LLC Two memory networks 2D mesh NoC for core memory access Ring bus for DMA and PCIe traffic DMA engine Used by both vector cores and x86 node Can access VE memory, VE registers, and x86 memory 15 NEC Corporation 2018

16 Network on chip (NoC) 2D mesh network Maximize bandwidth with minimal wiring Minimizing data transfer distance 16 layered mesh Deadlock avoidance Dimension-ordered routing Virtual channels for request and reply Adaptive flow control Age based QoS control L3 L14 L7 L10 L11 L6 L15 L2 L0 L13 L4 L9 L8 L5 L12 L1 L0 LLC Core Core L15 L15 L11 L7 L3 L14 L10 L6 Crossbar L13 L2 L4 L11 L8 L7 L12 L3 L1 L14 L5 L10 L9 L6 L0 L15 L4 L11 L8 L7 L12 L3 L1 L14 L5 L10 L9 L6 L13 L2 L2 L3 L14 L7 L10 L11 L6 L15 L2 L0 L13 L4 L9 L8 L5 L12 L1 16 NEC Corporation 2018

17 Last Level Cache (LLC) Memory side cache Avoiding massive snoop traffic Increasing efficiency of indirect memory access 16MB, write back #0 LLC #0 LLC #1 #1 Inclusive of L1 and L2 High bandwidth design LLC #2 LLC #3 128 banks, in total more than 3TB/s bandwidth Auto data scrubbing Assignable data buffer feature #2 LLC #4 NoC LLC #5 #3 Priority of data can be controlled by a flag for vector memory access instructions #4 LLC #6 LLC #7 #5 200GB/s Total 3TB/s 17 NEC Corporation 2018

Benchmarks Benchmark conditions SX-Aurora TSUBASA: SX-Aurora TSUBASA A500 model Intel Xeon: Intel Xeon Gold 6142 2

18 Benchmarks Benchmark conditions SX-Aurora TSUBASA: SX-Aurora TSUBASA A500 model Intel Xeon: Intel Xeon Gold sockets, 192GB DDR NVIDIA Tesla V100: Intel Xeon CPU E5-2630v4 2 sockets, 128GB DDR4-2400, NVIDIA Tesla V100 16GB

19 BW, efficiency (Xeon=1) Basic Performance Perf., efficiency (Xeon=1) Floating point calculation and memory bandwidth STREAM,Triad (Memory bandwidth) DGEMM (Floating point performance) SX-Aurora TSUBASA Intel Xeon Gold P NVIDIA Tesla V SX-Aurora TSUBASA Intel Xeon Gold P NVIDIA Tesla V100 Bandwidth BW/watt Industry leading memory access performance and efficiency Performance Perf./watt Comfortable enough compute capability for memory intensive workloads 19 NEC Corporation 2018

20 Perf., efficiency (Xeon=1) Performance on General Benchmarks Perf., efficiency (Xeon=1) HPCG and Himeno benchmark (Poisson equation solver) SX-Aurora TSUBASA HPCG Performance Intel Xeon Gold P Perf./watt NVIDIA Tesla V Himeno benchmark SX-Aurora TSUBASA Performance Intel Xeon Gold P Competitive performance and power efficiency available using standard programming paradigms Perf./watt NVIDIA Tesla V NEC Corporation 2018

21 Performance on Machine Learning Speed up (Spark/Xeon=1) Statistical machine learning NEC s Frovedis framework for AI/BigData processing Apache Spark MLlib compatible API Open source 80 Workloads Web ads optimization (Logistic regression) Document clustering (K-means) Recommendation (Singular value decomposition) LR K-means SVD Frovedis/SX-Aurora TSUBASA Spark/Xeon Gold P 21 NEC Corporation 2018

Summary SX-Aurora TSUBASA A new product line of vector supercomputers based on Aurora

Engine High memory bandwidth by six s configuration Enhancements of the vector

Very competitive performance and power efficiency using standard programming paradigms

22 Summary SX-Aurora TSUBASA A new product line of vector supercomputers based on Aurora architecture Vector capability is provided in a standard x86/linux environment Vector Engine High memory bandwidth by six s configuration Enhancements of the vector microarchitecture to provide high sustained performance and power efficiency Benchmarks Very competitive performance and power efficiency using standard programming paradigms Outstanding performance on statistical machine learning workloads with Frovedis framework 27 NEC Corporation 2018

23 2018 NEC Corporation. All rights reserved. Specifications are subject to change without notice. NEC is a registered trademark of NEC Corporation. All other trademarks mentioned here are the properties of their respective owners.

Performance Evaluation of a Vector Supercomputer SX-Aurora TSUBASA

Performance Evaluation of a Vector Supercomputer SX-Aurora TSUBASA Kazuhiko Komatsu, S. Momose, Y. Isobe, O. Watanabe, A. Musa, M. Yokokawa, T. Aoyama, M. Sato, H. Kobayashi Tohoku University 14 November,