Each Milliwatt Matters

Transcription

1 Each Milliwatt Matters Ultra High Efficiency Application Processors Govind Wathan Product Manager, CPG ARM Tech Symposia China 2015 November 2015

2 Ultra High Efficiency Processors Used in Diverse Markets 2

3 Ultra High Efficiency Processors Everywhere 2bn+ Entry-level phones shipped based on ARM Cortex -A5 and Cortex A7 Pricing range/spectrum: $50 to $200 3

4 Smartphone Shipments (m, units) Opportunity in Smartphones 2,200 2,000 50% Smartphones shipped in 2015 will be ARMv8-A 1,800 1,600 1,400 1,200 1, >1bn Entry-level smartphones shipped in % CAGR Premium/Mid-range Smartphones Entry-level Smartphones 8% CAGR for entry-level smartphones Source: Gartner and ARM 4

5 Accelerating Innovation with ARMv8-A Across all Markets ARMv7-A Cortex-A17 Cortex-A15 ARMv8-A Cortex-A72 Cortex-A57 High Performance Cortex-A9 Cortex-A53 High Efficiency Cortex-A7 Cortex-A5 Cortex-A35 Ultra High Efficiency 5

6 Requirements for Ultra High Efficiency Processors Efficiency first More performance Smallest area Deliver more for less In restricted power budgets Smallest silicon footprint 6

7 Introducing ARM s Most Efficient Application Processor Lower power Improved performance Advanced power management Scalable and versatile ARMv7-A 64b capable, backwards compatibility ARMv8-A 7

8 Introducing ARM s Most Efficient Application Processor Lower power Improved performance Advanced power management Scalable and versatile ARMv7-A 64b capable, backwards compatibility ARMv8-A 8

9 Relative core dynamic power Cortex-A35: Lower Power Than Cortex-A % 10% Power reduction from flow improvements Power reduction from microarchitecture enhancements Cortex-A7 Cortex-A7 Cortex-A35 Re-baselined Comparisons for same frequency implementations on 28nm process technology

10 Cortex-A35 is Smaller, Lower Power Than Cortex-A53 25% smaller core 32% lower power Smallest Lowest power 25% more efficient Most efficient 10 Same frequency implementations on 28nm process technology with identical core configurations

11 L1 Caches Instruction Queue Decode ETM Cortex-A35 Pipeline Redesigned for Maximum Efficiency Load-store SCU L2 cache Core0 Instruction Fetch Integer NEON ACP Bus I/f Governor L2 In-order, 8 stage with limited dual issue capability 11

12 L1 Caches Instruction Queue Decode ETM Redesigned Instruction Fetch Unit Advanced branch prediction reduces branch bubbles Balanced instruction fetch bandwidth for efficiency Instruction Fetch Load-store Integer SCU L2 cache ACP Smaller, power efficient instruction queue NEON Bus I/f Governor Core0 L2 12

13 L1 Caches Instruction Queue Decode ETM High Performance L1 Memory System Multi-stream automatic data prefetching Automatic write stream detection Instruction Fetch Load-store Integer SCU L2 cache ACP 512-entry main TLB Bus I/f NEON Governor Core0 L2 13

14 L1 Caches Instruction Queue Decode ETM Higher Performance L2 Memory Subsystem Increased buffering capacity and resource sharing Improved write stream efficiency Instruction Fetch Load-store Integer SCU L2 cache ACP Coherency optimizations to reduce contention NEON Bus I/f Governor Core0 L2 14

15 L1 Caches Instruction Queue Decode ETM Area Efficient NEON and Floating Point Pipeline Improved store performance Fully d double precision multiplier Load-store SCU L2 cache 5x DP FLOPs Vs. Cortex-A7 Instruction Fetch Integer ACP 2x SP FLOPs Vs. Cortex-A7 NEON Bus I/f Governor Core0 L2 15

16 L1 Caches Instruction Queue Decode ETM Configurable Bus Interfaces for Area Efficiency 128 bit AXI4 interface, or 128 bit AMBA4 ACE interface Load-store SCU L2 cache 128 bit AMBA5 CHI interface Instruction Fetch Integer ACP Optional 128 bit I/O coherent ACP port NEON Bus I/f Governor Core0 L2 16

17 L1 Caches Instruction Queue Decode ETM Governor Unit for Advanced Power Management Hardware support for entry and exit from retention Debug over power down Load-store SCU L2 cache Generic timer Instruction Fetch Integer ACP Bus I/f NEON Governor Core0 L2 17

18 Introducing ARM s Most Efficient Application Processor Lower power Improved performance Advanced power management Scalable and versatile ARMv7-A 64b capable, backwards compatibility ARMv8-A 18

19 Relative browsing performance Cortex-A35 Delivers Higher Browsing Performance x x GHz 1.2 GHz Cortex-A7 Cortex-A35 Cortex-A35 32b Same frequency implementation on 28nm 2.0 GHz 32b High performance implementation on 28nm

20 Relative Performance Cortex-A35 Delivers More Efficiency Over Cortex-A7 1.5 Cortex-A7 Cortex-A x 1.40x x 1.16x Higher performance Integer Video Float Geekbench MP1 Lower power 20 Performance comparisons at same clock frequency

21 Significant Uplift For Memory Intensive Workloads Higher performance L1 and L2 memory subsystems Advanced prefetchers Significant uplift in memory streaming performance Relative memory streaming performance 3.75x 0 Cortex-A7 Cortex-A35 32b 21 Performance comparisons at same clock frequency

22 Significant Acceleration of Cryptography Algorithms New cryptography instructions Available in AArch32 & AArch64 states Optional Relative performance at same frequency 3.5x 11.0x Accelerates AES,SHA, elliptic curve cryptography algorithms 2 0 SHA-1 AES 22 Performance comparisons at same clock frequency

23 Introducing ARM s Most Efficient Application Processor Lower power Improved performance Advanced power management Scalable and versatile ARMv7-A 64b capable, backwards compatibility ARMv8-A 23

24 New Power Management Features Standardized Q-channel power management New CPU low power modes Designed for retention These features are available in existing ARMv8-A processors 24

25 New CPU Low Power Modes to Reduce Power Cortex-A35 PD_CPU0 PD_TOP PD_CPU1 Power Domains PD_CPU PD_NEON PD_NEON PD_NEON PD_L2RAMS On On Ret Off On Ret Ret Off Lower power Cortex-A35 Power Domains Dual core configuration 25

26 Cortex-A35 Designed For Retention Hardware support for retention Cortex-A35 Automatic entry and exit from retention CPU0 NEON CPU1 RETN CPU2 RETN CPU3 RETN Q-channel simplifies integration Simplified power management Governor Power Controller Q-channel L2 Cache 26

27 Introducing ARM s Most Efficient Application Processor Lower power Improved performance Advanced power management Scalable and versatile ARMv7-A 64b capable, backwards compatibility ARMv8-A 27

28 Configurable For Markets Beyond Mobile One to four cores per cluster Configurable L1 and L2 caches Cortex Cortex-A35 ARM CoreSight Multicore Debug and Trace Optional cache protection ARMv8-A 32b/64b CPU NEON SIMD engine Floating Point Unit Core Optional I/O coherent ACP port 8-64K I-Cache, Optional Parity 8-64K D-Cache, Optional ECC 4 New configuration options for area scalability ACP SCU L2 Cache (128KB 1MB) Optional ECC 128-bit AMBA4 ACE or AMBA AXI4 or AMBA5 CHI 28

29 Cortex-A35: Most Configurable 64b Application Processor CPU0 CPU1 >10x smaller CPU3 CPU2 < 0.4 mm 2 28nm Cortex-A35 Quad core configuration 32K L1 caches, NEON TM, Crypto, 1MB L2 cache Cortex-A35 Smallest configuration Single core, 8K L1 caches, no L2 29 Configurable for applications ranging from mobile to deeply embedded

30 Relative total power Lowest Power 64b Application Processor Cortex-A35 Power Optimizations on 28nm 1.0 GHz Less than 90mW at 1.0 GHz x MHz Performance optimized Typical core configuration Very low power optimized Smallest core configuration Less than 6mW at 100 MHz

31 Introducing ARM s Most Efficient Application Processor Lower power Improved performance Advanced power management Scalable and versatile ARMv7-A 64b capable, backwards compatibility ARMv8-A 31

32 Full Backwards Compatibility, New Features Runs 32-bit (A32+T32) code unchanged New crypto and FP instructions available in AArch32 state New LD acquire/st release instructions 14 32b registers 32b Virtual Address Space Simplified Exception AArch32 Level Hierarchy AArch64 EL3, EL2, EL1, EL0 Crypto A32+T32 ISAs Crypto A64 ISA LD acquire/st release: C1x/C++11 compliant IEEE compliant floating point SP Floating Point NEON 16 x 128b registers 32 64b registers 48b Virtual Address Space DP Floating Point NEON 32 x 128b registers AArch32 ARMv8-A AArch64 32

33 64b Benefits for Entry Mobile and Beyond Realize greater performance via Larger register bank Clean instruction set Double-precision, IEEE-compliant floating point vector operations Native crypto instructions 14 32b registers 32b Virtual Address Space Simplified Exception AArch32 Level Hierarchy AArch64 EL3, EL2, EL1, EL0 Crypto A32+T32 ISAs Crypto A64 ISA LD acquire/st release: C1x/C++11 compliant IEEE compliant floating point SP Floating Point NEON 16 x 128b registers 32 64b registers 48b Virtual Address Space DP Floating Point NEON 32 x 128b registers AArch32 ARMv8-A AArch64 33

34 Entry Mobile Compute System Using Cortex-A35 Mali- V550 Video Mali- DP550 Display Cortex-A35 Mali-T820 GPU CoreLink MMU-500 CoreLink NIC-450 CoreLink TM NIC-450 Peripherals CoreLink DMC-500 CoreLink DMC-500 Memory System Integrated TrustZone DRAM 34

35 Energy Efficient ARM IP Suite for Next Gen Entry Mobile Most efficient applications processor Scalable and efficient CoreLink System IP Low power ARM Mali Processors Low power POP IP for mature process nodes 35

36 Enabling Mobile-first Experiences For Next Billion Users Cortex-A35: ARM s most efficient applications processor Ultra efficient 64b compute for next generation entry mobile Scalability and versatility for markets beyond mobile 36

37 The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright 2015 ARM Limited