Crystalfontz America, Inc.

Transcription

1 Crystalfontz America, Inc. SPECIFICATION CUSTOMER : MODULE NO.: CFAF320240L-035T-CTS APPROVED BY: ( FOR CUSTOMER USE ONLY ) PCB VERSION: SALES BY APPROVED BY CHECKED BY Crystalfontz America, Inc. 242 East Saltese Avenue Spokane Valley, WA Phone: (888) Fax: (509) techinfo@crystalfontz.com URL: Page of 32 DATA: PREPARED BY

2 Contents. Module Classification Information 2. Block Diagram 3. Electrical Characteristics 4. Absolute Maximum Ratings 5. Interface Pin Function 6. DC Characteristics 7. AC Characteristics 8. Data trafer order Setting 9. Register Depiction 0. Optical Characteristics. Contour Drawing 2.RELIABILITY TEST Page 3 of 32

3 .Module Classification Information CFA F L 035 T CTS Brand:CRYSTALFONTZ AMERICA, INC Display Type:H Character Type, G Graphic Type F TFT Type Displays Logical Dimeio: 320 pixels by 240 pixels Model PCB Variant: L Module's diagonal physical dimeion: 3.5 Backlight Type: F CCFL, White T LED, White Touch panel type: Capacitive touch panel This product is composed of a TFT LCD panel, driver ICs, FPC, Control Board and a backlight unit. The following table described the features of the CFAF320240L-035T-CTS Item Dimeion Unit Dot Matrix 320 x RGBx240(TFT) dots Module dimeion 93.5 x x 9.52 mm View area 73.x55.6 mm Active area x mm Dot size x 0.29 Driving IC package COG LCD type TFT, Negative, Tramissive View Direction 2 o clock Gray Scale Inversion 6 o clock Direction Backlight Type LED,Normally White Controller IC SSD963 *Expose the IC number blaze (Luminosity over than cd) when using the LCM may cause IC operating failure. *Color tone slight changed by temperature and driving voltage. Page 4 of 32

4 2.Block Diagram Page 5 of 32

5 3.Electrical Characteristics 3. Operating conditio: Item Supply Voltage For Logic Supply Current Symbol VCC Icc Condition VCC=3 Min 3.0 Typ Symbol Min. Typ. Max. IL (Typ) 9.8 (Typ) 2 (Typ) VL Hr Unit ma V Hour Max 3.6 Unit V ma 3.3 LED driving conditio Item Forward current Forward voltage Operating LED life time Note Note 2 : Ta = 25 _ Note 3 : Brightness to be decreased to 50% of the initial value CAUTION Do not drive the LEDs at any current over their rated maximum of 20mA (5mA recommended for longer life). Be aware that the forward voltage of white LEDs can vary (LED to LED, batch to batch, and over time) by a significant amount. We recommend using a cotant current LED power supply such as the AP3036, NCP5007, FAN5333, or similar to drive the LEDs. Do not use a cotant voltage source to drive the LEDs. Page 6 of 32

6 4.Absolute Maximum Ratings Item Power Voltage Input Signal Voltage Symbol DVDD,AVDD Vin Condition GND=0 GND=0 Min Max 5.0 VDD+0.3 Unit V V Remark Logic Output Voltage VOUT GND=0-0.3 VDD+0.3 V Note Note Note: Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above Page 7 of 32

7 5.Interface Pin Function 5. Pi Connection To Control Board P/N Symbol 8BIT Function Ground GND Power supply for Logic 2 VCC 3 BL_E Backlight control (H: On \ L: Off) 4 RS Command/Data select 8080 family MPU interface : Write signal 5 WR 8080 family MPU interface: Read signal 6 RD Data bus 7 DB0 8 DB 9 DB2 0 DB3 DB4 2 DB5 3 DB6 4 DB7 Chip select 5 CS 6 RES REST No connection 7 NC 8 FGND Frame Gnd No connection 9 NC No connection 20 NC Page 8 of 32

8 5.2 CTP PIN Definition: NOTE: PIN NAMES IN () IS FOR SPI TYPE INTERFACE INTERNAL PULL UP ON PIN 3~6(00K Ω) NOTE2:Control signal Voltage:3V~3.3V Page 9 of 32

9 6. DC CHARATERISTICS Conditio: Voltage referenced to VSS VDDD, VDDPLL =.2V VDDIO, VDDLCD = 3.3V TA = 25 C DC Characteristics Symbol Parameter PSTY Quiescent Power IIZ Input leakage current IOZ Output leakage current VOH Output high voltage VOL Output low voltage VIH Input high voltage VIL Input low voltage Test Condition Min VDDIO Typ 300 Max VDDIO 0.8VDDIO VDDIO VDDIO Page 0 of 32 Unit uw ua ua V V V V

10 7. AC Characteristics Conditio: Voltage referenced to VSS VDDD, VDDPLL =.2V VDDIO, VDDLCD = 3.3V TA = 25 C CL = 50pF (Bus/CPU Interface) CL = 0pF (LCD Panel Interface) 7. Clock Timing Table 7-:Clock Input Requirements for CLK (PLL-bypass) Symbol Parameter Min Max FCLK Input Clock Frequency (CLK) 0 TCLK Input Clock period (CLK) /fclk Units MHz Table 7-2:Clock Input Requirements for CLK Symbol Parameter Min FCLK Input Clock Frequency (CLK) 2.5 TCLK Input Clock period (CLK) /fclk Units MHz Max 50 Table 7-3:Clock Input Requirements for crystal oscillator XTAL Symbol Parameter Min Max Units FXTAL Input Clock Frequency MHz TXTAL Input Clock period /fxtal Page of 32

11 7.2 MCU Interface Timing 7.2. Parallel 6800-series Interface Timing Table 7-4: Parallel 6800-series Interface Timing Characteristics (Use CS# as clock) Symbol Parameter Min Typ Max Unit fmclk System Clock Frequency* 0 MHz / fmclk tmclk System Clock Period*.5* tmclk tpwcsh Control Pulse High Write 3 3.5* tmclk Width Read 30.5* tmclk tpwcsl Control Pulse Low Write (next write cycle) 3 9* tmclk Width Write (next read cycle) 80 9* tmclk Read 80 tas Address Setup Time 2 tah Address Hold Time 2 tdsw Data Setup Time 4 tdhw Data Hold Time tplw Write Low Time 4 tphw Write High Time 4 tplwr Read Low Time 38 tacc Data Access Time 32 tdhr Output Hold time tr Rise Time 0.5 tf Fall Time 0.5 * System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled) Figure 7-: Parallel 6800-series Interface Timing Diagram (Use CS# as Clock) Page 2 of 32

12 Table 7-5: Parallel 6800-series Interface Timing Characteristics (Use E as clock) Symbol fmclk tmclk tpwcsh Parameter System Clock Frequency* System Clock Period* Control Pulse Low Write (next write cycle) Width Write (next read cycle) Read Min / fmclk Typ - Max 0 - Unit MHz.5* tmclk 3 9* tmclk 80 9* tmclk 80.5* tmclk tpwcsl Control Pulse High Write 3 3.5* tmclk Width Read 30 tas Address Setup Time 2 tah Address Hold Time 2 tdsw Data Setup Time 4 tdhw Data Hold Time tplw Write Low Time 4 tphw Write High Time 4 tplwr Read Low Time 38 tacc Data Access Time 32 tdhr Output Hold time tr Rise Time 0.5 tf Fall Time 0.5 * System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled) Figure7-2: Parallel 6800-series Interface Timing Diagram (Use E as Clock) Page 3 of 32

13 7.2.2 Parallel 8080-series Interface Timing Table 7-6: Parallel 8080-series Interface Symbol fmclk tmclk tpwcsl Parameter System Clock Frequency* System Clock Period* Control Pulse High Write Width Read tpwcsh Control Pulse Low Write (next write cycle) Width Write (next read cycle) Read Min / fmclk Typ - Max 0 - Unit MHz.5* tmclk 3 3.5* tmclk 30.5* tmclk 3 9* tmclk 80 9* tmclk 80 tas Address Setup Time tah Address Hold Time 2 tdsw Write Data Setup Time 4 tdhw Write Data Hold Time tpwlw Write Low Time 2 tdhr Read Data Hold Time tacc Access Time 32 tpwlr Read Low Time 36 tr Rise Time 0.5 tf Fall Time 0.5 tcs Chip select setup time 2 tcsh Chip select hold time to read signal 3 * System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled) Figure 7-3: Parallel 8080-series Interface Timing Diagram (Write Cycle) Page 4 of 32

14 Figure 7-4: Parallel 8080-series Interface Timing Diagram (Read Cycle) Page 5 of 32

15 7.3 CTP I2C Timing: I2C Serial Data Trafer Format I2C master write, slave read I2C master read, slave write Lists the meanings of the mnemonics used in the above figures Page 6 of 32

16 Interface Timing Characteristics AS FOR STANDARD CTPM, HOST NEED TO USE BOTH INTERRUPT CONTROL SIGNAL AND SERIAL DATA INTERFACE TO GET THE TOUCH DATA. HERE IS THE TIMING TO GET TOUCH DATA. WRITE BYTES TO I2C SLAVE AS FOR STANDARD CTPM, HOST NEED TO USE BOTH INTERRUPT CONTROL SIGNAL AND SERIAL DATA INTERFACE TO GET THE TOUCH DATA, HERE IS THE TIMING TO GET TOUCH DATA. Page 7 of 32

17 TOUCH DATA READ PROTOCOL A DATA PACKET STARTS EITH A HEADER AND ENDS WITH CRC CODE. AS FOR 5 POINTS DATA PACKET, THE LENGTH OF THE PACKET IS ALWAYS 26 BYTES IN SPITE OF ACTUAL TOUCH POINTS. Page 8 of 32

18 7.4 SPI INTERFACE TIMING CHARACTERISTICS: NOTE():Tsysclk IS EQUAL TO ONE PERIOD OF THE DEVICE SYSTEM CLOCK(24MHz) SPI TIMING Page 9 of 32

19 8. Data trafer order Setting Pixel Data Format Both 6800 and 8080 support 8-bit, 9-bit, 6-bit, 8-bit and 24-bit data bus. Depending on the width of the data bus, the display data are packed into the data bus in different ways. Table 8-: Pixel Data Format Interfac e Cycle D[23] D[22] D[2] D[20] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[] D[0] D[9] D[8] 24 bits st R7 R6 R5 R4 R3 R2 R R0 G7 G6 G5 G4 G3 G2 G G0 8 bits st R5 R4 R3 R2 R R0 G5 G4 G3 G2 6 bits (565 format) st R5 R4 R3 R2 R G5 G4 G3 st R7 R6 R5 R4 R3 R2 R 6 bits 2 bits 9 bits 8 bits D[7] D[6] D[5] D[4] D[3] D[2] D[] D[0] B7 B6 B5 B4 B3 B2 B B0 G G0 B5 B4 B3 B2 B B0 G2 G G0 B5 B4 B3 B2 B R0 G7 G6 G5 G4 G3 G2 G G0 2nd B7 B6 B5 B4 B3 B2 B B0 R7 R6 R5 R4 R3 R2 R R0 3rd G7 G6 G5 G4 G3 G2 G G0 B7 B6 B5 B4 B3 B2 B B0 st R7 R6 R5 R4 R3 R2 R R0 G7 G6 G5 G4 2nd G3 G2 G G0 B7 B6 B5 B4 B3 B2 B B0 st R5 R4 R3 R2 R R0 G5 G4 G3 2nd G2 G G0 B5 B4 B3 B2 B B0 st R7 R6 R5 R4 R3 R2 R R0 2nd G7 G6 G5 G4 G3 G2 G G0 3rd B7 B6 B5 B4 B3 B2 B B0 Page 20of 32

20 9 Register Depiction Please coult the spec of SSD963 Version.2 Please coult the spec of FOCALTECH FT5x06 Page 2 of 32

21 0. OPTICAL CHARATERISTIC Note 2: Test equipment setup: After stabilizing and leaving the panel alone at a driven temperature for 0 minutes, the measurement should be executed. Measurement should be executed in a stable, windless, and dark room. Optical specificatio are measured by Topcon BM-7 luminance meter.0 field of view at a distance of 50cm and normal direction. Page 22 of 32

22 Note 3: Definition of Respoe time: The respoe time is defined as the LCD optical switching time interval between White state and Black state. Rise time, Tr, is the time between photo detector output inteity changed from 90 to 0. And fall time, Tf, is the time between photo detector output inteity changed from0 to 90. Note 4: Definition of contrast ratio: The contrast ratio is defined as the following expression. Note 5: White Vi = Vi50 ±.5V Black Vi = Vi50 ± 2.0V ± mea that the analog input signal swings in phase with VCOM signal. ± mea that the analog input signal swings out of phase with VCOM signal. The 00% tramission is defined as the tramission of LCD panel when all the input terminals of Page 23 of 32

23 module are electrically opened. Note 6: Definition of color chromaticity (CIE 93) Color coordinates measured at the center point of LCD Note 7: Measured at the center area of the panel when all the input terminals of LCD panel are electrically opened. Page 24 of 32

24 .Contour Drawing Page 25 of 32

25 2. RELIABILITY TEST WIDE TEMPERATURE RELIABILITY TEST N ITEM CONDITION O. STANDARD High Temp. Storage Hrs Appearance without defect 2 Low Temp. Storage Hrs Appearance without defect 3 High Temp. & High Humi. Storage 60 90%RH 240 Hrs Appearance without defect 4 High Temp. Operating Display Hrs Appearance without defect 5 Low Temp. Operating Display Hrs Appearance without defect 6 Thermal Shock -20, 30min. 70, 30min. Page 26 of 32 Appearance without defect NOTE 0 cycles