Memory: Page Table Structure. CSSE 332 Operating Systems Rose-Hulman Institute of Technology

Transcription

1 Memory: Page Table Structure CSSE 332 Operating Systems Rose-Hulman Institute of Technology

2 General address transla+on CPU virtual address data cache MMU Physical address Global memory

3 Memory management unit Translates Virtual Addresses page tables translation lookaside buffer (TLB) Page tables One for kernel addresses one or more for user space processes Page Table Entry (PTE) for user space processes Typically 32 bits page frame, protection, valid, modified, referenced

4 Address transla+on Virtual address: A logical address Virtual page number + offset Finds PTE for virtual page number Extract frame number and append offset Fail (MMU raises an exception - page fault): bounds error - outside address range validation error - non- resident page protection error - not permitted access

5 Address transla+on: simple paging 20 bits virtual page number 12 bits offset in page Real address DRAM Frames Frame X X offset Virtual address add PTE M R control bits frame number current page table register (Process) Page Table

6 Address translation example Page # (n bits) Offset (m bit) Process Page Table: Frame # (k bits) Physical Address

7 Structure of the page table Hierarchical Paging" Inverted Page Tables" Inverted Page Tables with Hashing "

8 Hierarchical page tables Break up the logical address space into multiple page tables" A simple technique is a two-level page table"

9 Two-level page-table scheme

10 Two-level paging example A logical address (on 32-bit machine with 1K page size) is divided into:" a page number consisting of 22 bits" a page offset consisting of 10 bits" Since the page table is paged, the page number is further divided into:" a 12-bit page number " a 10-bit page offset" Thus, a logical address is as follows: page number" p i " p 2 " d" page offset" 12" 10" 10" where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table"

11 Two- level page table example (2) Consider a process as described here: Logical address space is 4- GB (2 32 bytes) Size of a page is 4KB (2 12 bytes) There are pages in the process. This implies we need page table entries in the process page table. If each page table entry occupies 4- bytes, then we need a byte large page table The page table will occupy pages. Root table will consist of entries one for each page that holds part of the process page table Root table will occupy 2 12 bytes 4KB of space will be kept in main memory permanently A page access could require two disk accesses

12 Two- level page table example (3) Consider a process as described here: Logical address space is 4- GB (2 32) Size of a page is 4KB (2 12 bytes) There are 2 20 pages in the process. (2 32 /2 12 ) This implies we need 2 20 page table entries in the process page table, one entry per page. If each page table entry occupies 4- bytes, then we need a 2 22 byte (4MB) large page table. The page table will occupy 2 22 /2 12 i.e pages. Root table will consist of 2 10 entries one for each page that holds a part of the process page table Root table will occupy 2 12 bytes 4KB of space will be kept in main memory permanently A page access could require two disk accesses

13 Always in main memory Brought into main memory as needed

14 Inverted page table The page table can get very large An inverted page table is another solution An inverted page table has an entry for every frame in main memory and hence is of a fixed size This is why it is called an inverted page table Also contains info to identify process A hash function is used to map the page number (and process ID) to the frame number A PTE has a page number, process id, valid bit, modify bit, chain pointer

15 Inverted page table Virtual Address Physical Address Page # <PID, Page #> Offset Inverted Frame # Offset Page Table Search V M PID,Page # Frame # Page Frame matches Page # and PID Program Paging Hardware Memory

16 Inverted page table with hashing Virtual Address Physical Address Page # Offset Frame # Offset Hash <PID, Page #> Hash Table Inverted Page Table Page Frame Search V M PID,Page # Synonym Chain Program Paging Hardware matches Page # and PID Memory

17 Hashing techniques Hashing function: X mod 8 (b) Chained rehashing

18 Memory management concerns Problem: Page tables require at least 2 memory access per instruction One to fetch the page table entry One to fetch the data Solution: Translation Lookaside Buffer (TLB) A high- speed HW associative cache set up for page table entries Cache the address translations themselves

19 Associa+ve cache Direct page lookup Associative page lookup

20 Typical TLB use

21 Effec+ve access +me with TLB In tlb = 10ns (TLB) + 100ns (data) not in TLB: 10ns (TLB) (PT) + 100ns (data) Effective access time = 110ns (.90) + (1-.90) * 210ns = 120ns

22 Typical TLB parameters Block Size Hit Time Miss Penalty TLB Size 4 to 8 bytes (1 page table entry) 2.5 to 5 nsec (1 clock cycle) 50 to 150 nsec 32 bytes to 8 KB Desired Hit Rate 98% to 99.9%