XTX conga-x945 and conga-xa945

Transcription

1 XTX conga-x945 and conga-xa945 Intel Atom N270, Intel Core 2 Duo, Intel Core Duo and Celeron M processors with an Intel 945 chipset User's Guide Revision 1.3

2 Revision History Revision Date (dd.mm.yy) Author Changes GDA Preliminary release GDA Updated order table, specification table, and BIOS section. Added BIOS Setup Data Backup overview section Added Performance Control information to section 6.4. Added ACPI resume events table to section GDA Official Release. Added section Supply Voltage Ripple and sections 1.5.2, power consumption tables. Updated section 1.6 Supply Voltage Battery Power, section 1.7 Environmental Specifications, section 3.1 Heatspreader Dimensions diagram, section BIOS Setup Data Backup Overview diagram. Added Power Consumption Graph for Intel Core Duo U2500 ULV 1.2GHz variant and description for PP_TPM pin 60 on X2 connector. Updated complete BIOS Setup Description section GDA Added Electrostatic Sensitive Device information. Added Intel Core 2 Duo L GHz variant to document. Removed processor core voltage values from power consumption tables. Added caution statement to section 3 Heatspreader GDA Changed all references of 82945GM to 82945GME. Replaced Intel Core Duo U2500 variant with Intel Core Duo U7500. U2500 is no longer available as a standard variant. Added information about center mounting hole to 'Caution' statement in section 3 Heatspreader. Added information to 'Caution' statement in section Onboard Generated Supply Voltage. Added information to section PCI Express about x4 mode. Added note about floppy cable to section Parallel Port/Floppy Interface. Added section 5.7 'congatec Battery Management Interface'. Updated section 8 System Resources and section 9 BIOS Setup Description GDA Added conga-xa945 variant to user's guide. Improved section and added section Corrected name of SMB Alert signal in the 'ACPI Suspend and Resume Events' table in section 6.5. Was SMBALERT# but should be SMBALRT#. Added 'Note' to section 7 'Signal Descriptions and Pinout Tables'. Updated section 9, 'BIOS Setup Description'. 2/102

3 Preface This user's guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-x945/xa945. It is one of four documents that should be referred to when designing an XTX application. The other reference documents that should be used include the following: XTX Design Guide XTX Specification ETX Design Guide The links to these documents can be found on the congatec AG website at Disclaimer The information contained within this user's guide, including but not limited to any product specification, is subject to change without notice. congatec AG provides no warranty with regard to this user's guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec AG assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user's guide. In no event shall congatec AG be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user's guide or any other information contained herein or the use thereof. Intended Audience This user's guide is intended for technically qualified personnel. It is not intended for general audiences. Symbols The following symbols are used in this user's guide: Warning Warnings indicate conditions that, if not observed, can cause personal injury. Caution Cautions warn the user about how to prevent damage to hardware or loss of data. Note Notes call attention to important information that should be observed. 3/102

4 Terminology Term Description GB Gigabyte (1,073,741,824 bytes) GHZ Gigahertz (one billion hertz) kb Kilobyte (1024 bytes) MB Megabyte (1,048,576 bytes) Mbit Megabit (1,048,576 bits) khz Kilohertz (one thousand hertz) MHz Megahertz (one million hertz) PCI-EX PCI Express SATA Serial ATA PATA Parallel ATA T.O.M. Top of memory = max. DRAM installed HDA High Definition Audio I/F Interface N.C. Not connected N.A. Not available T.B.D. To be determined Copyright Notice Copyright 2006, congatec AG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from congatec AG. Some of the information found in this user's guide has been extracted WITH EXPRESS PERMISSION from the following COPYRIGHTED American Megatrends, Inc documents: AMIBIOS8_HDD_Security.pdf AMIBIOS8-Flash-Recovery-Whitepaper.pdf AMIBIOS8_SerialRedirection.pdf AMIBIOS8 Setup User's Guide The above mentioned documents are Copyright 2005 American Megatrends, Inc. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from American Megatrends, Inc. congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied as-is. 4/102

5 Trademarks Intel and Pentium are registered trademarks of Intel Corporation. Expresscard is a registered trademark of Personal Computer Memory Card International Association (PCMCIA). PCI Express is a registered trademark of Peripheral Component Interconnect Special Interest Group (PCI-SIG). I²C is a registered trademark of Philips Corporation. CompactFlash is a registered trademark of CompactFlash Association. Winbond is a registered trademark of Winbond Electronics Corp. AVR is a registered trademark of Atmel Corporation. ETX is a registered trademark of Kontron AG. AMICORE8 is a registered trademark of American Megatrends Inc. Microsoft, Windows, Windows NT, Windows CE and Windows XP are registered trademarks of Microsoft Corporation. VxWorks is a registered trademark of WindRiver. conga, congatec and XTX are registered trademark of congatec AG. All product names and logos are property of their owners. Warranty congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited warranty ("Limited Warranty"). congatec AG may in its sole discretion modify its Limited Warranty at any time and from time to time. Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec AG's option and expense. Customer will obtain a Return Material Authorization ("RMA") number from congatec AG prior to returning the non conforming product freight prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer. Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged or replaced product is shipped by congatec AG, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to congatec AG's direct customer only and is not assignable or transferable. Except as set forth in writing in the Limited Warranty, congatec AG makes no performance representations, warranties, or guarantees, either express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade. congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec AG shall not otherwise be liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive remedy against congatec AG, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the product only. 5/102

6 Certification congatec AG is certified to DIN EN ISO 9001:2000 standard. Technical Support congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products can be easily used and implemented. We request that you first visit our website at for the latest documentation, utilities and drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support department by at ETX Concept and XTXTM Extension The ETX concept is an off the shelf, multi vendor, Single-Board-Computer that integrates all the core components of a common PC and is mounted onto an application specific baseboard. ETX modules have a standardized form factor of 95mm x 114mm and have specified pinouts on the four system connectors that remain the same regardless of the vendor. The ETX module provides most of the functional requirements for any application. These functions include, but are not limited to, graphics, sound, keyboard/mouse, IDE, Ethernet, parallel, serial and USB ports. Four ruggedized connectors provide the baseboard interface and carry all the I/O signals to and from the ETX module. Baseboard designers can utilize as little or as many of the I/O interfaces as deemed necessary. The baseboard can therefore provide all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly ETX applications are scalable, which means once a product has been created there is the ability to diversify the product range through the use of different performance class ETX modules. Simply unplug one module and replace it with another, no redesign is necessary. XTX is an expansion and continuation of the well-established and highly successful ETX standard. XTX offers the newest I/O technologies on this proven form factor. Now that the ISA bus is being used less and less in modern embedded applications congatec AG offers an array of different features on the X2 connector than those currently found on the ETX platform. These features include new serial high speed buses such as PCI Express and Serial ATA. All other signals found on connectors X1, X3, and X4 remain the same in accordance to the ETX standard (Rev. 2.7) and therefore will be completely compatible. If the embedded PC application still requires the ISA bus then an ISA bridge can be implemented on the application specific baseboard or the readily available LPC bus located on the XTX module may be used. Contact congatec technical support for details. 6/102

7 Lead-Free Designs (RoHS) All congatec AG designs are created from lead-free components and are completely RoHS compliant. Electrostatic Sensitive Device All congatec AG products are electrostatic sensitive devices and are packaged accordingly. Do not open or handle a congatec AG product except at an electrostatic-free workstation. Additionally, do not ship or store congatec AG products near strong electrostatic, electromagnetic, magnetic, or radioactive fields unless the device is contained within its original manufacturer's packaging. Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty. conga-x945/xa945 Options Information The conga-x945 is available in five different optional variants. The conga-xa945 is available in one variant. This user's guide describes all of these options. Below you will find an order table showing the different configurations that are currently offered by congatec AG. Check the table for the Part no./order no. that applies to your product. This will tell you what options described in this user's guide are available on your particular module. Part-No Intel Core Duo L2400 LV 1.66GHz (Low Voltage) Core 2 Duo U7500 ULV 1.06GHz (Ultra Low Voltage) Cache 4 MByte 2 MByte 2 MByte 1 MByte 1 MByte SATA 2x 2x 2x 2x 2x SDVO Yes Yes Yes Yes Yes USB 2.0 6x 6x 6x 6x 6x PCI Express 4x 4x 4x 4x 4x Yes Yes Yes Yes Yes Suspend to RAM (S3) Intel Core 2 Duo L7400 LV 1.5GHz (Low Voltage) CPU Intel Intel Celeron M Intel Celeron M 423 ULV GHz 1.06GHz (Ultra Low Voltage) conga-xa945 Variants Part-No. CPU Intel Atom N GHz Cache 512kB SATA 2x SDVO Yes USB 2.0 6x PCI Express 4x Suspend to RAM (S3) Yes 7/102

8 Contents 1 Specifications Feature List Supported Operating Systems Mechanical Dimensions Electrical Characteristics Supply Voltage Ripple Rise Time Power Consumption conga-xa945 Intel Atom N GHz 512kB cache conga-x945 Intel Core 2 Duo L GHz 4MB cache conga-x945 Intel Core Duo L GHz 2MB cache conga-x945 Intel Core 2 Duo U GHz 2MB cache conga-x945 Intel Celeron M GHz 1MB cache conga-x945 Intel Celeron M GHz 1MB cache Supply Voltage Battery Power CMOS Battery Power Consumption Environmental Specifications Block Diagram Heatspreader Heatspreader Dimensions Exploded view of Threaded XTX Heatspreader, Module and Carrier Board Assembly Connector Subsystems Connector X PCI Bus USB Audio Onboard Generated Supply Voltage Connector X2 (XTX Extension) LPC USB Serial ATA PCI Express ExpressCard AC'97 / HDA (High Definition Audio) Digital Audio Extended System Management Connector X Graphics LCD TV-Out Serial Ports (1 and 2) Serial Infrared Interface Parallel Port/Floppy Interface Keyboard/Mouse /102

9 4.4 Connector X IDE Ethernet I²C Bus 400kHz Power Control Power Management Additional Features Watchdog Onboard Microcontroller Embedded BIOS Simplified Overview of BIOS Setup Data Backup SDVO Security Features Suspend to RAM (S3) congatec Battery Management Interface conga Tech Notes Comparison of I/O APIC to 8259 PIC Interrupt mode Native vs. Compatible IDE mode Compatible Mode Native Mode Thermal Monitor and Catastrophic Thermal Protection Processor Performance Control Thermal Management ACPI Suspend Modes and Resume Events USB 2.0 EHCI Host Controller Support Signal Descriptions and Pinout Tables X1 Connector Signal Descriptions...44 Connector X1 Pinout...46 X2 Connector Signal Descriptions (XTX extension)...47 X2 Connector Pinout...51 X3 Connector Signal Descriptions...53 X4 Connector Signal Descriptions...58 X4 Connector Pinout...61 SDVO Connector X Boot Strap Signals System Resources System Memory Map I/O Address Assignment LPC Bus Interrupt Request (IRQ) Lines Direct Memory Access (DMA) Channels PCI Configuration Space Map PCI Interrupt Routing Map PCI Bus Masters I²C Bus SM Bus BIOS Setup Description /102

10 9.1 Entering the BIOS Setup Program Boot Selection Popup Manufacturer Default Settings Setup Menu and Navigation Main Setup Screen Advanced Setup ACPI Configuration Submenu PCI Configuration Submenu PCI IRQ Resource Exclusion Submenu PCI Interrupt Routing Submenu Graphics Configuration Submenu CPU Configuration Submenu for conga-x945 variants only CPU Configuration Submenu for conga-xa945 variants only Chipset Configuration Submenu I/O Interface Configuration Submenu Clock Configuration IDE Configuration Submenu Primary/Secondary IDE Master/Slave Submenu USB Configuration Submenu USB Mass Storage Device Configuration Submenu Keyboard/Mouse Configuration Submenu Remote Access Configuration Submenu Hardware Monitoring Submenu Watchdog Configuration Submenu Boot Setup Boot Device Priority Boot Settings Configuration Security Setup Security Settings Hard Disk Security Hard Disk Security User Password Hard Disk Security Master Password Power Setup Exit Menu Additional BIOS Features Updating the BIOS BIOS Recovery BIOS Recovery via Storage Devices BIOS Recovery via Serial Port Serial Port and Console Redirection BIOS Security Features Hard Disk Security Features Industry Specifications /102

11 1 Specifications 1.1 Feature List Table 1 Feature Summary Form Factor ETX standard (Rev. 2.7) with XTXTM extension Processor Intel Atom N GHz with 512-kB L2 cache Intel Core 2 Duo L7400 LV 1.5GHz with 4-MByte L2 cache (Low Voltage) Intel Core Duo L GHz with 2-MByte L2 cache LV (Low Voltage) Intel Core Duo U7500 ULV 1.06GHz with 2-MByte L2 cache (Ultra Low Voltage) Intel Celeron M 423 ULV 1.06GHz, with 1-MByte L2 cache (Ultra Low Voltage) Intel Celeron M GHz, with 1-MByte L2 cache Memory SO-DIMM DDR2 667 up to 2-GByte Chipset Graphics and Memory Controller Hub (GMCH) Intel 82945GME Intel I/O Controller Hub 82801GBM (ICH7M) Audio Realtek ALC 203 AC'97 Rev. 2.3 compatible. Ethernet ICH7M with PHY Intel Graphics Options Intel Graphics Media Accelerator 950 with max.224mbyte Dynamic Video Memory Technology (DVMT 3.0) as well as Dual independent display support. CRT Interface 400 MHz RAMDAC Resolutions up to 70Hz (QXGA) including 85Hz (HDTV) Flatpanel Interface (integrated) 2x112MHz LVDS Transmitter Supports all 1x18, 2x18, 1x24, 2x24 Bit TFT configurations (current chipset revisions support 24Bit modes although not officially stated by Intel ) Supports both conventional (FPDI) and nonconventional (LDI) color mappings Automatic Panel Detection via EPI (Embedded Panel Interface based on VESA EDID 1.3) Resolutions 640x480 up to 1600x1200 (UXGA) Motion Video Support Up- and Downscaling High definition content decode H/W motion compensation Subpicture support Dynamic bob and weave AUX Output 2 x Intel compliant SDVO ports (serial DVO) 200MPixel/sec each Supports external DVI, TV and LVDS transmitter TV Out: Integrated TV encoder Supports component + s-video Super I/O Winbond 83627HG Peripheral Interfaces BIOS Based on AMIBIOS8-1MByte Flash BIOS with congatec Embedded BIOS features 2x Serial ATA 4x x1 PCI Express Links PCI Bus Rev x USB 2.0 (EHCI) LPC Bus (no ISA Bus) 1x EIDE (UDMA-66/100) PS/2 Keyboard, Mouse I2C Bus, Fast Mode (400 khz) multimaster Floppy (shared with LPT) LPT (EEP/ECP, shared with floppy) 2 x COM Ports, TTL Level 1 x IrDA Port AC'97/HDA (High Definition Audio codecs) Digital Audio interface Power Management ACPI 3.0 compliant with battery support. Also supports Suspend to RAM (S3). Note Some of the features mentioned in the Feature Summary are optional. Check the article number of your module and compare it to the option information list on page 7 of this user's guide to determine what options are available on your particular module. 11/102

12 1.2 Supported Operating Systems The conga-x945/xa945 supports the following operating systems Microsoft Windows Vista Microsoft Windows XP/2000 Microsoft Windows XP Embedded Microsoft Windows CE 5.0 / 6.0 Linux QNX Mechanical Dimensions 95.0 mm x mm (3.75 x 4.5 ) Height approx. 12mm (0.4 ) Electrical Characteristics Characteristics 5V Voltage +/-5% Ripple 5V_SB Min Typ Max Units Vdc mvpp Current See section 1.5 'Power Consumption' for supply current information. Voltage +/-5% Current Comment 0-20MHz Vdc ma 12/102

13 1.4.1 Supply Voltage Ripple Maximum 100mV peak to peak over a frequency band of 10Hz to 20MHz. The dynamic range shall not exceed the static range Rise Time The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum rise time of 250V/s. The smooth turn-on requires that, during the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive. 1.5 Power Consumption The power consumption values listed in this document were measured under a controlled environment. The XTX module was mounted into a special baseboard. This special baseboard does not have any power consuming components mounted on it. It provides one connector for a CRT monitor connection, a PS/2 keyboard and mouse connection, and an IDE device connection. The baseboard is powered by a Direct Current (DC) power supply that is set to output 5 Volts and is connected directly to the special baseboard. Additionally, positive and negative sense lines are connected to the baseboard in order to measure the current consumption of the module. This current consumption value is displayed by the DC power supply's readout and this is the value that is recorded as the power consumption measurement. All recorded values are approximate. All external peripheral devices, such as the hard drive, are externally powered so that they do not influence the power consumption value that is measured for the module. This ensures the value measured reflects the true power consumption of the module and only the module. A keyboard is used to configure the module and then it is 13/102

14 disconnected before the measurement is recorded. If the keyboard remained connected, an additional current consumption of approximately 10 ma is noticed. Each module was measured while running Windows XP Professional with SP2 (service pack 2) and the Power Scheme was set to Portable/Laptop. This setting ensures that Pentium M processors reduce their output during desktop idle. Celeron M processors do not support this feature and therefore run at full speed even during desktop idle. The screen resolution was set to 800x600 32bit High Color. Each module was tested while using a swissbit DDR2 PC MB memory module. Using different sizes of RAM will cause slight variances in the measured results. Power consumption values were recorded during the following stages: Windows XP Professional SP2 Desktop Idle (1000MHz for Intel Core Duo L GHz) 100% CPU workload (see note below) Windows XP Professional Standby Mode (requires setup node Suspend Mode in the BIOS to be configured to S1 POS (Power On Suspend)) Suspend to RAM (requires setup node Suspend Mode in BIOS to be configured to S3 STR (Suspend to RAM)) Note A software tool was used to stress the CPU to 100% workload. Processor Information In the following power tables there is some additional information about the processors. Intel offers processors that are considered to be low power consuming. These processors can be identified by their voltage status. Intel uses the following terms to describe these processors. If none of these terms are used then the processor is not considered to be low power consuming. LV=Low voltage ULV=Ultra low voltage When applicable, the above mentioned terms will be added to the power tables to describe the processor. For example: Intel Core Duo L GHz 2MB L2 cache LV 90nm Intel also describes the type of manufacturing process used for each processor. The following term is used: nm=nanometer The manufacturing process description is included in the power tables as well. See 14/102

15 example below. For information about the manufacturing process visit Intel 's website. Intel Core Duo L GHz 2MB L2 cache LV 65nm conga-xa945 Intel Atom N GHz 512kB cache With 512MB memory installed conga-xa945 Art. No conga-xa945 Intel Atom N GHz 512kB cache LV 65nm Layout Rev. X270X0 /BIOS Rev. X270R110 Memory Size 512MB Operating System Windows XP Professional SP2 Power State Desktop Idle 100% workload Standby Power consumption (measured 1.2 A/6 W in Amperes/Watts) A/10 W 1.3 A/6.5 W Suspend to Ram (S3) 0.1 A/0.5 W conga-x945 Intel Core 2 Duo L GHz 4MB cache With 512MB memory installed Intel Core 2 Duo L GHz 4MB L2 cache LV 65nm Layout Rev. X945B0 /BIOS Rev. X945R111 conga-x945 Art. No Memory Size 512MB Operating System Windows XP Professional SP2 Power State Desktop Idle 100% workload Standby Suspend to Ram (S3) Power consumption (measured in Amperes/Watts) 1.2 A/6 W 5.5 A/27.5 W 0.1 A/0.5 W A/8.5 W conga-x945 Intel Core Duo L GHz 2MB cache With 512MB memory installed Intel Core Duo L GHz 2MB L2 cache LV 65nm Layout Rev. X945X0 /BIOS Rev. X945R006 conga-x945 Art. No Memory Size 512MB Operating System Windows XP Professional SP2 Power State Desktop Idle 100% workload Standby Suspend to Ram (S3) Power consumption (measured in Amperes/Watts) 1.2 A/6 W 4.8 A/24 W 0.1 A/0.5 W 1.4 A/7 W 15/102

16 1.5.4 conga-x945 Intel Core 2 Duo U GHz 2MB cache With 512MB memory installed Intel Core 2 Duo U GHz 2MB L2 cache ULV 65nm Layout Rev. X945C1 /BIOS Rev. X945R111 conga-x945 Art. No Memory Size 512MB Operating System Windows XP Professional SP2 Power State Desktop Idle 100% workload Standby Suspend to Ram (S3) Power consumption (measured in Amperes/Watts) 1.2 A/6 W 3.3 A/16.5 W 0.1 A/0.5 W A/7 W conga-x945 Intel Celeron M GHz 1MB cache With 512MB memory installed Intel Celeron M GHz 1MB L2 cache ULV 65nm Layout Rev. X945A0 /BIOS Rev. X945R007 conga-x945 Art. No Memory Size 512MB Operating System Windows XP Professional SP2 Power State Desktop Idle 100% workload Standby Suspend to Ram (S3) Power consumption (measured in Amperes/Watts) 1.4 A/7 W 2.5 A/12.5 W 0.1 A/0.5 W A/7 W conga-x945 Intel Celeron M GHz 1MB cache With 512MB memory installed Intel Celeron M GHz 1MB L2 cache 65nm Layout Rev. X945A0 /BIOS Rev. X945R111 conga-x945 Art. No Memory Size 512MB Operating System Windows XP Professional SP2 Power State Desktop Idle 100% workload Standby Power consumption (measured in Amperes/Watts) 1.9 A/9.5 W 4.6 A/23 W Suspend to Ram (S3) 2.1 A/10.5 W 0.1 A/0.5 W Note All recorded power consumption values are approximate and only valid for the controlled environment described earlier. 100% workload refers to the CPU workload and not the maximum workload of the complete module. Power consumption results will vary depending on the workload of other components such as graphics engine, memory, etc. 16/102

17 Supply Voltage Battery Power 2.0V-3.6V DC Typical 3V DC CMOS Battery Power Consumption 20ºC Intel Integrated in the I/O Controller Hub 82801GBM (ICH7M) Voltage Current 3V DC 2.4 µa The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime. You should measure the CMOS battery power consumption in your customer specific application in worst case conditions, for example during high temperature and high battery voltage. The self-discharge of the battery must also be considered when determining CMOS battery lifetime. For more information about calculating CMOS battery lifetime refer to application note AN9_RTC_Battery_Lifetime.pdf, which can be found on the congatec AG website at Environmental Specifications Temperature Operation: 0 to 60 C Storage: -20 to +80 C Humidity Operation: 10% to 90% Storage: 5% to 95% Caution The above operating temperatures must be strictly adhered to at all times. When using a heatspreader the maximum operating temperature refers to any measurable spot on the heatspreader's surface. congatec AG strongly recommends that you use the appropriate congatec module heatspreader as a thermal interface between the module and your application specific cooling solution. If for some reason it is not possible to use the appropriate congatec module heatspreader, then it is the responsibility of the operator to ensure that all components found on the module operate within the component manufacturer's specified temperature range. For more information about operating a congatec module without heatspreader contact congatec technical support. Humidity specifications are for non-condensing conditions. 17/102

18 2 Block Diagram 18/102

19 3 Heatspreader An important factor for each system integration is the thermal design. The heatspreader acts as a thermal coupling device to the module. It is a 2mm thick aluminum plate. The heatspreader is thermally coupled to the CPU via a thermal gap filler and on some modules it may also be thermally coupled to other heat generating components with the use of additional thermal gap fillers. Although the heatspreader is the thermal interface where most of the heat generated by the module is dissipated, it is not to be considered as a heatsink. It has been designed to be used as a thermal interface between the module and the application specific thermal solution. The application specific thermal solution may use heatsinks with fans, and/or heat pipes, which can be attached to the heatspreader. Some thermal solutions may also require that the heatspreader is attached directly to the systems chassis therefore using the whole chassis as a heat dissipater. Caution The center mounting hole on the heatspreader must be used to ensure that all components that are required to make contact with heatspreader do so. Failure to utilize the center mounting hole will result in improper contact between these components and heatspreader thereby reducing heat dissipation efficiency. Attention must be given to the mounting solution used to mount the heatspreader and module into the system chassis. Do not use a threaded heatspreader together with threaded carrier board standoffs. The combination of the two threads may be staggered, which could lead to stripping or cross-threading of the threads in either the standoffs of the heatspreader or carrier board. For more information about this subject refer to Application Note AN14_ETX_XTX_Mounting_Solutions.pdf that can be found on the congatec website. 19/102

20 3.1 Heatspreader Dimensions Note All measurements are in millimeters. Torque specification for heatspreader screws is 0.5 Nm. 20/102

21 3.2 Exploded view of Threaded XTX Heatspreader, Module and Carrier Board Assembly 21/102

22 4 Connector Subsystems X connector Subsystems (top view) In this view the connectors are seen through the module. 4.1 Connector X1 The following subsystems can be found on connector X PCI Bus The implementation of the PCI bus complies with PCI specification Rev. 2.3 and ETX specification Rev USB The conga-x945/xa945 offers 4 USB ports, via the Intel 82801GBM (ICH7M), that are connected to the X1 connector. These ports are both USB 1.1 and 2.0 compliant. For more information about how the USB host controllers are routed see section /102

23 4.1.3 Audio The conga-x945/xa945 is equipped with a Realtek ALC203 PCI audio controller. It is AC specification compliant and legacy audio SB16TM compatible. Note The USB and Audio controllers are PCI bus devices. The BIOS allocates the necessary system resources when configuring the PCI devices Onboard Generated Supply Voltage Pins 12, 16 and 24 on the X1 connector provide the ability to connect external devices to the modules onboard generated supply voltage (3.3V±5%). 3.3V external devices can be connected to these pins but must not exceed a maximum external load of 500mA. For more information about this feature contact congatec AG technical support. Caution Do not connect pins 12, 16 and 24 to a 3.3V external power supply. This will cause a current cross-flow and may result in either a system malfunction and/or damage to the external power supply and the module. 23/102

24 4.2 Connector X2 (XTX Extension) congatec AG has chosen to replace the outdated ISA bus, currently found on ETX modules X2 connector, with the latest technologies available in todays market. This implementation is called XTX. The XTX extension is an enhancement of the highly successful ETX standard and provides consumers the ability to equip their embedded applications with the latest technology while still utilizing the ETX standard form factor. The following subsystems can be found on connector X LPC As a part of the replacement to the no longer supported ISA bus, conga-x945/xa945 offers the LPC (Low Pin Count) bus through the use of Intel 82801GBM (ICH7M). There are already many devices available for this Intel defined bus. The LPC bus corresponds approximately to a serialized ISA bus yet with a significantly reduced number of signals. Due to the software compatibility to the ISA bus, I/O extensions such as additional serial ports can be easily implemented on an application specific baseboard using this bus USB 2.0 The conga-x945/xa945 offers two additional USB ports, via the Intel 82801GBM (ICH7M), that are connected to the X2 connector. These ports are both USB 1.1 and 2.0 compliant. For more information about how the USB host controllers are routed see section Serial ATA Two Serial ATA150 connections are provided via the Intel 82801GBM (ICH7M). Serial ATA is an enhancement of the parallel ATA therefore offering higher performance. As a result of this enhancement the traditional restrictions of parallel ATA are overcome with respect to speed and EMI. Serial ATA starts with a transfer rate of 150 Mbytes/s and can be expanded up to 600 Mbytes/s in order to accommodate future developments. Serial ATA is completely protocol and software compatible to parallel ATA PCI Express The conga-x945/xa945 offers 4 x1 PCI Express links via the Intel 82801GBM (ICH7M), which can be configured to support PCI Express edge cards or ExpressCards. Additionally, these links can be statically configured as 4 x1 or 1 x4. AC_SYNC and AC_SDOUT can be used to switch PCI Express channels 0-3 between x1 and x4 mode. If both signals are each pulled-up (using 1KΩ resistors) to 3.3V at the rising edge of PWROK then x4 mode is enabled. x1 mode is used by default if these resistors are not populated. The PCI Express interface is based on the PCI Express Specification 1.0a ExpressCard The conga-x945/xa945 supports the implementation of ExpressCards, which requires the dedication of one USB port and one PCI Express lane for each ExpressCard used. 24/102

25 4.2.6 AC'97 / HDA (High Definition Audio) Digital Audio The conga-x945/xa945 provides an interface that supports the connection of AC'97 digital audio codecs as well as HDA audio codecs. For more information about this interface consult the XTX Design Guide Extended System Management conga-x945/xa945 has additional signals and functions to further improve system management. One of these signals is an output signal called FAN_PWMOUT that allows system fan control using a PWM (Pulse Width Modulation) Output. Additionally there is an input signal called FAN_TACHOIN that provides the ability to monitor the system fan's RPMs (revolutions per minute). This signal must receive two pulses per revolution in order to produce an accurate reading. For this reason a two pulse per revolution fan, or similar hardware solution, is recommended. These features are implemented by the Winbond W83627HG Super I/O. 25/102

26 4.3 Connector X3 The following subsystems can be found on connector X3. The implementation of all the subsystems comply with ETX specification 2.7. The different subsystems require I/O and IRQ resources. The necessary resources are allocated by the BIOS during the POST routine and are configured to be compatible to common PC/AT settings. You can use the BIOS setup to configure some of the parameters that relate to the specific subsystems. Check the BIOS Setup Description section for more information about how to configure a particular subsystem Graphics The conga-x945/xa945 graphics are driven by an Intel Graphics Media Accelerator 950 engine, which is incorporated into the Intel 82945GME chipset found on the conga-x945/xa LCD The Intel 82945GME chipset, found on the conga-x945/xa945, offers an integrated dual channel LVDS interface that is connected to Display Pipe B TV-Out TV-Out support is integrated into the Intel 82945GME chipset and is supported on both Display Pipe A and Pipe B Serial Ports (1 and 2) The conga-x945/xa945 offers two serial interfaces (TTL) that are provided by the Winbond W83627HG Super I/O controller located on the conga-x945/xa Serial Infrared Interface Serial port 2 can be configured as a serial infrared interface. The Infrared (IrDA) function provides point-to-point (or multi-point to multi-point) wireless communication, which can operate under various transmission protocols including IrDA SIR. This feature is also implemented by the onboard Winbond W83627HG Super I/O Parallel Port/Floppy Interface The parallel port/floppy interface can be configured as either a conventional LPT parallel port or a floppy-disk drive port. This is software implemented and can be configured in the BIOS setup program. See section of this document for information about configuring the parallel port/floppy interface. Note When using the onboard floppy interface the floppy drive must be connected via a non-twisted floppy cable versus a twisted cable. The floppy drive will not function when connected via a twisted floppy cable. 26/102

27 4.3.7 Keyboard/Mouse The implementation of these subsystems comply with ETX specification /102

28 4.4 Connector X4 The following subsystems can be found on connector X4. The implementation of all the subsystems comply with ETX specification 2.7. The different subsystems require I/O and IRQ resources. The necessary resources are allocated by the BIOS during the POST routine and are configured to be compatible to common PC/AT settings. You can use the BIOS setup to configure some of the parameters that relate to the specific subsystems. Check the BIOS Setup Description section for more information about how to configure a particular subsystem IDE The IDE host adapter is capable of UDMA-100 operation. Only the Primary IDE channel is supported Ethernet Ethernet interface is provided by an Intel integrated Fast Ethernet NIC controller. The controller is IEEE 802.3u, 10/100Base-Tx fast Ethernet compatible. The interface provides single-ended differential signals that have to be routed through an Ethernet transformer I²C Bus 400kHz The I²C bus is implemented through the use of ATMEL ATmega88 microcontroller. It provides a Fast Mode (400kHz max.) multi-master I²C Bus that has maximum I²C bandwidth Power Control PWGIN PWGIN (pin 4 on the X4 connector) can be connected to an external power good circuit or it may also be utilized as a manual reset input. In order to use PWGIN as a manual reset the pin must be grounded through the use of a momentary-contact pushbutton switch. When external circuitry asserts this signal, it's necessary that an open-drain driver drives this signal causing it to be held low for a minimum of 15ms to initiate a reset. Using this input is optional. Through the use of an internal monitor on the +5V input voltage and/or the internal power supplies the conga-x945/xa945 module is capable of generating its own power-on reset. The conga-x945/xa945 provides support for controlling ATX-style power supplies. In order to do this the power supply must provide a constant source of 5V power. When not using an ATX power supply then the conga-x945/xa945's pins PS_ON, 5V_SB, and PWRBTN# should be left unconnected. PS_ON# The PS_ON (pin 5 on the X4 connector) signal is an active-low output that turns on the main outputs of an ATX-style power supply. This open-collector signal can be pulled up 28/102

29 to the 5V_SB supply voltage through the use of a 1K resistor. Usually there is a pull-up resistor internally implemented in the power supply itself yet it is also good practice to implement a footprint for the pull-up resistor in the baseboard circuitry. PWRBTN# When using ATX-style power supplies PWRBTN# (pin 7 on the X4 connector) is used to connect to a momentary-contact, active-low pushbutton input while the other terminal on the pushbutton must be connected to ground. This signal is XTX internally pulled up to 5V_SB using a 4k7 resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this signal from the system may vary as a result of modifications made in BIOS settings or by system software. Power Supply Implementation Guidelines 5 volt input power is the sole operational power source for the conga-x945/xa945. The remaining necessary voltages are internally generated on the module using onboard power supplies. A baseboard designer should be aware of the following important information when designing a power supply for a conga-x945/xa945 application: As mentioned earlier in section the conga-x945/xa945 is capable of generating an onboard 3.3V supply with an output current that is limited to 500mA. If an external device requires more then this 500mA limit then it's necessary to design a 3.3V supply into the baseboard. Caution It is not possible to connect an external 3.3V supply to the onboard generated 3.3V supply pins on the conga-x945/xa945 module. This will cause a current cross-flow and may result in either a system malfunction and/or damage to the external power supply and the module. Sometimes when designing baseboards, baseboard designers choose to fuse power to some external devices such as keyboards or USB devices by using solid-state or polyswitch overcurrent protection devices. This results in the protective devices typically only opening after they pass several times their rated current for long periods of time. When the application power supply is incapable of generating the necessary current needed to open these protective devices it's possible that the application crashes as a result of an external fault and therefore will reduce the applications reliability as well as make a fault diagnosis of the application difficult. It has also been noticed that on some occasions problems occur when using a 5V power supply that produces non monotonic voltage when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a malfunction. It must be mentioned that this problem is quite rare but has been observed in some mobile power supply applications. The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips. This should be done during the power supply qualification phase therefore ensuring that the above mentioned problem doesn't 29/102

30 arise in the application. For more information about this issue visit and view page 25 figure 7 of the document ATX12V Power Supply Design Guide V Power Management APM 1.2 compliant. ACPI 3.0 compliant with battery support. Also supports Suspend to RAM (S3). 30/102

31 5 Additional Features 5.1 Watchdog The conga-x945/xa945 is equipped with a multi stage watchdog. This solution can be triggered by software and external OEM hardware (input pin is pin 48 on the X2 connector called WDTRG#). For more information about the Watchdog feature see the BIOS setup description section of this document and application note AN3_Watchdog.pdf on the congatec AG website at Onboard Microcontroller The conga-x945/xa945 is equipped with an ATMEL Atmega88 microcontroller. This onboard microcontroller plays an important role for most of the congatec BIOS features. It fully isolates some of the embedded features such as system monitoring or the I²C bus from the x86 core architecture, which results in higher embedded feature performance and more reliability, even when the x86 processor is in a low power mode. 5.3 Embedded BIOS The conga-x945/xa945 is equipped with congatec Embedded BIOS and has the following features: ACPI Power Management ACPI Battery Support Supports Customer Specific CMOS Defaults Multistage Watchdog User Data Storage Manufacturing Data and Board Information OEM Splash Screen Flat Panel Auto Detection BIOS Setup Data Backup (see section 5.3.1) Fast Mode I²C Bus Console Redirection and BIOS Update (flashing BIOS) via Serial Port 31/102

32 5.3.1 Simplified Overview of BIOS Setup Data Backup The above diagram provides an overview of how the BIOS Setup Data is backed up on congatec modules. OEM default values mentioned above refer to customer specific CMOS settings created using the congatec System Utility tool. 32/102

33 Once the BIOS Setup Program has been entered and the settings have been changed, the user saves the settings and exits the BIOS Setup Program using the F10 key feature. After the F10 function has been evoked, the CMOS Data is stored in a dedicated non-volatile CMOS Data Backup area located in the BIOS Flash Memory chip as well as RTC. The CMOS Data is written to and read back from the CMOS Data Backup area and verified. Once verified the F10 Save and Exit function continues to perform some minor processing tasks and finally reaches an automatic reset point, which instructs the module to reboot. After the Automatic Reset has been triggered the congatec module can be powered off and if need be removed from the baseboard without losing the new CMOS settings. 5.4 SDVO Two SDVO (Serial Digital Video Output) ports are supported via a connector located on the bottom side of conga-x945/xa945. These ports support the connection of external transmitters such as DVI, TV-Out, and LVDS. For more information about the pinout of the connector (X6) see section 7.8 of this document. 5.5 Security Features The conga-x945/xa945 can be equipped optionally with a Trusted Platform Module (TPM 1.2). This TPM 1.2 includes co-processors to calculate efficient hash and RSA algorithms with key lengths up to 2,048 bits as well as a real random number generator. Security sensitive applications like gaming and e-commerce will benefit also with improved authentication, integrity and confidence levels. 5.6 Suspend to RAM (S3) The Suspend to RAM feature is available on the conga-x945/xa congatec Battery Management Interface In order to facilitate the development of battery powered mobile systems based on embedded modules, congatec AG has defined an interface for the exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according to the congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable operating system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states,...) without the need for any additional modifications to the system BIOS. The conga-x945/xa945 BIOS fully supports this interface. For more information about this subject visit the congatec website and view the following documents: congatec Battery Management Interface Specification Battery System Design Guide conga-sbm² User s Guide 33/102

34 6 conga Tech Notes The conga-x945/xa945 has some technological features that require additional explanation. The following section will give the reader a better understanding of some of these features. This information will also help to gain a better understanding of the information found in the System Resources section of this user's guide as well as some of the setup nodes found in the BIOS Setup Program description section. 6.1 Comparison of I/O APIC to 8259 PIC Interrupt mode I/O APIC (Advanced Programmable Interrupt controller) mode deals with interrupts differently than the 8259 PIC. The method of interrupt transmission used by APIC mode is implemented by transmitting interrupts through the system bus and they are handled without the requirement of the processor to perform an interrupt acknowledge cycle. Another difference between I/O APIC and 8259 PIC is the way the interrupt numbers are prioritized. Unlike the 8259 PIC, the I/O APIC interrupt priority is independent of the actual interrupt number. A major advantage of the I/O APIC found in the chipset of the conga-x945/xa945 is that it's able to provide more interrupts, a total of 24 to be exact. It must be mentioned that the APIC is not supported by all operating systems. In order to utilize the APIC mode it must be enabled in the BIOS setup program before the installation of the OS and it only functions in ACPI mode. You can find more information about APIC in the IA32 Intel Architecture Software Developer's Manual, Volume 3 in chapter 8. Note You must ensure that your operating system supports APIC mode in order to use it Native vs. Compatible IDE mode Compatible Mode When operating in compatible mode, the SATA and PATA (Parallel ATA) controller together need two legacy IRQs (14 and 15) and are unable to share these IRQs with other devices. This is a result of the fact that the SATA and PATA controller emulate legacy IDE controllers Native Mode Native mode allows the SATA and PATA controllers to operate as true PCI devices and therefore do not need dedicated legacy resources, which means it can be configured anywhere within the system. When either the SATA or PATA controller runs in native mode it only requires one PCI interrupt for both channels and also has the ability to share this interrupt with other devices in the system. Setting Enhanced mode in the 34/102

35 BIOS setup program will automatically enable Native mode as Native mode is a subset of Enhanced mode. See section for more information about this. Running in native mode frees up interrupt resources (IRQs 14 and 15) and decreases the chance that there may be a shortage of interrupts when installing devices. Note If your operating system supports native mode then congatec AG recommends you enable it. 6.3 Thermal Monitor and Catastrophic Thermal Protection Intel Atom, Core 2 Duo, Core Duo and Celeron M processors have a thermal monitor feature that helps to control the processor temperature. The integrated TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation temperature, that the Intel Thermal Monitor uses to activate the TCC, cannot be configured by the user nor is it software visible. The Thermal Monitor can control the processor temperature through the use of two different methods defined as TM1 and TM2. TM1 method consists of the modulation (starting and stopping) of the processor clocks at a 50% duty cycle. The TM2 method initiates an Enhanced Intel Speedstep transition to the lowest performance state once the processor silicon reaches the maximum operating temperature. Note The maximum operating temperature for Intel Atom, Core 2 Duo, Core Duo and Celeron M processors is 100 C. TM2 mode is used for Intel Atom, Core 2 Duo and Core Duo processors, it is not supported by Intel Celeron M processors. Two modes are supported by the Thermal Monitor to activate the TCC. They are called Automatic and On-Demand. No additional hardware, software, or handling routines are necessary when using Automatic Mode. Note To ensure that the TCC is active for only short periods of time thus reducing the impact on processor performance to a minimum, it is necessary to have a properly designed thermal solution. The Intel Core 2 Duo, Core Duo and Celeron M processor's respective datasheet can provide you with more information about this subject. THERMTRIP# signal is used by Intel's Intel Atom, Core 2 Duo, Core Duo and Celeron M processors for catastrophic thermal protection. If the processor's silicon reaches a temperature of approximately 125 C then the processor signal THERMTRIP# will go active and the system will automatically shut down to prevent any damage to the processor as a result of overheating. The THERMTRIP# signal activation is completely independent from processor activity and therefore does not produce any bus cycles. Note In order for THERMTRIP# to be able to automatically switch off the system it is necessary to use an ATX style power supply. 35/102

36 6.4 Processor Performance Control Intel Atom, Core 2 Duo and Core Duo run at different voltage/frequency states (performance states), which is referred to as Enhanced Intel SpeedStep technology (EIST). Operating systems that support performance control take advantage of microprocessors that use several different performance states in order to efficiently operate the processor when it's not being fully utilized. The operating system will determine the necessary performance state that the processor should run at so that the optimal balance between performance and power consumption can be achieved during runtime. The Windows family of operating systems links its processor performance control policy to the power scheme setting found in the control panel option applet. Note If the Home/Office or Always On power scheme is selected when using Windows operating systems then the processor will always run at the highest performance state. For more information about this subject see chapter 8 of the ACPI Specification Revision 2.0c, which can be found at Also visit Microsoft's website and search for the document called Windows Native Processor Performance Control. The congatec BIOS allows you to limit the maximum processor frequency. This can be useful if the maximum performance is not required or if the maximum processor performance state dissipates too much power and heat. In the 'CPU Configuration' submenu of the 'BIOS Setup Program' you'll find the node for 'Max. Frequency' limitation. For each Intel Core 2 Duo and Core Duo the BIOS lists the supported frequencies. If a lower frequency than the maximum one is selected, the processor will never run at frequencies above this setting. Celeron M processors do not support Enhanced Intel SpeedStep technology. They always run at a fixed frequency. In order to limit the performance and power consumption of Celeron M processors, the congatec BIOS offers 'On-Demand Clock Modulation' support in the 'CPU Configuration' submenu of the 'BIOS Setup Program'. When 'On-Demand Clock Modulation' is enabled, the processor clock is throttled using the duty cycle determined in setup. Keep in mind that the 'On-Demand' clock modulation duty cycle indicates that the clock on to clock off interval ratio. This means that when set to 75% the clock is running 75% of the overall time and this leads to a performance decrease of approximately 25%. On the conga-x945 variant that is equipped with a Celeron M GHz CPU (article number ), the power consumption decreases approximately 3W when set to 75% duty cycle and 6W when set to 50% duty cycle. 36/102

37 The following graphs provide examples of how each maximum frequency limitation setting, found in the 'BIOS Setup Program', affects power consumption of the Intel Core Duo processor variants. 37/102

38 38/102

39 6.5 Thermal Management ACPI is responsible for allowing the operating system to play an important part in the system's thermal management. This results in the operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands put on the CPU by the application. The conga-x945/xa945 ACPI thermal solution offers three different cooling policies. Passive Cooling When the temperature in the thermal zone must be reduced, the operating system can decrease the power consumption of the processor by throttling the processor clock. One of the advantages of this cooling policy is that passive cooling devices (in this case the processor) do not produce any noise. Use the passive cooling trip point setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to start or stop the passive cooling procedure. Active Cooling During this cooling policy the operating system is turning the fan on/off. Although active cooling devices consume power and produce noise, they also have the ability to cool the thermal zone without having to reduce the overall system performance. Use the active cooling trip point setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to start the active cooling device. It is stopped again when the temperature goes below the threshold (5 C hysteresis). Critical Trip Point If the temperature in the thermal zone reaches a critical point then the operating system will perform a system shut down in an orderly fashion in order to ensure that there is no damage done to the system as result of high temperatures. Use the critical trip point setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to shut down the system. Notes The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the appropriate trip points. If passive cooling is activated and the processor temperature is above the trip point the processor clock is throttled according to the formula below. P[%] = TC1(Tn-Tn-1) + TC2(Tn-Tt) P is the performance delta Tt is the target temperature = critical trip point. The two coefficients TC1 and TC2 and the sampling period TSP are hardware dependent constants. These constants are set to fixed values for the 39/102

40 conga-x945/xa945: TC1= 1 TC2= 5 TSP= 5 seconds See section 12 of the ACPI Specification 2.0 C for more information about passive cooling. 6.6 ACPI Suspend Modes and Resume Events conga-x945/xa945 supports the S1 (POS= Power On Suspend) state and S3 (STR= Suspend to Ram). For more information about S3 wake events see section ACPI Configuration Submenu. S4 (Suspend to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by the following operating systems (S4_OS= Hibernate): Win2K WinXP The following table lists the Wake Events that resume the system from both S1 or S3 unless otherwise stated in the Conditions/Remarks column: Wake Event Conditions/Remarks Power Button Wakes unconditionally from S1-S5. GPE1# Only if configured as Lid Switch in the ACPI setup menu. Additionally the lid button has to be activated using the Windows Power Options. The best way to use it is to go to Standby (see note below) on lid button press and wake from Standby (see note below) on lid button release. GPE2# Set GPE2 Function node to Sleep Button in the ACPI setup menu or set Resume On Ring to in the Power setup menu. Onboard LAN Event Device driver must be configured for Wake On LAN support. For configuration go to Device Manager, Network Adapters, Intel(R) PRO/100 VE Network Connection and launch properties. Power Management: Allow this device to bring the computer out of standby. Advanced->Wake on LAN Options->Properties: Enable PME: Wake On Link Settings: Forced Wake On Settings: Wake on Magic & Directed Using this configuration the system will wake from Standby (see note below) in case a magic packet or a directed packet is sent. Directed packet: e.g. ping to last IP / MAC address. If there is no network cable connected to the system when it goes to Standby (see note below) mode, the system will wake from Standby (see note below) as soon as a cable is connected. SMBALRT# Wakes unconditionally from S1-S5. PCI Express WAKE# Wakes unconditionally from S1-S3. 40/102

41 Wake Event Conditions/Remarks PME# Activate the wake up capabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On PME# to in the Power setup menu. USB Mouse/Keyboard Event When Standby mode is set to S1, no special action must be taken for a USB Mouse/Keyboard Event to be used as a Wake Event. When Standby mode is set to S3, the following must be done for a USB Mouse/Keyboard Event to be used as a Wake Event.. USB Hardware must be powered by standby power source. Set USB Device Wakeup from S3/S4 to ENABLED in the ACPI setup menu. Under Windows XP add following registry entries: Add this key: HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Services\usb Under this key add the following value: USBBIOSx =DWORD: Note that Windows XP disables USB wakeup from S3, so this entry has to be added to reenable it. Configure USB keyboard/mouse to be able to wake up the system: In Device Manager look for the keyboard/mouse devices. Go to the Power Management tab and check 'Allow this device to bring the computer out of standby'. Note: When the standby state is set to S3 in the ACPI setup menu, the power management tab for USB keyboard /mouse devices only becomes available after adding the above registry entry and rebooting to allow the registry changes to take affect. RTC Alarm Activate and configure Resume On RTC Alarm in the Power setup menu. Watchdog Power Button Event Wakes unconditionally from S1-S5. PS/2 Mouse/Keyboard Only can be used as a Wake Event when in S1 mode. Event Note The above list has been verified using a Windows XP SP2 ACPI enabled installation. When using Windows XP, Standby mode is either an S1 state or S3 state depending on what has been selected in the ACPI Configuration Menu in the BIOS setup program. For more information about this see section of this document. 41/102

42 6.7 USB 2.0 EHCI Host Controller Support The 8 USB ports are shared between an EHCI host controller and the 4 UHCI host controllers. Only 6 (USB ports 0-5) of the available 8 USB ports and only 3 (UHCI 0-2) of the available 4 UHCI host controllers are supported on the conga-x945. Within the EHC functionality there is a port-routing logic that executes the mixing between the two different types of host controllers (EHCI and UHCI). This means that when a USB device is connected the routing logic determines who owns the port. If the device is not USB 2.0 compliant, or if the software drivers for EHCI support are not installed, then the UHCI controller owns the ports. Routing Diagram: 42/102

43 7 Signal Descriptions and Pinout Tables The following section describes the signals found on the four X connectors located on the bottom of the module. X1, X3, and X4 connectors are ETX standard compliant while the X2 connector complies with the XTXTM extension specification. Table 2 describes the terminology used in this section for the Signal Description tables. The PU/ PD column indicates if a XTX module pull-up or pull-down resistor has been used, if the field entry area in this column for the signal is empty, then no pull-up or pull-down resistor has been implemented by congatec. The # symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When # is not present, the signal is asserted when at a high voltage level. Note The Signal Description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs implemented by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to the respective chip's datasheet. Table 2 Signal Tables Terminology Descriptions Term Description PU congatec implemented pull-up resistor PD congatec implemented pull-down resistor I/O 3.3V Bi-directional signal 3.3V tolerant I/O 5V Bi-directional signal 5V tolerant I 3.3V Input 3.3V tolerant I 5V Input 5V tolerant I/O 3.3VSB Input 3.3V tolerant active in standby state O 3.3V Output 3.3V signal level O 5V Output 5V signal level P Power Input/Output DDC Display Data Channel PCIE In compliance with PCI Express Base Specification, Revision 1.1 SATA In compliance with Serial ATA specification, Revision 1.0a LVDS Low Voltage Differential Signal-350mV nominal; 450mV maximum differential signal TPM Trusted Platform Module 43/102

44 7.1 X1 Connector Signal Descriptions Table 3 Signal Descriptions Signal Description I/O VCC Power Supply +5VDC ±5% P External supply Power Ground P External supply 3V Power Supply +3.3VDC P See section N.C. Not Connected N.A. Do not connect SERIRQ Serial Interrupt request I 3.3V Table 4 PU/PD Comment PU 10K 3.3V PCI Signal Descriptions Signal Description of PCI Bus Signals I/O PCICLK1..4. Clock output O 3.3V REQ0..3# Bus request I 3.3V GNT0..3# Bus grant O 3.3V GNT2/3# is a boot strap signal (see note below) AD0..31 Address/Data bus lines I/O 3.3V 5V Tolerant CBE0..3# Bus command/byte enables I/O 3.3V 5V Tolerant PAR Bus parity I/O 3.3V 5V Tolerant SERR# Bus system error I/O 3.3V PU 8k2 3.3V 5V Tolerant GPERR# Bus grant parity error I/O 3.3V PU 8k2 3.3V 5V Tolerant PME# Bus power management event I/O 3.3VSB PU 10k 3.3VSB LOCK# Bus lock I/O 3.3V PU 8k2 3.3V 5V Tolerant DEVSEL# Bus device select I/O 3.3V PU 8k2 3.3V 5V Tolerant TRDY# Bus target ready I/O 3.3V PU 8k2 3.3V 5V Tolerant IRDY# Bus initiator ready I/O 3.3V PU 8k2 3.3V 5V Tolerant STOP# Bus stop I/O 3.3V PU 8k2 3.3V 5V Tolerant FRAME# Bus frame I/O 3.3V PU 8k2 3.3V 5V Tolerant PCIRST# Bus reset O 3.3V INTA# Bus interrupt A I 3.3V PU 8k2 3.3V 5V Tolerant INTB# Bus interrupt B I 3.3V PU 8k2 3.3V 5V Tolerant INTC# Bus interrupt C I 3.3V PU 8k2 3.3V 5V Tolerant Bus interrupt D I 3.3V PU 8k2 3.3V 5V Tolerant INTD# PU/PD Comment PU 8k2 3.3V REQ1..3# is a boot strap signal (see note below) 5V Tolerant Asserted during system reset Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 7.9 of this user's guide. 44/102

45 Table 5 USB Signal Descriptions Signal Description of USB Signals I/O USB0 USB Port 0, data + or D+ I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USB0# USB Port 0, data - or D- I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USB1 USB Port 1, data + or D+ I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USB1# USB Port 1, data - or D- I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USB2 USB Port 2, data + or D+ I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USB2# USB Port 2, data - or D- I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USB3 USB Port 3, data + or D+ I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USB3# USB Port 3, data - or D- I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 Table 6 PU/PD Comment Audio Signal Descriptions Signal Description of Audio Signals I/O SNDL Line-Level stereo output left O SNDR Line-Level stereo output right O AUXAL Auxiliary input A left I 22k PD Analog input (1 Vrms) AUXAR Auxiliary input A right I 22k PD Analog input (1 Vrms) MIC Microphone input I 2k2 PU AudioVref Analog input (1 Vrms) AS Analog ground of sound controller P ASVCC Analog supply of sound controller P PU/PD Comment Analog output (1 Vrms) Analog output (1 Vrms) 45/102

46 7.2 Connector X1 Pinout Table 7 X1 Connector Pinout Pin Signal Pin Signal Pin Signal Pin Signal PCICLK3 PCICLK1 REQ3# GNT2# REQ2# REQ1# GNT0# VCC SERIRQ AD0 AD1 AD4 AD6 CBE0# AD8 AD10 AD11 AD12 AD13 AD14 AD15 CBE1# PCICLK4 PCICLK2 GNT3# 3V GNT1# 3V RESERVED VCC REQ0# 3V AD2 AD3 AD5 AD7 AD9 AUXAL MIC AUXAR ASVCC SNDL AS SNDR VCC PAR GPERR# PME# LOCK# TRDY# IRDY# FRAME# AD16 AD17 AD19 AD20 AD22 AD23 AD24 VCC AD25 AD28 AD27 AD30 PCIRST# INTC# INTA# VCC SERR# Reserved USB2# DEVSEL# USB3# STOP# USB2 CBE2# USB3 AD18 USB0# AD21 USB1# CBE3# VCC AD26 USB0 AD29 USB1 AD31 INTD# INTB# 46/102

47 7.3 X2 Connector Signal Descriptions (XTX extension) Table 8 LPC Interface Signal Descriptions Signal Description I/O LPC_AD[0..3] Multiplexed Command, Address and Data. I/O 3.3V LPC_FRAME# Frame: Indicates start of a new cycle or termination of a broken cycle. O 3.3V LPC_DRQ[0..1]# Encoded DMA/Bus Master Request. I 3.3V Table 9 PU/PD Comment PU 10k 3.3V Serial ATA Signal Descriptions Signal Description I/O PU/PD Comment SATA0_RX+ SATA0_RX- Serial ATA channel 0, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 1.0a SATA0_TX+ SATA0_TX- Serial ATA channel 0, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 1.0a SATA1_RX+ SATA1_RX- Serial ATA channel 1, Receive Input differential pair. I SATA Supports Serial ATA specification, Revision 1.0a SATA1_TX+ SATA1_TX- Serial ATA channel 1, Transmit Output differential pair. O SATA Supports Serial ATA specification, Revision 1.0a SATA2_RX+ SATA2_RX- Serial ATA channel 2, Receive Input differential pair. N.C. Not supported SATA2_TX+ SATA2_TX- Serial ATA channel 2, Transmit Output differential pair. N.C. Not supported SATA3_RX+ SATA3_RX- Serial ATA channel 3, Receive Input differential pair. N.C. Not supported SATA3_TX+ SATA3_TX- Serial ATA channel 3, Transmit Output differential pair. N.C. Not supported IL_SATA# Serial ATA Interlock Switch Input. I 3.3V PU 10k 3.3V SATALED# Serial ATA Led. Open collector output pin driven during SATA command activity. OC 3.3V - SATALED# is a boot strap signal (see note below) Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 7.9 of this user's guide. 47/102

48 Table 10 PCI Express Signal Descriptions Signal Description I/O PU/PD Comment PCIE0_RX+ PCIE0_RX- PCI Express channel 0, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE0_TX+ PCIE0_TX- PCI Express channel 0, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE1_RX+ PCIE1_RX- PCI Express channel 1, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE1_TX+ PCIE1_TX- PCI Express channel 1, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE2_RX+ PCIE2_RX- PCI Express channel 2, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE2_TX+ PCIE2_TX- PCI Express channel 2, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE3_RX+ PCIE3_RX- PCI Express channel 3, Receive Input differential pair. I PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE3_TX+ PCIE3_TX- PCI Express channel 3, Transmit Output differential pair. O PCIE Supports PCI Express Base Specification, Revision 1.1 PCIE_CLK_REF+ PCIE_CLK_REF- PCI Express Reference Clock for Lanes 0 to 3. O PCIE PD 49.9R PCE_WAKE# PCI Express Wake Event: Sideband wake signal asserted by components requesting wakeup. I 3.3VSB PU 1k 3.3VSB Refer to XTX design guide for additional information Note AC_SYNC and AC_SDOUT can be used to switch PCI Express channels 0-3 between x1 and x4 mode. If both signals are each pulled-up (using 1k Ω resistors) to 3.3V at the rising edge of PWROK then x4 mode is enabled. x1 mode is used by default if these resistors are not populated. For more information refer to section 7.9 of this user's guide. 48/102

49 Table 11 ExpressCard Support Pins Descriptions Signal Description I/O PU/PD EXEC_CPPE[0..1]# ExpressCard capable card request. I 3.3VSB PU 8k2 3.3VSB EXEC_RST[0..1]# ExpressCard Reset O 3.3V PU 10k 3.3V Table 12 Comment Audio Codec Signal Descriptions Signal Description I/O PU/PD Comment AC_RST# CODEC Reset O 3.3V AC_SYNC Serial Bus Synchronization. O 3.3V AC_BIT_CLK MHz Serial Bit Clock from CODEC. O 3.3V AC_SDOUT Audio Serial Data Output to CODEC. O 3.3V AC_SDIN[0..2] Audio Serial Data Input from CODEC0..CODEC2. I 3.3V Only AC_SDIN2 is PD 10k CODECSET Disable onboard Audio Codec. I 3.3V PD 10k AC_SYNC is a boot strap signal (see note below) AC_SDOUT is a boot strap signal (see note below) Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 7.9 of this user's guide. AC_SYNC and AC_SDOUT can be used to switch PCI Express channels 0-3 between x1 and x4 mode. If both signals are each pulled-up (using 1k Ω resistors) to 3.3V at the rising edge of PWROK then x4 mode is enabled. x1 mode is used by default if these resistors are not populated. For more information refer to section 7.9 of this user's guide. Table 13 USB Signal Descriptions Signal Description I/O USBP4 USB Port 4, data + or D+ I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USBP4# USB Port 4, data - or D- I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USBP5 USB Port 5, data + or D+ I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 USBP5# USB Port 5, data - or D- I/O 3.3V USB 2.0 compliant and backwards compatible to USB 1.1 PU/PD Comment 49/102

50 Table 14 Miscellaneous Signal Descriptions Signal Description I/O PU/PD Ground. All pins should be connected to the baseboard ground plane. P 5V_SB Additional Power input for the internal P suspend and power-control circuitry. This signal is connected to XTX-Connector X4/Pin3. Refer to XTX Specification for further details. VCC 5V Power Input. All VCC pins should be connected to the baseboard 5 Volt power plane. SUS_STAT# Suspend Status: indicates that the system will O 3.3VSB be entering a low power state soon. PU 10k 3.3VSB SLP_S3# S3 Sleep Control: This signal shuts off power to all non-critical systems when in S3 (Suspend to Ram), S4 or S5 states. O 3.3VSB PU 10k 3.3VSB SLP_S5# SLP_S5# is for power plane control. This signal is used to shut power off to all noncritical systems when in the S5 (soft off) states. O 3.3VSB PU 10k 3.3VSB PCI_CLKRUN# This clock supports the PCI CLKRUN protocol. It connects to peripherals that need to request clock restart or prevention of clock stopping. I/O 3.3V PU 8k2 3.3V PCI_GNT#A reserved O 3.3V PCI_REQ#A reserved I 3.3V FAN_PWMOUT Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the fan's RPM. O 5V FAN_TACHOIN Fan tachometer input. I 5V WDTRIG Watch Dog Trigger signal. I 5V PP_TPM Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip has an internal pull-down. This signal is used to indicate Physical Presence to the TPM. I 3.3V Comment P PCI_GNT#A is a boot strap signal (see note below) PU 8k2 3.3V Requires a fan with a two pulse output. PU 10k 5V Trigger source should have OC output. Trusted Platform Module chip is optional. Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 7.9 of this user's guide. 50/102

51 7.4 X2 Connector Pinout The following table includes a reference column describing the corresponding ETX standard X2 connector pinout. Table 15 X2 Connector Pinout Pin XTXTM Signal ETX Reference Pin XTXTM Signal ETX Reference PCIE_CLK_REF+ SD14 4 SATA0_RX+ SD15 5 PCIE_CLK_REF- SD13 6 SATA0_RX- MASTER# 7 SD12 8 DREQ7 9 PCIE3_TX+ SD11 10 SATA0_TX- DACK7# 11 PCIE3_TX- SD10 12 SATA0_TX+ DREQ6 13 SD9 14 5V_SB DACK6# 15 PCIE3_RX+ SD8 16 SATA1_RX+ DREQ5 17 PCIE3_RX- MEMW# 18 SATA1_RX- DACK5# 19 VCC MEMR# 20 5V_SB DREQ0 21 EXC1_CPPE# LA17 22 SATA1_TX- DACK0# 23 EXC1_RST# LA18 24 SATA1_TX+ IRQ14 25 USBP5 LA19 26 IRQ15 27 USBP5# LA20 28 SATA2_RX+(*) IRQ12 29 LA21 30 SATA2_RX-(*) IRQ11 31 PCIE2_TX+ LA22 32 SUS_STAT# IRQ10 33 PCIE2_TX- LA23 34 PCI_CLKRUN# IO16# PCIE2_RX+ SBHE# 38 SATA2_TX-(*) M16# 39 PCIE2_RX- SA0 40 SATA2_TX+(*) OSC 41 EXC0_CPPE# SA1 42 BALE 43 EXC0_RST# SA2 44 SATA3_RX+(*) TC 45 USBP4 SA3 46 SATA3_RX-(*) DACK2# 47 USBP4# SA4 48 WDTRIG IRQ3 49 SLP_S3# SA5 50 SATALED# IRQ4 51 VCC VCC 52 VCC VCC 53 PCIE1_RX- SA6 54 SATA3_TX-(*) IRQ5 55 PCIE1_RX+ SA7 56 SATA3_TX+(*) IRQ6 57 SA8 58 IL_SATA# IRQ7 59 PCIE1_TX- SA9 60 PP_TPM SYSCLK 61 PCIE1_TX+ SA10 62 RESERVED REFSH# 63 PCE_WAKE# SA11 64 PCI_GNT#A(*) DREQ1 65 SLP_S5# SA12 66 PCI_REQ#A(*) DACK1# 51/102

52 Pin XTXTM Signal ETX Reference Pin XTXTM Signal ETX Reference PCIE0_RX- SA13 70 RESERVED DREQ3 71 PCIE0_RX+ SA14 72 RESERVED DACK3# 73 SA15 74 VCC IOR# 75 PCIE0_TX- SA16 76 RESERVED IOW# 77 PCIE0_TX+ SA18 78 RESERVED SA17 79 CODECSET SA19 80 VCC SMEMR# 81 AC_RST# IOCHRDY 82 AC_SDOUT AEN 83 VCC VCC 84 VCC VCC 85 AC_SYNC SD0 86 AC_SDIN0 SMEMW# 87 AC_SDIN1 SD2 88 AC_SDIN2 SD1 89 AC_BIT_CLK SD3 90 FAN_TACHOIN NOWS# 91 LPC_AD0 DREQ2 92 FAN_PWMOUT SD4 93 LPC_AD1 SD5 94 LPC_FRAME# IRQ9 95 LPC_AD2 SD6 96 LPC_DRQ0# SD7 97 LPC_AD3 IOCHK# 98 LPC_DRQ1# RSTDRV Note The signals marked with an asterisk symbol (*) are not supported on the conga-x945/xa /102

53 7.5 X3 Connector Signal Descriptions Table 16 Signal Descriptions Signal Description I/O VCC N.C. LTGIO0 Power Supply +5VDC, ±5% Power Ground Not connected Not connected P P N.A. N.C. Table 17 PU/PD Comment External supply External supply Do not connect Not supported CRT Signal Descriptions Signal Description of CRT signals I/O PU/PD Comment HSY VSY R G B DDCK DDDA Horizontal Synchronization Pulse Vertical Synchronization Pulse Red channel RGB Analog Video Output Green channel RGB Analog Video Output Blue channel RGB Analog Video Output Display Data Channel Clock Display Data Channel Data O 3.3V O 3.3V O O O I/O 5V I/O 5V PD 150R PD 150R PD 150R PU 2k2 5V PU 2k2 5V Analog output Analog output Analog output Table 18 TV Signal Descriptions Signal Description of CRT signals I/O PU/PD Comment SYNC Y C COMP Composite sync Luminance for S-Video or Red for SCART Chrominance for S-Video or Green for SCART Composite Video or Blue for SCART N.C. O O O PD 150R PD 150R PD 150R Not supported Analog output Analog output Analog output 53/102

54 Table 19 COM Signal Descriptions Signal Description of COM signals I/O PU/PD Comment DTR1# Data terminal ready for COM1 O 5V PU 4k7 5V DTR1# is a boot strap signal (see note below) DTR2# RI1#, RI2# TXD1, TXD2 Data terminal ready for COM2 Ring indicator for COM1/COM2 Data transmit for COM1/COM2 O 5V I 5V O 5V RXD1, RXD2 CTS1#, CTS2# RTS1# Data receive for COM1/COM2 Clear to send for COM1/COM2 Request to send for COM1 I 5V I 5V O 5V RTS2# DCD1#, DCD2# DSR1#, DSR2# Request to send for COM2 Data carrier detect for COM1/COM2 Data set ready for COM1/COM2 O 5V I 5V I 5V PD 100k 5V PD 100k 5V PU 4k7 5V TXD1 and TXD2 are boot strap signals (see note below) PD 100k 5V PD 100k 5V PD 4k7 RTS1# is a boot strap signal (see note below) PD 100k 5V PD 100k 5V PD 100k 5V Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 7.9 of this user's guide. Table 20 Keyboard and Infrared Signal Descriptions Signal Description of keyboard and infrared signals I/O PU/PD KBDAT Keyboard Data I/O 5V PU 8k2 5V KBCLK Keyboard Clock O 5V PU 8k2 5V MSDAT Mouse Data I/O 5V PU 8k2 5V MSCLK Mouse Clock O 5V PU 8k2 5V IRTX Infrared Transmit O 5V IRRX Infrared Receive I 5V Comment 54/102

55 Table 21 LVDS Flat Panel Signals Signal Description of LVDS Flat I/O Panel signals BIASON Controls display contrast voltage ON N.C. DIGON Controls display Power ON O 5V BLON# Controls display Backlight ON O 5V LCDDO0..19 LVDS channel data O LVDS DETECT# Panel hot-plug detection N.C. FPDDC_CLK DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V FPDDC_DAT DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V Table 22 PU/PD Comment Not supported PD 10k Not supported LVDS Interface Pinout Pin Signal Name R HSY VSY DETECT# (*) LCDDO[16] LCDDO[17] LCDDO[13] LCDDO[12] LCDDO[8] LCDDO[9] LCDDO[4] LCDDO[5] LCDDO[1] LCDDO[0] VCC FPDDC_DAT FPDDC_CLK BIASON (*) COMP SYNC(*) Signal Mapping TX2OUTCLKTX2OUTCLK+ TX2OUT1+ TX2OUT1TX1OUT3TX1OUT3+ TX1OUT2TX1OUT2+ TX1OUT0+ TX1OUT0- Pin Signal Name B G DDCK DDDA LCDDO[18] LCDDO[19] LCDDO[15] LCDDO[14] LCDDO[11] LCDDO[10] LCDDO[7] LCDDO[6] LCDDO[3] LCDDO[2] VCC LTGIO0 BLON# DIGON Y C Signal Mapping TX2OUT3TX2OUT3+ TX2OUT2+ TX2OUT2TX2OUT0+ TX2OUT0TX1OUTCLK+ TX1OUTCLKTX1OUT1+ TX1OUT1- TX1= Channel 1 transmit TX2= Channel 2 transmit Note The signals marked with an asterisk symbol (*) are not supported on the conga-x945/xa /102

56 Table 23 FDC Signal Descriptions Signal Description of FDC signals (shared with LPT) I/O FLPY# Floppy Interface configuration input N.A. RES DENSEL N.C. Density select: low = 250/300Kb/s high = 500/1000Kb/s Index signal Track signal Write protect signal Raw data read Disk change Head select Direction Motor step Drive select Motor select Raw write data Write enable N.A. O 5V INDEX# TRK0# WP# RDATA# DSKCHG# HDSEL# DIR# STEP# DRV MOT# WDATA# WGATE# Table 24 PU/PD Comment Not supported, see section for more information. Not available I 5V I 5V I 5V I 5V I 5V O 5V O 5V O 5V O 5V O 5V O 5V O 5V Floppy Support Mode Pinout Pin Signal FLPY# (*) VCC RESERVED RESERVED IRRX IRTX RXD2 RTS2# DTR2# DCD2# DSR2# CTS2# TXD2 RI2# VCC RXD1 RTS1# DTR1# DCD1# DSR1# CTS1# TXD1 RI1# Floppy Support Mode Pinout Pin Signal RESERVED DENSEL RESERVED HDSEL# RESERVED DIR# RESERVED STEP# DSKCHG# RDATA# WP# TRK0# INDEX# VCC DRV MOT WDATA# WGATE# MSCLK MSDAT KBCLK KBDAT Note The signals marked with an asterisk symbol (*) are not supported on the conga-x945/xa /102

57 Table 25 LPT Signal Descriptions Signal Description of LPT signals (shared with FDC) I/O LPT LPT Interface configuration input N.A. STB# AFD# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 ERR# INIT# SLIN# ACK# BUSY PE SLCT Strobe signal Automatic feed Data bus D0 Data bus D1 Data bus D2 Data bus D3 Data bus D4 Data bus D5 Data bus D6 Data bus D7 LPT error Initiate Select Acknowledge Busy Paper empty Power On O 5V O 5V I/O 5V I/O 5V I/O 5V I/O 5V I/O 5V I/O 5V I/O 5V I/O 5V I 5V O 5V O 5V I 5V I 5V I 5V I 5V Table 26 PU/PD Comment Not supported, see section for more information. LPT Support Mode Pinout Pin Signal LPT (*) VCC STB# RESERVED IRRX IRTX RXD2 RTS2# DTR2# DCD2# DSR2# CTS2# TXD2 RI2# VCC RXD1 RTS1# DTR1# DCD1# DSR1# CTS1# TXD1 RI1# Parallel Port Mode Pinout Pin Signal RESERVED AFD# PD7 ERR# PD6 INIT# PD5 SLIN# PD4 PD3 PD2 PD1 PD0 VCC ACK# BUSY PE SLCT MSCLK MSDAT KBCLK KBDAT Note The signals marked with an asterisk symbol (*) are not supported on the conga-x945/xa /102

58 7.6 X4 Connector Signal Descriptions Table 27 Signal Descriptions Signal Description I/O VCC N.C. PIDE SIDE Power Supply +5VDC, ±5% Power Ground Not connected Refers to Primary IDE channel Refers to Secondary IDE channel P P N.A. I/O N.C. Table 28 PU/PD Comment External supply External supply Do not connect Not supported IDE Signal Descriptions Signal Description of IDE signals I/O PIDE_D0..15 PIDE_A0..2 PIDE_CS1# PIDE_CS3# PIDE_DRQ PIDED_AK# PIDE_RDY PIDE_IOR# PIDE_IOW# PIDE_INTRQ SIDE_D0..15 SIDE_A0..2 SIDE_CS1# SIDE_CS3# SIDE_DRQ SIDED_AK# SIDE_RDY SIDE_IOR# SIDE_IOW# SIDE_INTRQ DASP_S PDIAG_S HDRST# CBLID_P# Primary IDE Data bus Primary IDE Address bus Primary IDE chip select channel 0 Primary IDE chip select channel 1 Primary IDE DMA request Primary IDE DMA acknowledge Primary IDE ready Primary IDE IO read Primary IDE IO write Primary IDE interrupt request Secondary IDE Data bus Secondary IDE Address bus Secondary IDE chip select channel0 Secondary IDE chip select channel1 Secondary IDE DMA request Secondary IDE DMA acknowledge Secondary IDE ready Secondary IDE IO read Secondary IDE IO write Secondary IDE interrupt request Secondary IDE Drive active Secondary IDE Master/Slave negotiation Hard Drive reset Primary IDE 80 pin cable detect I/O 3.3V O 3.3V O 3.3V O 3.3V I 3.3V O 3.3V I 3.3V O 3.3V O 3.3V I 3.3V N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. O 5V I 3.3V PU/PD Comment 5V tolerant 5V tolerant PU 4k7 3.3V 5V tolerant PU 8k2 3.3V 5V tolerant PD 10k 58/102

59 Table 29 Ethernet Signal Descriptions Signal Description of Ethernet signals I/O TXD#, TXD Ethernet transmit signal pair O RXD#, RXD Ethernet receive signal pair I ACTLED# LILED# SPEEDLED# Ethernet activity LED Ethernet link LED Ethernet speed LED, ON at 100Mb/s O 3.3V O 3.3V O 3.3V Table 30 Signals for external transformer Signals for external transformer Power Control Signals Signal Description of Power Control signals I/O PWGIN Power good input I 5V_SB PS_ON# PWRBTN# Supply of internal suspend circuit Power Save ON Power Button P O 5VSB I 5VSB Table 31 PU/PD Comment PU/PD Comment Also usable as reset input, make low with O.C. to cause reset. PU 10k 5VSB PU 10k 5VSB Power Management Signals Signal Description of Power Management signals I/O PU/PD RSMRST# Resume / reset input I 3.3VSB SMBALRT# System management bus alert input I 3.3VSB BATLOW# Battery low input I 3.3VSB GPE1# General purpose power management event input 1 General purpose power management event input 2 System management interrupt input I 3.3VSB PU 100k 3.3VSB PU 10k 3.3VSB PU 10k 3.3VSB PU 10k 3.3VSB PU 10k 3.3VSB PU 10k 3.3VSB GPE2# EXTSMI# I 3.3VSB I 3.3VSB Comment 59/102

60 Table 32 Miscellaneous Signal Descriptions Signal Description of Miscellaneous signals I/O SPEAKER Speaker output O 3.3V BATT I2CLK I2DAT SMBCLK SMBDATA KBINH# OVCR# ROMKBCS# EXT_PRG GPCS# Battery supply I2C Bus clock I2C Bus Data SM Bus clock SM Bus Data Keyboard inhibit Over current detect for USB Do not connect Do not connect General purpose chip select I I/O 5V I/O 5V I/O 3.3V I/O 3.3V I 5V I 3.3VSB N.A. N.A. N.C. PU/PD Comment SPEAKER is a boot strap signal (see note below) PU 4k7 5V PU 4k7 5V PU 2k2 3.3V PU 2k2 3.3V PU 10k 3.3VSB Not available Not available Not supported Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 7.9 of this user's guide. 60/102

61 7.7 X4 Connector Pinout Table 33 Connector X4 Pinout Pin Signal Pin Signal Pin Signal Pin Signal V_SB PS_ON# PWRBTN# KBINH# RSMRST# ROMKBCS#(*) EXT_PRG(*) VCC OVCR# EXTSMI# SMBCLK SIDE_CS3#(*) SIDE_CS1#(*) SIDE_A2(*) SIDE_A0(*) PDIAG_S(*) SIDE_A1(*) SIDE_INTRQ(*) BATLOW# SIDE_AK#(*) SIDE_RDY(*) SIDE_IOR#(*) VCC PWGIN SPEAKER BATT LILED# ACTLED# SPEEDLED# I2CLK VCC GPCS#(*) I2DAT SMBDATA SMBALRT# DASP_S(*) PIDE_CS3# PIDE_CS1# PIDE_A2 PIDE_A0 PIDE_A1 GPE1# PIDE_INTRQ PIDE_AK# PIDE_RDY VCC SIDE_IOW#(*) SIDE_DRQ(*) SIDE_D15(*) SIDE_D0(*) SIDE_D14(*) SIDE_D1(*) SIDE_D13(*) SIDE_D2(*) SIDE_D12(*) SIDE_D3(*) SIDE_D11(*) SIDE_D4(*) SIDE_D10(*) SIDE_D5(*) VCC SIDE_D9(*) SIDE_D6(*) SIDE_D8(*) GPE2# RXD# RXD TXD# TXD PIDE_IOR# PIDE_IOW# PIDE_DRQ PIDE_D15 PIDE_D0 PIDE_D14 PIDE_D1 PIDE_D13 PIDE_D2 PIDE_D12 PIDE_D3 PIDE_D11 PIDE_D4 PIDE_D10 VCC PIDE_D5 PIDE_D9 PIDE_D6 CBLID_P# PIDE_D8 SIDE_D7(*) PIDE_D7 HDRST# Note The signals marked with an asterisk symbol (*) are not supported on the conga-x945/xa /102

62 7.8 SDVO Connector X6 Connector and flat foil cable information for the SDVO connector (X6) located on the bottom side of the conga-x945/xa945. Connector type Order no. Hirose 0.5mm Pitch Bottom Contact Type FH12-45S-0.5SH (55) FFC type Manufacturer Order No. 45 positions, 30cm length, 0.5mm pitch both ends opposite sides YOUNGSHIN MCAB45x300B05 Table 34 SDVO Pinout Description Pin Signal Description 1 Ground 2 SDVOC_BCLKN Serial Digital Video C clock complement. 3 SDVOC_BCLKP Serial Digital Video C clock. 4 Ground 5 SDVOC_GREEN# Serial Digital Video C green complement. 6 SDVOC_GREEN Serial Digital Video C green. 7 Ground 8 SDVOB_BCLKN Serial Digital Video B clock complement. 9 SDVOB_BCLKP Serial Digital Video B clock. 10 Ground 11 SDVOB_GREEN# Serial Digital Video B green data complement. 12 SDVOB_GREEN Serial Digital Video B green data. 13 Ground 14 SDVOC_INT# Serial Digital Video input interrupt complement. 15 SDVOC_INT Serial Digital Video input interrupt. 16 Ground 17 SDVOB_INT# Serial Digital Video input interrupt complement. 18 SDVOB_INT Serial Digital Video input interrupt. 19 Ground 20 SDVOC_BLUE# Serial Digital Video C blue complement. 21 SDVOC_BLUE Serial Digital Video C blue data. 22 Ground 23 SDVOC_RED# Serial Digital Video C red data complement / alpha complement. PU/PD 62/102

63 Pin Signal Description PU/PD 24 SDVOC_RED Serial Digital Video C red data / SDVO B alpha. 25 Ground 26 SDVOB_BLUE# Serial Digital Video B blue data complement. 27 SDVOB_BLUE Serial Digital Video B blue data. 28 Ground 29 SDVOB_RED# Serial Digital Video B red data complement. 30 SDVOB_RED Serial Digital Video B red data. 31 Ground 32 SDVO_FLDSTALL# Serial Digital Video field stall complement. 33 SDVO_FLDSTALL Serial Digital Video field stall. 34 Ground 35 SDVO_TVCLKIN# Serial Digital Video TV-Out synchronization clock complement. 36 SDVO_TVCLKIN Serial Digital Video TV-Out synchronization clock. 37 Ground 38 SDVOCTRL_CLK I²C based control signal (Clock) for SDVO device. 39 SDVOCTRL_DATA I²C based control signal (Data) for SDVO device. SDVOCTRL_DATA is a boot strap signal (see note below) 40 PWRGOOD PWRGOOD signal PU 10k 3.3V 41 +5V Power supply +5V 42 +5V Power supply +5V 43 +5V Power supply +5V 44 SDAOUFP1 Custom 45 SDAOUFP2 Custom Note Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more information refer to section 7.9 of this user's guide. 63/102

64 7.9 Boot Strap Signals Table 35 Boot Strap signal Descriptions Signal Description of Boot Strap Signals I/O PU/PD REQ1..3# Bus request I 3.3V PU 8k2 3.3V REQ1..3# is a boot strap signal (see caution statement below) GNT2/3# Bus grant SATALED# Serial ATA Led. Open collector output pin driven during SATA command activity. OC 3.3V SATALED# is a boot strap signal (see caution statement below) PCI_GNT#A reserved O 3.3V PCI_GNT#A is a boot strap signal (see note below) AC_SYNC Serial Bus Synchronization. O 3.3V AC_SYNC is a boot strap signal (see caution statement below) AC_SDOUT Audio Serial Data Output to CODEC. O 3.3V AC_SDOUT is a boot strap signal (see caution statement below) DTR1# Data terminal ready for COM1 O 5V PU 4k7 5V DTR1# is a boot strap signal (see caution statement below) TXD1, TXD2 Data transmit for COM1/COM2 O 5V PU 4k7 5V TXD1 and TXD2 are boot strap signals (see caution statement below) RTS1# Request to send for COM1 O 5V PD 4k7 RTS1# is a boot strap signal (see caution statement below) SPEAKER Speaker output O 3.3V SDVOCTRL_DATA I²C based control signal (Data) for SDVO device. O 3.3V Comment GNT2/3# are boot strap signals (see note below) SPEAKER is a boot strap signal (see caution statement below) SDVOCTRL_DATA is a boot strap signal. Pulled high indicates an external SDVO application is present. Caution The signals listed in the table above are used as chipset configuration straps during system reset. In this condition (during reset), they are inputs that are pulled to the correct state by either XTX internally implemented resistors or chipset internally implemented resistors that are located on the module. No external DC loads or external pull-up or pull-down resistors should change the configuration of the signals listed in the above table with the exception of AC_SYNC, AC_SDOUT and SDVOCTRL_DATA. External resistors may override the internal strap states and cause the XTX module to malfunction and/or cause irreparable damage to the module. AC_SYNC and AC_SDOUT can be used to switch PCI Express channels 0-3 between x1 and x4 mode. If both signals are each pulled-up (using 1k Ω resistors) to 3.3V at the rising edge of PWROK then x4 mode is enabled. x1 mode is used by default if these resistors are not populated. SDVOCTRL_DATA can be pulled-up (using 5.6KΩ resistor) to 2.5V in order to tell the chipset to run in SDVO mode. If it is necessary to drive a TTL input (or another input which sources or sinks significant current) that uses the TXD1 signal, a CMOS-input buffer can be inserted in the signal path so that this line is not pulled up or down by external circuitry during system reset. 64/102

65 8 System Resources 8.1 System Memory Map Table 36 Memory Map Address Range (decimal) Address Range (hex) Size Description (TOM-192kB) TOM N.A. 192kB ACPI reclaim, MPS and NVS area ** (TOM-8MB-192kB) (TOM192kB) N.A. 1 or 8MB VGA frame buffer * 1024kB (TOM-8MB-192kB) N.A N.A. Extended memory 869kB 1024kB E FFFFF 128kB Runtime BIOS 800kB 869kB D DFFFF 96kB Upper memory 640kB 800kB A CFFFF 160kB Video memory and BIOS 639kB 640kB 9FC00-9FFFF 1kB Extended BIOS data 0 639kB FC00 512kB Conventional memory Note T.O.M. = Top of memory = max. DRAM installed * VGA frame buffer can be reduced to 1MB in setup. ** Only if ACPI Aware OS is set to YES in setup. 65/102

66 8.2 I/O Address Assignment The I/O address assignment of the conga-x945/xa945 module is functionally identical with a standard PC/AT. The most important addresses and the ones that differ from the standard PC/AT configuration are listed in the table below. Table 37 I/O Address Assignment I/O Address (hex) Size Available Description FF 256 bytes No Motherboard resources F 16 bytes No congatec System Control bytes No Secondary IDE channel 01F0-01F7 8 bytes No Primary IDE channels 02F8-02FF 8 bytes Note 1 Serial Port 2 (COM2) byte No Secondary IDE channel command port byte No Secondary IDE channel status port F 8 bytes Note 1 Parallel Port 1 (LPT1) 03B0 03DF 16 bytes No Video system 03F0-03F5 6 bytes No Floppy channel 1 03F6 1 byte No Primary IDE channel command port 03F7 1 byte No Primary IDE channel status port 03F8-03FF 8 bytes Note 1 Serial Port 1 (COM1) BF 64 bytes No Motherboard resources 04D0 04D1 2 bytes No Motherboard resources F 128 bytes No Motherboard resources 0A00 0A0F 16 bytes No Motherboard resources 0CF8-0CFB 4 bytes No PCI configuration address register 0CFC - 0CFF 4 bytes No PCI configuration data register Note 2 PCI / PCI Express bus 0D00 FFFF Notes 1. Default, but can be changed to another address range. 2. The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not consume I/O resources in that area. 66/102

67 8.2.1 LPC Bus On the conga-x945/xa945 the PCI Bus acts as the subtractive decoding agent. All I/O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus. Only specified I/O ranges are forwarded to the LPC Bus. In the congatec Embedded BIOS the following I/O address ranges are sent to the LPC Bus: 280 2FF 3F8 3FF 3E8 3EF A00 A0F Parts of these ranges are not available if the devices of the onboard Super I/O are activated or if an additional Super I/O is used on the carrier board. If you require additional LPC Bus resources other than those mentioned above, or more information about this subject, contact congatec technical support for assistance. 8.3 Interrupt Request (IRQ) Lines Table 38 IRQ Lines in PIC mode IRQ# Available Typical Interrupt Source Connected to Pin 0 No Counter 0 Not applicable 1 No Keyboard Not applicable 2 No Cascade Interrupt from Slave PIC Not applicable 3 Note 1 Serial Port 2 (COM2) / Generic IRQ3 via SERIRQ 4 Note 1 Serial Port 1 (COM1) / Generic IRQ4 via SERIRQ 5 Yes Not applicable IRQ5 via SERIRQ 6 Note 1 Floppy Drive Controller / Generic IRQ6 via SERIRQ 7 Note 1 Parallel Port 1 (LPT1) / Generic IRQ7 via SERIRQ 8 No Real-time Clock Not applicable 9 Note 3 SCI / Generic IRQ9 via SERIRQ 10 Yes Not applicable IRQ10 via SERIRQ 11 Yes Not applicable IRQ11 via SERIRQ 12 Note 1 PS/2 Mouse / Generic IRQ12 via SERIRQ 13 No Math processor Not applicable 14 Note 1, 2 IDE Controller 0 (IDE0) / Generic IRQ14 Note 1, 2 IDE Controller 1 (IDE1) / Generic IRQ15 15 In PIC mode, the PCI bus interrupt lines can be routed to any free IRQ. Notes 1. Default, but can be changed to another interrupt. If disabled in BIOS setup resource can be used for another purpose. 2. If the ATA/IDE configuration is set to enhanced mode in BIOS setup (serial ATA and 67/102

68 parallel ATA native mode operation), IRQ14 and 15 are free for PCI/LPC bus. 3. In ACPI mode, IRQ9 is used for the SCI (System Control Interrupt). The SCI can be shared with a PCI interrupt line. Table 39 IRQ Lines in APIC mode IRQ# Available Typical Interrupt Source Connected to Pin / Function 0 No Counter 0 Not applicable 1 No Keyboard Not applicable 2 No Cascade Interrupt from Slave PIC Not applicable 3 Note 1 Serial Port 2 (COM2) / Generic IRQ3 via SERIRQ 4 Note 1 Serial Port 1 (COM1) / Generic IRQ4 via SERIRQ 5 Yes Not applicable IRQ5 via SERIRQ 6 Note 1 Floppy Drive Controller / Generic IRQ6 via SERIRQ 7 Note 1 Parallel Port 1 (LPT1) / Generic IRQ7 via SERIRQ 8 No Real-time Clock Not applicable 9 Note 3 Generic IRQ9 via SERIRQ, option for SCI 10 Yes Not applicable IRQ10 via SERIRQ 11 Yes Not applicable IRQ11 via SERIRQ 12 Note 1 PS/2 Mouse / Generic IRQ12 via SERIRQ 13 No Math processor Not applicable 14 Note 1, 2 IDE Controller 0 (IDE0) / Generic IRQ14 15 Note 1, 2 IDE Controller 1 (IDE1) / Generic IRQ15 16 No N.A. PIRQA, Integrated VGA Controller, PCI Express Root Port 0, Intel High Definition Audio Controller (Azalia) 17 No N.A. PIRQB, AC'97 Audio, PCI Express Root Port 1 18 No N.A. PIRQC, Parallel ATA Controller in enhanced/native mode, UHCI Host Controller 2, PCI Express Root Port 2 19 No N.A. PIRQD, Serial ATA controller in enhanced/native mode, UHCI Host Controller 1, SMBus Controller, PCI Express Root Port 3 Yes N.A. PIRQE, PCI Bus INTD, onboard LAN Controller, option for SCI 21 Yes N.A. PIRQF, PCI Bus INTA 22 Yes N.A. PIRQG, PCI Bus INTB 23 Yes N.A. PIRQH, PCI Bus INTC, UHCI Host Controller 0, EHCI Host Controller 20 In APIC mode, the PCI bus interrupt lines are connected with IRQ 20, 21, 22 and 23. Notes 1. Default but can be changed to another interrupt. If disabled in BIOS setup resource can be used for another purpose. 2. If the ATA/IDE configuration is set to enhanced mode in BIOS setup (serial ATA and parallel ATA native mode operation), IRQ14 and 15 are free for PCI/LPC bus. 68/102

69 3. In ACPI mode, IRQ9 is used for the SCI (System Control Interrupt). The SCI can be shared with a PCI interrupt line. 8.4 Direct Memory Access (DMA) Channels Table 40 DMA Channels DMA# Data Width Available Description 0 8 bits Yes 1 8 bits Yes 2 8 bits Note 1 Floppy Drive Controller 3 8 bits Note 2 Parallel Port (LPT) 4 16 bits No Cascade DMA Controller 5 16 bits Yes 6 16 bits Yes 7 16 bits Yes Notes 1. If the corresponding device is disabled in BIOS setup then the DMA channel can be used by customers hardware. 2. Not available if Parallel Port is used in ECP mode (Enhanced Parallel Port). 69/102

70 8.5 PCI Configuration Space Map Table 41 PCI Configuration Space Map Bus Number Device (hex) Number (hex) Function Number (hex) PCI Interrupt Description Routing 00h 00h 00h N.A. Host Bridge 00h 02h 00h Internal VGA Graphics 00h 02h 01h N.A. VGA Graphics 00h 1Bh 00h Internal Intel High Definition Audio Controller (Azalia) 00h (Note 1) 1Ch 00h Internal PCI Express Root Port 0 00h (Note 1) 1Ch 01h Internal PCI Express Root Port 1 00h (Note 1) 1Ch 02h Internal PCI Express Root Port 2 00h (Note 1) 1Ch 03h Internal PCI Express Root Port 3 00h 1Dh 00h Internal UHCI Host Controller 0 00h 1Dh 01h Internal UHCI Host Controller 1 00h 1Dh 02h Internal UHCI Host Controller 2 00h 1Dh 07h Internal EHCI Host Controller 00h 1Eh 00h Internal PCI to PCI Bridge 00h 1Eh 02h Internal AC97 Audio Controller 00h 1Fh 00h N.A. PCI to LPC Bridge 00h 1Fh 01h Internal Parallel ATA Controller in enhanced mode 00h 1Fh 02h Internal Serial ATA Controller in enhanced mode / Parallel ATA and Serial ATA as combined IDE Controller in compatible mode 00h 1Fh 03h Internal SMBus Host Controller 01h (Note 1) 00h xxh Internal PCI Express Port 0 02h (Note 1) 00h xxh Internal PCI Express Port 1 03h (Note 1) 00h xxh Internal PCI Express Port 2 04h (Note 1) 00h xxh Internal PCI Express Port 3 05h (Note 1) 08h 00h Internal Onboard LAN Controller 05h (Note 1) 03h xxh INTA-INTD PCI Bus Slot 1 05h (Note 1) 04h xxh INTA-INTD PCI Bus Slot 2 05h (Note 1) 05h xxh INTA-INTD PCI Bus Slot 3 05h (Note 1) 06h xxh INTA-INTD PCI Bus Slot 4 Notes 1. The given bus numbers only apply if all PCI Express Ports are enabled in the BIOS setup. If for example PCI Express Port 2 is disabled then PCI Express Port 3 will be assigned bus number 2 instead of bus number 3, Port 4 will be assigned bus number 3 and the onboard LAN controller as well as the standard PCI slots will be assigned bus number 4. Furthermore, the respective PCI Express Root Port is hidden if the 70/102

71 corresponding PCI Express Port is disabled. 8.6 PCI Interrupt Routing Map Table 42 PIRQ PCI BUS INT Line ¹ PCI Interrupt Routing Map APIC Mode IRQ VGA Azalia HDA A 16 x x B 17 C 18 D 19 E INTD 20 F INTA 21 G INTB 22 H INTC 23 LAN PATA Native SM Bus AC97 x x x x PCI Interrupt Routing Map (continued) B PCI-EX Root Port 2 x PCI-EX Root PCI-EX Port 3 Port 0 x C E EHCI x x x D UHCI 2 x SATA PCI-EX Root PCI-EX Root Native Port 0 Port 1 A UHCI 1 x Table 43 PIRQ UHCI 0 x PCI-EX Port 1 PCI-EX Port 2 PCI-EX Port 3 x² x³ x4 x5 x³ x4 x5 x² x 4 x 5 x² x³ x 5 x² x³ x4 x F G H Notes ¹ These interrupts are available for external devices/slots on the X1 connector. ² Interrupt used by single function PCI Express devices (INTA). ³ Interrupt used by multifunction PCI Express devices (INTB). 4 Interrupt used by multifunction PCI Express devices (INTC). 5 Interrupt used by multifunction PCI Express devices (INTD). 71/102

72 8.7 PCI Bus Masters The conga X945 supports 4 external PCI Bus Masters. There are no limitations in connecting bus master PCI devices. Note If there are two devices connected to the same PCI REQ/GNT pair and they are transferring data at the same time then the latency time of these shared PCI devices can not be guaranteed. 8.8 I²C Bus There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions. 8.9 SM Bus System Management (SM) bus signals are connected to the Intel I/O Controller Hub 82801GBM (ICH7M) and the SM bus is not intended to be used by off-board nonsystem management devices. For more information about this subject please contact congatec technical support. 72/102

73 9 BIOS Setup Description The following section describes the BIOS setup program. The conga-x945 and conga-xa945 use different BIOS ROM files that are not interchangeable but the BIOS setup programs are identical except for the CPU Configuration Submenus. Both versions of the CPU Configuration Submenus are described within this section. The BIOS setup program can be used to view and change the BIOS settings for the module. Only experienced users should change the default BIOS settings. 9.1 Entering the BIOS Setup Program. The BIOS setup program can be accessed by pressing the <DEL> key during POST Boot Selection Popup The BIOS offers the possibility to access a Boot Selection Popup menu by pressing the <F11> key during POST. If this option is used a message will be displayed during POST stating that the Boot Selection Popup menu has been selected and the menu itself will be displayed immediately after POST thereby allowing the operator to choose the boot device to be used Manufacturer Default Settings Pressing the <End> key repeatedly, immediately after power is initiated will result in the manufacturer default settings being loaded for that boot sequence and only that boot sequence. This is helpful when a previous BIOS setting is no longer desired. If you want to change the BIOS settings, or save the manufacturer default settings, then you must enter the BIOS setup program and use the 'Save and Exit' function. This feature is enabled by default. See setup node in the BIOS Setup Program section Security Settings. 9.2 Setup Menu and Navigation The congatec BIOS setup screen is composed of the menu bar and two main frames. The menu bar is shown below: Note Entries in the option column that are displayed in bold print indicate BIOS default values. Main Advanced Boot Security Power Exit The left frame displays all the options that can be configured in the selected menu. Grayed-out options cannot be configured. Only the blue options can be configured. When an option is selected, it is highlighted in white. The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options and the possible impacts when changing the selected option in the left frame. 73/102

74 The setup program uses a key-based navigation system. Most of the keys can be used at any time while in setup. The table below explains the supported keys: 9.3 Key Description Left/Right Select a setup menu (e.g. Main, Boot, Exit). Up/Down Select a setup item or sub menu. + - Plus/Minus Change the field value of a particular setup item. Tab Select setup fields (e.g. in date and time). F1 Display General Help screen. F2/F3 Change Colors of setup screen. F7 Discard Changes. F9 Load optimal default settings. F10 Save changes and exit setup. ESC Discard changes and exit setup. ENTER Display options of a particular setup item or enter submenu. Main Setup Screen When you first enter the BIOS setup, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. The Main screen reports BIOS, processor, memory and board information and is for configuring the system date and time. Feature Options Description System Time Hour:Minute:Second Specifies the current system time. Note: The time is in 24-hour format. System Date Day of week, month/day/year Specifies the current system date. Note: The date is in month-day-year format. BIOS ID no option Displays the BIOS ID. Processor no option Displays the processor type. CPU Frequency no option Displays CPU frequency. System Memory no option Displays the total amount of system memory. Product Revision no option Displays the hardware revision of the board Serial Number no option Displays the serial number of the board. BC Firmware Rev. no option Displays the revision of the congatec board controller. MAC Address no option Displays the MAC address of the onboard Ethernet controller. Boot Counter no option Displays the number of boot-ups. (max ) Running Time no option Displays the time the board is running [in hours max ]. 74/102

75 9.4 Advanced Setup Select the Advanced tab from the setup menu to enter the Advanced BIOS Setup screen. The menu is used for setting advanced features: Main Advanced Boot Security Power Exit ACPI Configuration PCI Configuration Graphics Configuration CPU Configuration Chipset Configuration I/O Interface Configuration Clock Configuration IDE Configuration USB Configuration Keyboard/Mouse Configuration Remote Access Configuration Hardware Health Configuration Watchdog Configuration 75/102

76 9.4.1 ACPI Configuration Submenu Feature Options Description ACPI Aware O/S No Yes Set this value to allow the system to utilize the Intel ACPI (Advanced Configuration and Power Interface). Set to NO for non ACPI aware operating system like DOS and Windows NT. Set to YES if your OS complies with the ACPI specification (e.g. Windows 2000, XP) ACPI Version Features ACPI v1.0 ACPI v2.0 ACPI v3.0 ACPI version supported by the BIOS ACPI code and tables. System Off Mode G3/Mech Off S5/Soft Off Select the actual power down mode when the system performs a shutdown with a congatec battery system connected. Note: This node is only visible when the system is connected to a congatec battery system. ACPI APIC support Set to enable to include the APIC support table to ACPI. Suspend mode S1 (POS) S3 (STR) Select the state used for ACPI system suspend. Repost Video on S3 Resume No Yes Determines whether to invoke VGA BIOS post on S3 resume (required by some OS to re-initialize graphics). USB Device Wakeup From S3/S4 Enable or disable USB device wakeup from S3 and S4 state. Active Cooling Trip Point 50, 60, 70, 80, 90 C Specifies the temperature threshold at which the ACPI aware OS turns the fan on/off. Passive Cooling Trip Point 50, 60, 70, 80, 90 C Specifies the temperature threshold at which the ACPI aware OS starts/stops CPU clock throttling. Critical Trip Point, 80, 85, 90, 95, 100, 105, 110 C Specifies the temperature threshold at which the ACPI aware OS performs a critical shutdown. Watchdog ACPI Event Shutdown Restart Select the event that is initiated by the watchdog ACPI event. When the watchdog times out a critical but orderly OS shutdown or restart can be performed (see note below). GPE1 Function No Function Lid Switch Determines the functionality of GPE1 (pin 42 of X4 connector). GPE2 Function No Function Sleep Button Determines functionality of GPE2 (pin 89 of X4 connector). Note In ACPI mode it is not possible for a Watchdog ACPI Event handler to directly restart or shutdown the OS. For this reason the congatec BIOS will do one of the following: For Shutdown: An over temperature notification is executed. This causes the OS to shut down in an orderly fashion. For Restart: An ACPI fatal error is reported to the OS. It depends on your particular OS as to how this reported fatal error will be handled when the Restart function is selected. If you are using Windows XP/2000 there is a setting 76/102

77 that can be enabled to ensure that the OS will perform a restart when a fatal error is detected. After a very brief blue-screen the system will restart. You can enable this setting buy going to the System Properties dialog box and choosing the Advanced tab. Once there choose the Settings button for the Startup and Recovery section. This will open the Startup and Recovery dialog box. In this dialog box under System failure there are three check boxes that define what Windows will do when a fatal error has been detected. In order to ensure that the system restarts after a 'Watchdog ACPI Event that is set to 'Restart', you must make sure that the check box for the selection Automatically restart has been checked. If this option is not selected then Windows will remain at a blue-screen after a 'Watchdog ACPI Event that has been configured for 'Restart' has been generated. Below is a Windows screen-shot showing the proper configuration. Win XP/2000 Watchdog ACPI Event restart configuration 77/102