i960 RM/RN I/O Processor

Transcription

1 i960 RM/RN I/O Processor Specification Update January 1999 Notice: The 80960RM/RN may contain design defects or errors known as errata. Characterized errata that may cause 80960RM/RN s behavior to deviate from pubished specifications are documented in this specification update. Order Number:

2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel s website at Copyright Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners. i960 RM/RN I/O Processor Specification Update

3 Contents Revision History... 5 Preface... 6 Summary Table of Changes... 7 Identification Information Errata...11 Specification Changes Specification Clarifications Documentation Changes i960 RM/RN I/O Processor Specification Update 3

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5 Revision History Date Version Description 01/20/ /13/ / Added the following Errata: #7, Data Corruption Occurs when Transfer Data Value Matches the Memory Mapped Register (MMR) Addresses of the DMA Channels. #8, Data Corruption Occurs when Transfer Data Value Matches the Memory Mapped Register (MMR) Addresses of the Application Accelerator Unit. Added the following Specification Changes: #1, Default Value of the Memory Controller s Refresh Frequency Register (RFR). #2, Resetting the Memory Controller s SDRAM Output Buffers during the Power-Fail Sequence. #3, PCI-to-PCI Bridge Configuration Registers: Bridge Subsystem Vendor ID Register (BSVIR) and Bridge Subsystem ID Register (BSIR). Added the following Documentation Change: #3, Section of the i960 RM/RN I/O Processor Developer s Manual. Added the following Specification Clarifications: #1, Hooking up the SDRAM Clock Enable Inputs on the SDRAM DIMM for Non- Battery-Backup Applications #2, Hooking up the SDRAM Clock Enable Outputs (SCKE0 and SCKE1) from the i960 RM/RN I/O Processor to the Clock Enable Inputs on the SDRAM DIMM in a Battery-Backup Application This is the new Specification Update document. It contains all identified errata published prior to this date. i960 RM/RN I/O Processors Specification Update 5

6 Preface Preface As of July, 1996, Intel s Computing Enhancement Group has consolidated available historical device and documentation errata into this new document type called the Specification Update. We have endeavored to include all documented errata in the consolidation process, however, we make no representations or warranties concerning the completeness of the Specification Update. This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents/Related Documents Title Order # i960 RM/RN I/O Processor Developer s Manual RM I/O Processor Data Sheet RN I/O Processor Data Sheet i960 RM/RN I/O Processor Design Guide Nomenclature Errata are design defects or errors. These may cause the Product Name s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification. Note: Errata remain in the specification update throughout the product s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). 6 i960 RM/RN I/O Processors Specification Update

7 Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Product Name product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: Codes Used in Summary Table Stepping Page : Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping. (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping. (Page): Page location of item in this document. Status Doc: Fix: Fixed: NoFix: Eval: Document change or update will be implemented. This erratum is intended to be fixed in a future step of the component. This erratum has been previously fixed. There are no plans to fix this erratum. Plans to fix this erratum are under evaluation. Row Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. i960 RM/RN I/O Processors Specification Update 7

8 Summary Table of Changes Errata No. Steppings A-0 # # Page Status Errata 1 11 NoFix 2 11 NoFix 3 12 NoFix 4 12 NoFix 5 12 NoFix 6 13 NoFix 7 13 Fix 8 15 Fix The ATU Discard Timer Status Bit in ATUCR Gets Set Even Though Delayed Read/Write Completes Before Discard Timer Expires A Target Abort Occurs on the Internal Bus when Target Abort Passing from the Internal Bus to the PCI Buses through the ATUs is Disabled After Initialization, Changing the Configuration Cycle Retry Bit in the EBCR to Retry Configuration Cycles while they are Occurring can Cause Data Corruption A Target Abort from the Internal Bus may be Reported to the PCI Bus, Without the Target Abort Being Returned Secondary Interrupts are Routed to the Core Processor, Rather than the Primary PCI Bus, as their Default Secondary IDSEL Select Register (SISR) Bits are in Reverse Order Data Corruption Occurs when Transfer Data Value Matches the Memory Mapped Register (MMR) Addresses of the DMA Channels Data Corruption Occurs when Transfer Data Value Matches the Memory Mapped Register (MMR) Addresses of the Application Accelerator Unit Specification Changes No. Steppings A-0 # # Page Status Specification Changes 1 16 Fix 2 16 Fix 3 16 Fix Default Value of the Memory Controller s Refresh Frequency Register (RFR) Resetting the Memory Controller s SDRAM Output Buffers during the Power-Fail Sequence PCI-to-PCI Bridge Configuration Registers: Bridge Subsystem Vendor ID Register (BSVIR) and Bridge Subsystem ID Register (BSIR) Specification Clarifications No. Steppings A-0 # # Page Status Specification Clarifications 1 17 Doc 2 17 Doc Hooking up the SDRAM Clock Enable Inputs on the SDRAM DIMM for Non- Battery-Backup Applications Hooking up the SDRAM Clock Enable Outputs (SCKE0 and SCKE1) from the i960 RM/RN I/O Processor to the Clock Enable Inputs on the SDRAM DIMM in a Battery-Backup Application 8 i960 RM/RN I/O Processors Specification Update

9 Summary Table of Changes Documentation Changes No. Document Revision Page Status Documentation Changes Doc Doc Doc Page 1 of 80960RM Schematics and Page 1 of 80960RN Schematics Page 1 of 80960RM Schematics and Page 1 of 80960RN Schematics Section of the i960 RM/RN I/O Processor Developer s Manual i960 RM/RN I/O Processors Specification Update 9

10 Identification Information Identification Information Markings Topside Markings GC80960RM100 SSSSSS MALAY FFFFFFFF-[{SN}] M INTEL 98 GC80960RN100 SSSSSS MALAY FFFFFFFF-[{SN}] M INTEL RM 80960RN Device ID Registers Device and Stepping Processor Device ID Register (PDIDR - 0x1710) PCI-to-PCI Bridge Unit Revision ID (RIDR - 0x1008) Address Translation Unit Revision ID Register (ATURID - 0x1208) i960 Core Processor Device ID (DEVICEID - 0xFF ) 80960RM A x0 0x RN A x0 0x i960 RM/RN I/O Processors Specification Update

11 Errata Errata 1. The ATU Discard Timer Status Bit in ATUCR Gets Set Even Though Delayed Read/Write Completes Before Discard Timer Expires Problem: Implication: Workaround: The ATU Discard Timer Status bit (bit 15, in the Address Translation Unit Configuration Register, local bus address 1288H) is getting set even though the transaction completed correctly. This scenario occurs when a single-word delayed read or write is completing on the PCI bus through either the primary ATU or the secondary ATU at the same time that the discard timer is timing out. This should not affect multi-word transactions, but should occur with all configuration reads and writes that line up with the discard timer time-out. Although the discard timer time-out bit is being set, the transaction is completing properly, so the only implication here is the handling of any actions that occur as a result of the discard timer being set. Software that handles the discard timer status bit, should just reset the ATU Discard Timer Status bit (bit 15, in the Address Translation Unit Configuration Register, local bus address 1288H) in this scenario. The likelihood of seeing the problem is reduced if the timer value is set to Status: NoFix. See the Table Summary Table of Changes on page A Target Abort Occurs on the Internal Bus when Target Abort Passing from the Internal Bus to the PCI Buses through the ATUs is Disabled Problem: Implication: Workaround: If a target abort occurs on the Internal Bus due to an ECC error, and target abort passing from the internal bus to the PCI busses is disabled, the ATU can deadlock when all the following conditions are true: The PCI master must be a 32-bit master The PCI master induces data-to-data wait states A target abort occurs on the internal bus The Primary (bit 0, in the Primary ATU Interrupt Mask Register, local bus address 12BCH) or Secondary (bit 0, in the Secondary ATU Interrupt Mask Register, local bus address 12C0H) ATU ECC Target Abort Enable bit is clear. Under these conditions the relevant ATU will not pass the target abort back to the PCI master, and the ATU will enqueue subsequent read transactions, but will never return data. The discard timer will not rescue this case, since pointers have been corrupted. Always set The Primary ATU ECC Target Abort Enable bit (bit 0, in the Primary Interrupt Mask Register, local bus address 12BCH) and the Secondary ATU ECC Target Abort ENable bit (bit 0, in the Secondary Interrupt Mask Register, local bus address 12C0H) to allow the ATUs to pass the target abort back to the PCI master. Status: NoFix. See the Table Summary Table of Changes on page 7. i960 RM/RN I/O Processors Specification Update 11

12 Errata 3. After Initialization, Changing the Configuration Cycle Retry Bit in the EBCR to Retry Configuration Cycles while they are Occurring can Cause Data Corruption Problem: Implication: Workaround: After initialization, if the Configuration Cycle Retry Bit (bit 2, in the Extended Bridge Configuration Register, local bus address 1040H) is changed to retry configurations cycles at the same time that a configuration read completion is starting on the primary PCI bus, the ATU will return data, but will not dequeue it. Under the above conditions, if another read of the same address were to occur, the old, stale data in the queue would be returned to the master. Do not change the Configuration Cycle Retry Bit (bit 2, in the Extended Bridge Configuration Register, local bus address 1040H) after initialization. Status: NoFix. See the Table Summary Table of Changes on page A Target Abort from the Internal Bus may be Reported to the PCI Bus, Without the Target Abort Being Returned Problem: Implication: Workaround: If a target abort occurs on the internal bus before the primary Memory Enable Bit (bit 1, in the Primary ATU Command Register, local bus address 1204H) is cleared, or the secondary Memory Enable Bit (bit 1, in the Secondary ATU Command Register, local bus address 1298H) is cleared, the target abort will be reported incorrectly in the ATU error registers, when the transaction master aborts on the relevant PCI bus. Furthermore, the transaction will be dequeued. If the memory enables are turned back on, the original target abort will be lost. Also, if enabled, this WILL generate an interrupt to the core. Ensure that the queues in the ATUs are cleared before changing the Memory Enable Bit (bit 1, in the Primary ATU Command Register, local bus address 1204H) or the Memory Enable Bit (bit 1, in the Secondary ATU Command Register, local bus address 1298H) after initialization. Status: NoFix. See the Table Summary Table of Changes on page Secondary Interrupts are Routed to the Core Processor, Rather than the Primary PCI Bus, as their Default Problem: Implication: Workaround: The secondary interrupts (S_INTA#, S_INTB#, S_INTC#, and S_INTD#) are routed to the 80960RM/RN core processor as their default. They should be routed to the primary PCI bus as their default. When booting in configuration mode 0, cards located on the secondary PCI bus will have their interrupts routed to the i960 core processor and may not function correctly in the system. Boot the processor in Mode 3 (Default Mode), and set the S_INTA# Select Bit, S_INTB# Select Bit, S_INTC# Select Bit, and S_INTD# Select Bit (Bits 3:0, in the PCI Interrupt Routing Select Register, local bus address 1050H) in the initialization software. Then make sure to clear the Configuration Cycle Retry Bit (bit 2, in the Extended Bridge Control Register, local bus address 1040H) to allow the bridge and the ATU to accept configuration cycles. If the system must boot in mode 0, these bits can be modified by an external agent on the PCI bus by using PCI configuration cycles. Status: NoFix. See the Table Summary Table of Changes on page i960 RM/RN I/O Processors Specification Update

13 Errata 6. Secondary IDSEL Select Register (SISR) Bits are in Reverse Order Problem: The bits in the Secondary IDSEL Select Register (SISR) are in reverse order Refer to Table 1 SISR Bit Mapping on page 13 for the bit descriptions. Table 1. SISR Bit Mapping Bit Number Bit 09 Bit 08 Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00 Description AD16 IDSEL Disable AD17 IDSEL Disable AD18 IDSEL Disable AD19 IDSEL Disable AD20 IDSEL Disable AD21 IDSEL Disable AD22 IDSEL Disable AD23 IDSEL Disable AD24 IDSEL Disable AD25 IDSEL Disable Implication: Workaround: When private devices are being used on the secondary side and the SISR is programmed without taking the bit reversal into account, the private devices may not be hidden from the host. In addition, public devices may be hidden from the host. Program the SISR with the new bit mapping as described above. Status: NoFix. See the Table Summary Table of Changes on page Data Corruption Occurs when Transfer Data Value Matches the Memory Mapped Register (MMR) Addresses of the DMA Channels Problem: This problem appears across all 3 DMA channels: DMA Ch-0, Ch-1, and Ch-2. If the transfer data value falls within the MMR address range of the active DMA channel (1400H - 143FH for Ch-0, 1440H - 147FH for Ch-1, and 1480H - 14FFH for Ch-2), data corruption will occur. Examples on page 14 describe the error condition. i960 RM/RN I/O Processors Specification Update 13

14 Errata Assumption: DMA channel 0 is used to transfer data from PCI to IOP memory. Single Transaction on the Internal Bus Case 1 Case 2 RM/RN Internal Bus RM/RN Internal Bus H H These data values are corrupted in IOP memory H 5A5A5A5AH No data corruption 256-byte Queue 256-byte Queue Primary PCI Bus Primary PCI Bus Case 3: Two Transactions on the Internal Bus (one disconnect) RM/RN Internal Bus Case 4: Three Transactions on the Internal Bus (two disconnects) RM/RN Internal Bus H 5A5A5A5AH H 5A5A5A5AH Queue data to be transferred following disconnect and reacquisition 1st disconnect and reacquisition H H These data values are corrupted in IOP memory. These data values are corrupted in IOP memory H H 2nd disconnect and reacquisition H H Primary PCI Bus Primary PCI Bus 14 i960 RM/RN I/O Processors Specification Update

15 Errata Implication: Workaround: Status: Data corruption results when the data value matches the MMR address range of the active DMA channel. There are two possible workarounds for this errata: Use the Primary Address Translation Unit (PATU) to transfer data from Primary PCI to IOP memory and Secondary Address Translation Unit (SATU) to transfer data from Secondary PCI to IOP memory. Configure the Memory Controller Unit to execute in 32-bit mode. For further information, refer to Section on page of the i960 RM/RN I/O Processor Developer s Manual and to Table 4 in the 80960RM/RN I/O processor datasheets. Fix. A fix for this errata is planned for the B-0 stepping. 8. Data Corruption Occurs when Transfer Data Value Matches the Memory Mapped Register (MMR) Addresses of the Application Accelerator Unit Problem: Implication: Workaround: Status: If the transfer data value falls within the MMR address range of the Application Accelerator Unit (1800H - 18FFH), data corruption will occur. Data corruption results when the data value matches the MMR address range of the Application Accelerator Unit. There are two possible workarounds for this errata: Compute the OR Parity calculation through software by using the i960 JT processor. Configure the Memory Controller Unit to execute in 32-bit mode. For further information, refer to Section on page of the i960 RM/RN I/O Processor Developer s Manual and to Table 4 in the 80960RM/RN I/O processor datasheets. Fix. A fix for this errata is planned for the B-0 stepping. i960 RM/RN I/O Processors Specification Update 15

16 Specification Changes Specification Changes 1. Default Value of the Memory Controller s Refresh Frequency Register (RFR) Issue: Status: The Refresh Frequency Register (RFR) will default to the value 00H. The desired value of the RFR will need to be specified during the SDRAM initialization sequence/routine. Fix. This change is planned for the B-0 stepping. 2. Resetting the Memory Controller s SDRAM Output Buffers during the Power-Fail Sequence Issue: Status: SDRAM output buffers will be reset to the default value (low-drive strength) after the power-fail sequence has executed with the current buffer strength configuration. Fix. This change is planned for the B-0 stepping. 3. PCI-to-PCI Bridge Configuration Registers: Bridge Subsystem Vendor ID Register (BSVIR) and Bridge Subsystem ID Register (BSIR) Issue: Status: To guarantee compliance with the PCI-to-PCI Bridge Architecture Specification Rev 1.0, the Bridge Subsystem Vendor ID Register (BSVIR@PCI configuration offset 34H) and the Bridge Subsystem ID Register (BSIR@PCI configuration offset 36H) will be specified to be reserved in the configuration address space. Configuration software should therefore not write to these reserved locations. Fix. This change is planned for the B-0 stepping. 16 i960 RM/RN I/O Processors Specification Update

17 Specification Clarifications Specification Clarifications 1. Hooking up the SDRAM Clock Enable Inputs on the SDRAM DIMM for Non- Battery-Backup Applications Problem: During the power-up reset sequence, the SDRAM devices occasionally enter a pseudo, self-refresh mode. This causes a lock-up condition on the SDRAM device. Normal operation of the SDRAM device which includes the SDRAM initialization sequence does not clear the lock-up condition. Workaround: Tie the Clock Enable Inputs on the SDRAM DIMM to V CC. 2. Hooking up the SDRAM Clock Enable Outputs (SCKE0 and SCKE1) from the i960 RM/RN I/O Processor to the Clock Enable Inputs on the SDRAM DIMM in a Battery-Backup Application Problem: Workaround: During the power-up reset sequence, the SDRAM devices occasionally enter a pseudo, self-refresh mode. This causes a lock-up condition on the SDRAM device. Normal operation of the SDRAM device which includes the SDRAM initialization sequence does not clear the lock-up condition. Ensure that the Clock Enable Inputs to the SDRAM DIMM are held low during power-up. This is accomplished as shown in the following circuit schematics (Sheet RM schematics and Sheet RN schematics in i960 RM/RN I/O Processor Design Guide). i960 RM/RN I/O Processors Specification Update 17

18 Specification Clarifications A B C D E F G H RAM3V {01,04,10} SDRAM {03,05} R601 1/10W 5% 1K SDRAM-DIMM168P SDRAM-DIMM168P GND1 GND5 GND1 GND5 DQ DQ0 86 NC4 44 DQ32 DQ32 CKE0 SCKE0 {03,10} DQ SCE0# DQ SCE1# DQ1 CS2 DQ33 CS3 DQ SM2 DQ SM6 DQ2 M2 DQ34 M6 DQ DQ3 M3 SM3 DQ35 89 DQ35 M7 SM VCC1 NC5 VCC1 NC5 DQ DQ DQ4 VCC6 DQ36 VCC5 DQ5 8 DQ NC6 DQ37 DQ37 NC6 +3V DQ DQ DQ6 NC7 DQ38 NC7 DQ SCB2 DQ SCB6 TL7702BCD DQ7 CB2 DQ39 CB SENSE DQ DQ8 CB3 SCB3 DQ40 95 DQ40 CB7 SCB RESIN RESET GND2 GND6 GND2 GND6 3 DQ DQ16 DQ DQ48 CT RESET SCKE0 {03,10} DQ9 DQ16 DQ41 DQ REF DQ10 14 DQ10 DQ17 56 DQ17 DQ42 DQ42 DQ DQ49 DQ DQ18 DQ DQ50 U601 DQ11 DQ18 DQ43 DQ50 DQ DQ19 DQ DQ51 DQ12 DQ19 DQ44 DQ51 DQ13 17 DQ13 VCC7 59 DQ DQ45 VCC DQ DQ52 VCC2 DQ20 VCC2 DQ52 DQ14 19 DQ NC8 61 DQ46 DQ46 NC8 145 DQ DQ DQ15 NC9 DQ47 NC9 SCB SCB CB0 CKE1 SCKE1 {03,10} CB4 NC10 +3V SCB1 22 CB1 GND7 64 SCB5 106 CB5 GND DQ DQ53 GND3 DQ21 GND3 DQ53 TL7702BCD DQ DQ54 7 NC1 DQ22 NC1 DQ54 SENSE NC2 67 DQ23 NC2 151 DQ55 DQ23 DQ55 RESIN RESET VCC3 GND8 VCC3 GND8 CT RESET SCKE1 {03,10} SWE# DQ24 SCAS# DQ56 1 WE DQ24 CAS DQ56 REF SM0 28 M0 70 DQ25 SM4 112 M4 154 DQ57 DQ25 DQ57 U602 SM DQ26 SM DQ58 M1 DQ26 M5 DQ58 SCE0# DQ27 SCE1# DQ59 CS0 DQ27 CS1 DQ59 31 NC3 73 SRAS# VCC8 RAS VCC DQ DQ60 GND4 DQ28 GND4 DQ60 SA DQ29 SA DQ61 A0 DQ29 A1 DQ61 SA2 34 A2 76 DQ30 SA3 118 A3 160 DQ62 DQ30 DQ62 SA DQ31 SA DQ63 A4 DQ31 A5 DQ63 SA SA A6 GND9 A7 GND9 SA8 37 A A9 163 CLK2 SA9 DCLK2 {03} CLK3 DCLK3 {03} SA SBA A10 NC10 BA0 NC11 SBA SA BA1 NC11 A11 SA0 40 VCC4 SDA 82 SDA {03,07} 124 VCC4 SA VCC5 SCL SCL {03,07} DCLK1 {03} CLK1 SA2 42 CLK DCLK0 {03} VCC9 NC4 VCC8 168 A B C D E F G H uF CAP C uF CAP C601 R602 1/10W 5% 1K J5 J uF CAP C uF CAP C602 C CYCLONE MICROSYSTEMS Title: 80960RM 25 SCIENCE PARK Name: SDRAM 168-PIN DIMM REV NEW HAVEN, CT Date: 1/11/99 Sheet 6 of i960 RM/RN I/O Processors Specification Update

19 Specification Clarifications A B C D E F G H RAM3V {01,04,11} SDRAM {03,05} R601 1/10W 5% 1K SDRAM-DIMM168P SDRAM-DIMM168P GND1 GND5 GND1 GND5 DQ DQ0 86 NC4 44 DQ32 DQ32 CKE0 SCKE0 {03,11} DQ SCE0# DQ SCE1# DQ1 CS2 DQ33 CS3 DQ SM2 DQ SM6 DQ2 M2 DQ34 M6 DQ DQ3 M3 SM3 DQ35 89 DQ35 M7 SM7 +3V VCC1 NC5 VCC1 NC5 TL7702BCD DQ DQ DQ4 VCC6 DQ36 VCC5 7 SENSE DQ DQ5 NC6 50 DQ37 DQ37 NC RESIN RESET DQ DQ DQ6 NC7 DQ38 NC7 3 CT RESET SCKE0 {03,11} DQ SCB2 DQ SCB6 DQ7 CB2 DQ39 CB6 1 REF DQ CB7 137 DQ8 CB3 SCB3 DQ40 95 DQ40 SCB7 U GND2 GND6 GND2 GND6 DQ DQ16 DQ DQ48 DQ9 DQ16 DQ41 DQ48 DQ10 14 DQ10 DQ17 56 DQ17 DQ42 98 DQ42 DQ DQ49 DQ DQ18 DQ DQ50 DQ11 DQ18 DQ43 DQ50 DQ DQ19 DQ DQ51 DQ12 DQ19 DQ44 DQ51 DQ13 17 DQ13 VCC7 59 DQ DQ45 VCC DQ DQ52 VCC2 DQ20 VCC2 DQ52 +3V DQ14 19 DQ NC8 61 DQ46 DQ46 NC8 145 DQ DQ TL7702BCD DQ15 NC9 DQ47 NC9 7 SCB SCB SENSE CB0 CKE1 SCKE1 {03,11} CB4 NC RESIN RESET SCB1 CB1 64 CB5 148 GND7 SCB5 GND DQ DQ53 CT RESET SCKE1 {03,11} GND3 DQ21 GND3 DQ DQ DQ54 REF NC1 DQ22 NC1 DQ54 U NC NC2 151 DQ23 DQ23 DQ55 DQ VCC3 GND8 VCC3 GND8 SWE# DQ24 SCAS# DQ56 WE DQ24 CAS DQ56 SM0 28 M0 112 DQ25 70 DQ25 SM4 M4 DQ DQ57 SM DQ26 SM DQ58 M1 DQ26 M5 DQ58 SCE0# DQ27 SCE1# DQ59 CS0 DQ27 CS1 DQ59 31 NC3 VCC8 73 SRAS# 115 RAS VCC DQ DQ60 GND4 DQ28 GND4 DQ60 SA DQ29 SA DQ61 A0 DQ29 A1 DQ61 SA2 34 A2 76 DQ30 SA3 118 DQ30 A3 DQ DQ62 SA DQ31 SA DQ63 A4 DQ31 A5 DQ63 SA SA A6 GND9 A7 GND9 SA8 37 A8 CLK A9 CLK3 163 DCLK2 {03} SA9 DCLK3 {03} SA SBA A10 NC10 BA0 NC11 SBA SA BA1 NC11 A11 SA0 40 VCC4 SDA 82 SDA {03,07} 124 VCC4 SA VCC5 SCL SCL {03,07} DCLK1 {03} CLK1 SA2 42 CLK DCLK0 {03} NC4 168 VCC9 VCC8 A B C D E F G H uF CAP C uF CAP C601 R602 1/10W 5% 1K J5 J5 C uF CAP C uF CAP C602 CYCLONE MICROSYSTEMS Title: 80960RN 25 SCIENCE PARK Name: SDRAM 168-PIN DIMM REV NEW HAVEN, CT Date: 1/11/99 Sheet 6 of 11 i960 RM/RN I/O Processors Specification Update 19

20 Documentation Changes Documentation Changes 1. Page 1 of 80960RM Schematics and Page 1 of 80960RN Schematics Issue: FETs Q2 and Q3 have had pinout changes as shown below. Affected Docs: i960 RM/RN I/O Processor Design Guide. 20 i960 RM/RN I/O Processors Specification Update

21 Documentation Changes 2. Page 1 of 80960RM Schematics and Page 1 of 80960RN Schematics Issue: The fan connector, J13, has been changed by the manufacturer as shown below. Affected Docs: i960 RM/RN I/O Processor Design Guide. 3. Section of the i960 RM/RN I/O Processor Developer s Manual Issue: The last sentence of the third paragraph has been modified as follows: Old: Logical Memory Mask register (LMMSK). New: Logical Memory Mask register (LMMR). Affected Docs: i960 RM/RN I/O Processor Developer s Manual. i960 RM/RN I/O Processors Specification Update 21

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