Uniprocessor Computer Architecture Example: Cray T3E

Transcription

1 Chapter 2: Computer-System Structures MP Example: Intel Pentium Pro Quad Lab 1 is available online Last lecture: why study operating systems? Purpose of this lecture: general knowledge of the structure of a computer system and understanding technology trends Key issues in a computer system General System Architecture (CPU, $s, MM, disk, bus, IO devices and controllers), Uni vs. Multi Processors I/O Structure (IO interrupts, IO methods, HW support, e.g., DMA) Storage Structure (CPU regs, $, MM, disk) Storage Hierarchy (why? expensivecheap; smalllarge) Hardware Protection (user/system, IO protection, Mem protection) Interrupt controller CPU Bus interface 256-KB L 2 $ P-Pro module P-Pro bus (64-bit data, 36-bit addr ess, 66 MHz) PCI I/O cards PCI bridge PCI bus PCI bridge Multiprocessor P-Pro module P-Pro module Memory controller MIU 1-, 2-, or 4-way interleaved DRAM All coherence and multiprocessing glue in processor module PCI bus Highly integrated, targeted at high volume Hmm this looks like a Computer System? Example: SUN Enterprise Algorithms The System Programming Languages P $ P $ CPU/mem cards $ 2 $ 2 Mem ctrl Bus interface/switch Gigaplane bus (256 data, 41 addr ess, 83 MHz) Compiler Hardware Technology, Architecture Runtime, Operating System bt, SCSI Bus interface SBUS SBUS SBUS 2 FiberChannel I/O cards Figure by courtesy of Anant Agarwal, MIT 16 cards of either type: processors + memory, or I/O All memory accessed over bus, so symmetric multiproc. (SMP) Higher bandwidth, higher latency bus Uniprocessor Computer Architecture Example: Cray T3E External I/O P $ Mem Mem ctrl and NI XY Switch Z Multiprocessor system Scale up to 1024 processors, 480MB/s links 1

2 Let s look at trends, 1 st Technology Trends Transistor Count Growth Rate,000,000 Performance Supercomputers 10 Mainframes Microprocessors Minicomputers The natural building block for multiprocessors is now also about the fastest! Transistors 10,000,000,000,000 R00 Pentium i80386 i80286 R2000 R3000 i ,000 i8080 i8008 i million transistors on chip by early 2000 s A.D. Transistor count grows much faster than clock rate - 40% per year, order of magnitude more contribution in 2 decades General Technology Trends Microprocessor performance increases 50% - % per year Transistor count doubles every 3 years DRAM size quadruples every 3 years Huge investment per generation is carried by huge commodity market Sun MIPS M/120 MIPS M2000 IBM RS HP Integer Not that single-processor performance is plateauing, but that parallelism is a natural way to improve it. 750 DEC alpha FP Architectural Trends: Bus-based MPs Micro on a chip makes it natural to connect many to shared memory dominates server and enterprise market, moving down to desktop Faster processors began to saturate bus, then bus technology advanced today, range of sizes for bus-based systems, desktop to large servers Number of processors Sequent B2 Sequent B8000 Symmetry81 Symmetry21 Power Sun SC2000 SGI Challenge SE60 SE10 SS0 CRAY CS6400 SE70 SC2000E SGI PowerChallenge/XL AS8400 SE30 SS0E Sun E00 Sun E6000 SS690MP 140 AS2 HP K400 P-Pro SGI PowerSeries SS690MP 120 SS10 SS Clock Frequency Growth Rate Clock rate (MHz) 30% per year R00 Pentium 10 i8086 i80286 i80386 i i8008 i Shared bus bandwidth (MB/s),000 10,000 Bus Bandwidth SS690MP 120 SS690MP 140 Symmetry81/21 SGI PowerSeries SGI Challenge Power SGI PowerCh XL SC2000 SS0 SS10/ SE10/ SE60 Sun E00 Sun E6000 AS8400 CS6400 HPK400 SC2000E AS2 P-Pro SS0E SS20 SE70/SE30 Sequent B2 Sequent B

3 Phases in VLSI Generation Common Functions of Interrupts,000,000 Bit-level parallelism Instruction-level Thread-level (?) Transistors 10,000,000 R00,000 Pentium i80386 i80286,000 R3000 R2000 i ,000 i8080 i8008 i Interrupt transfers control to the interrupt service routine generally, through the interrupt vector, which contains the addresses of all the service routines. Interrupt architecture must save the address of the interrupted instruction. Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt. A trap is a software-generated interrupt caused either by an error or a user request. An operating system is interrupt driven. How good is instruction-level parallelism? Thread-level needed in microprocessors? Economics Interrupt Handling Commodity microprocessors not only fast but CHEAP Development cost is tens of millions of dollars (5- typical) BUT, many more are sold compared to supercomputers Crucial to take advantage of the investment, and use the commodity building block Exotic parallel architectures no more than special-purpose Multiprocessors being pushed by software vendors (e.g. database) as well as hardware vendors Standardization by Intel makes small, bus-based SMPs commodity The operating system preserves the state of the CPU by storing registers and the program counter. Determines which type of interrupt has occurred: polling vectored interrupt system Separate segments of code determine what action should be taken for each type of interrupt Desktop: few smaller processors versus one larger one? Multiprocessor on a chip is here. Computer-System Operation Interrupt Time Line For a Single Process Doing Output I/O devices and the CPU can execute concurrently. Each device controller is in charge of a particular device type. Each device controller has a local buffer. CPU moves data from/to main memory to/from local buffers I/O is from the device to local buffer of controller. Device controller informs CPU that it has finished its operation by causing an interrupt. 3

4 I/O Structure Direct Memory Access Structure After I/O starts, control returns to user program only upon I/O completion. Wait instruction idles the CPU until the next interrupt Wait loop (contention for memory access). At most one I/O request is outstanding at a time, no simultaneous I/O processing. After I/O starts, control returns to user program without waiting for I/O completion. System call request to the operating system to allow user to wait for I/O completion. Device-status table contains entry for each I/O device indicating its type, address, and state. Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt. Used for high-speed I/O devices able to transmit information at close to memory speeds. Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention. Only one interrupt is generated per block, rather than the one interrupt per byte. Two I/O Methods Storage Structure Synchronous Asynchronous Main memory only large storage media that the CPU can access directly. Secondary storage extension of main memory that provides large nonvolatile storage capacity. Magnetic disks rigid metal or glass platters covered with magnetic recording material Disk surface is logically divided into tracks, which are subdivided into sectors. The disk controller determines the logical interaction between the device and the computer. Device-Status Table Moving-Head Disk Mechanism 4

5 Storage Hierarchy Migration of A From Disk to Register Storage systems organized in hierarchy. Speed Cost Volatility Caching copying information into faster storage system; main memory can be viewed as a last cache for secondary storage. Storage-Device Hierarchy Hardware Protection Dual-Mode Operation I/O Protection Memory Protection CPU Protection Caching Dual-Mode Operation Use of high-speed memory to hold recently-accessed data. Requires a cache management policy. Caching introduces another level in storage hierarchy. This requires data that is simultaneously stored in more than one level to be consistent. Caching is typically transparent to the OS Sharing system resources requires operating system to ensure that an incorrect program cannot cause other programs to execute incorrectly. Provide hardware support to differentiate between at least two modes of operations. 1. User mode execution done on behalf of a user. 2. Monitor mode (also kernel mode or system mode) execution done on behalf of operating system. 5

6 Dual-Mode Operation (Cont.) Memory Protection Mode bit added to computer hardware to indicate the current mode: monitor (0) or user (1). When an interrupt or fault occurs hardware switches to monitor mode. Interrupt/fault monitor set user mode user Must provide memory protection at least for the interrupt vector and the interrupt service routines. In order to have memory protection, add two registers that determine the range of legal addresses a program may access: Base register holds the smallest legal physical memory address. Limit register contains the size of the range Memory outside the defined range is protected. Privileged instructions can be issued only in monitor mode. I/O Protection Use of A Base and Limit Register All I/O instructions are privileged instructions. Must ensure that a user program could never gain control of the computer in monitor mode (I.e., a user program that, as part of its execution, stores a new address in the interrupt vector). Use of A System Call to Perform I/O Hardware Address Protection 6

7 Hardware Protection Local Area Network Structure When executing in monitor mode, the operating system has unrestricted access to both monitor and user s memory. The load instructions for the base and limit registers are privileged instructions. CPU Protection Wide Area Network Structure Timer interrupts computer after specified period to ensure operating system maintains control. Timer is decremented every clock tick. When timer reaches the value 0, an interrupt occurs. Timer commonly used to implement time sharing. Time also used to compute the current time. Load-timer is a privileged instruction. Network Structure Local Area Networks (LAN) Wide Area Networks (WAN) 7