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5 :32.20*20.50*10.50mm 23dBm :-104dBm :127dB Sleep mode:<2.0µa RX mode:29ma TX EM351/EM357: 128K/192K bytes Flash;12K bytes RAM STM32W:128K bytes Flash; 8K bytes RAM 1 x 1 x TW 1 x SP/ 2 C PCB board, good ESD/EMC protection ability. SM FCC certified:fcc D:46RY12M02

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7 2 1.6 [1] EEE Std EEE Standard for nformation technology - Part 15.4 Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [2] ZigBee Specification. ZigBee Document r17, ctober 19, 2007

8 Figure 2-1. XTAL (Crystal Frequency 24MHz) Cortex M3 Core Data Program Power Management -QPSK Modem RAM 12kB Flash 192kB SP TW EEE MAC Accelerator ARM CRTEX-M3 CPU with NVC and MPU Timers UART 2.4GHz Radio Encryption Accelerator GP registers Antenna PA & LNA Matching Network

9 Parameters Min Max Power supply range(vcc) 2.1V 3.6V Pin working voltage range (except ADC pin) -0.3V VDD_PADS+0.3 ADC pin working voltage range -0.3V 2.0V Max drive current data for all / Max RX RF levle 40 ma +10 dbm Parameter Range Unit, VCC 2.1 to 3.6 V RX current 29 ma TX current(@20dbm) 170 ma TX current(@23dbm) 230 ma Sleeping current <2.0 μa TX power -9 to +23 dbm

10 Parameter Condition Range Unit 2400~ MHz 16 0B~1A Hex 5 MHz -9 to +23 dbm Packct Loss 1% -104 dbm 250 kbps For unbalanced output 50 Ω Parameter Condition Range Unit 192KB bytes 12KB bytes 24 MHz Parameter Condition Range Unit bps 12/4096 Bits/µs >1 MΩ 1.2 V 0 - VREF V 400 KHz (Logical 0) -8/ 4 ma 0 ~ 0.18*VCC V (Logical 1) -8/ 4 ma 0.82*VCC ~ VCC V KHz

11 Parameter Value Remark Size 32.2 * 20.5 * 10.5mm Weight 4.0g Working temp. -40 C to +85 C perating Relative Humidity Range <95% 3.3. Picture 3-7. Size Picture 3-8. Package

12 7 Picture 3-9. Attention:PN1 is marked based on white point The PN next to the dot is PN1

13 8 Figure Pin instruction Module Pin No. QFN48 Pin No. Signal Direction Description 1 3.3V - DC3.3V supply 2 3.3V - DC3.3V supply PA1 / Digital / TM2_CH3 SC2SDA SC2MS / PA2 / Digital / TM2_CH4 SC2SCL SC2SCLK / Timer 2 channel 3 output Disable remap with TM2_R[6] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[7:4] Timer 2 channel 3 input. Disable remap with TM2_R[6]. TW data of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with TM2_R[6] Select TW with SC2_MDE Select alternate open-drain output function with GP_PACFGL[7:4] SP slave data out of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with TM2_R[6] Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE Select alternate output function with GP_PACFGL[7:4] SP master data in of Serial Controller 2 Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE Timer 2 channel 4 output Disable remap with TM2_R[7] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[11:8] Timer 2 channel 4 input. Disable remap with TM2_R[7]. TW clock of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with TM2_R[7] Select TW with SC2_MDE Select alternate open-drain output function with GP_PACFGL[11:8] SP master clock of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with TM2_R[7] Enable master with SC2_SPCFG[4] Select SP with SC2_MDE Select alternate output function with GP_PACFGL[11:8] PB4 / Digital / TM2_CH4 SP slave clock of Serial Controller 2 Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE Timer 2 channel 4 output Enable remap with TM2_R[7] Enable timer output in TM2_CCER Select alternate output function with GP_PBCFGH[3:0]

14 9 Module Pin No. QFN48 Pin No Signal Direction Description Timer 2 channel 4 input. Enable remap with TM2_R[7]. UART_RTS UART RTS handshake of Serial Controller 1 Either disable timer output in TM2_CCER or disable remap with TM2_R[7] Enable with SC1_UARTCFG[5] Select UART with SC1_MDE Select alternate output function with GP_PBCFGH[3:0] SC1nSSEL SP slave select of Serial Controller 1 Enable slave with SC1_SPCFG[4] Select SP with SC1_MDE PA0 / Digital / Timer 2 channel 1 output Disable remap with TM2_R[4] TM2_CH1 Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[3:0] Timer 2 channel 1 input. Disable remap with TM2_R[4]. SP master data out of Serial Controller 2 Either disable timer output in TM2_CCER or enable remap with TM2_R[4] Enable master with SC2_SPCFG[4] Select SP with SC2MS SC2_MDE Select alternate output function with GP_PACFGL[3:0] SP slave data in of Serial Controller 2 Enable slave with SC2_SPCFG[4] Select SP with SC2_MDE PC1 / Digital / ADC3 Analog ADC nput 3 Enable analog function with GP_PCCFGL[7:4] Serial Wire utput asynchronous trace output to debugger SW Select asynchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GP_PCCFGL[7:4] Synchronous CPU trace data bit 0 Select 1-, 2- or 4-wire TRACEDA synchronous trace interface in ARM core Enable trace TA0 interface in ARM core Select alternate output function with GP_PCCFGL[7:4] PB3 / Digital / Timer 2 channel 3 output Enable remap with TM2_R[6] TM2_CH3 Enable timer output in TM2_CCER Select alternate output function with GP_PBCFGL[15:12] Timer 2 channel 3 input. Enable remap with TM2_R[6]. UART_CTS UART CTS handshake of Serial Controller 1 Enable with SC1_UARTCFG[5] Select UART with SC1_MDE SP master clock of Serial Controller 1 Either disable timer SC1SCLK output in TM2_CCER or disable remap with TM2_R[6] Enable master with SC1_SPCFG[4] Select SP with SC1_MDE Select alternate output function with

15 10 Module Pin No. QFN48 Pin No Signal Direction Description GP_PBCFGL[15:12] SP slave clock of Serial Controller 1 Enable slave with SC1_SPCFG[4] Select SP with SC1_MDE PA5 / Digital / ADC5 Analog ADC nput 5. Select analog function with GP_PACFGH[7:4]. Data signal of Packet Trace nterface (PT). Disable trace PT_DATA interface in ARM core. Select alternate output function with GP_PACFGH[7:4]. nbtm Embedded serial bootloader activation out of reset. Signal is DE active during and immediately after a reset on NRST. Synchronous CPU trace data bit 3. Select 4-wire TRACEDA synchronous trace interface in ARM core. Enable trace TA3 interface in ARM core. Select alternate output function with GP_PACFGH[7:4] PA4 / Digital / ADC4 Analog ADC nput 4. Select analog function with GP_PACFGH[3:0]. Frame signal of Packet Trace nterface (PT). Disable trace PT_EN interface in ARM core. Select alternate output function with GP_PACFGH[3:0]. Synchronous CPU trace data bit 2. Select 4-wire TRACEDA synchronous trace interface in ARM core. Enable trace TA2 interface in ARM core. Select alternate output function with GP_PACFGH[3:0]. PC7 / Digital / SC32A / khz crystal oscillator. Select analog function with GP_PCCFGH[15:12] SC32_EX T Digital 32 khz clock input source PC6 / Digital / SC32B / khz crystal oscillator Select analog function with GP_PCCFGH[11:8] ntx_act nverted TX_ACTVE signal (see PC5) Select alternate output VE function with GP_PCCFGH[11:8] PB1 / Digital / SP slave data out of Serial Controller 1 Either disable timer SC1MS output in TM2_CCER or disable remap with TM2_R[4] Select SP with SC1_MDE Select slave with SC1_SPCR Select alternate output function with GP_PBCFGL[7:4] SP master data out of Serial Controller 1 Either disable timer SC1MS output in TM2_CCER or disable remap with TM2_R[4] Select SP with SC1_MDE Select master with SC1_SPCR

16 11 Module Pin No. QFN48 Pin No Signal Direction Description SC1SDA SC1TXD TM2_CH1 / PB0 / Digital / VREF VREF Analog Analog Select alternate output function with GP_PBCFGL[7:4] TW data of Serial Controller 1 Either disable timer output in TM2_CCER, or disable remap with TM2_R[4] Select TW with SC1_MDE Select alternate open-drain output function with GP_PBCFGL[7:4] UART transmit data of Serial Controller 1 Either disable timer output in TM2_CCER or disable remap with TM2_R[4] Select UART with SC1_MDE Select alternate output function with GP_PBCFGL[7:4] Timer 2 channel 1 output Enable remap with TM2_R[4] Enable timer output in TM2_CCER Select alternate output function with GP_PACFGL[7:4] Timer 2 channel 1 input. Disable remap with TM2_R[4]. ADC reference output. Enable analog function with GP_PBCFGL[3:0]. ADC reference input. Enable analog function with GP_PBCFGL[3:0]. Enable reference output with an ST system function. RQA External interrupt source A. TRACECLK Synchronous CPU trace clock. Enable trace interface in ARM core. Select alternate output function with GP_PBCFGL[3:0]. TM1CLK Timer 1 external clock input. TM2MSK Timer 2 external clock mask input NRESET Active low chip reset (internal pull-up) PB2 / Digital / SC1MS SC1MS SC1SCL SC1RXD TM2_CH2 / SP master data in of Serial Controller 1 Select SP with SC1_MDE Select master with SC1_SPCR SP slave data in of Serial Controller 1 Select SP with SC1_MDE Select slave with SC1_SPCR TW clock of Serial Controller 1 Either disable timer output in TM2_CCER, or disable remap with TM2_R[5] Select TW with SC1_MDE Select alternate open-drain output function with GP_PBCFGL[11:8] UART receive data of Serial Controller 1 Select UART with SC1_MDE Timer 2 channel 2 output Enable remap with TM2_R[5] Enable timer output in TM2_CCER Select alternate output function with GP_PBCFGL[11:8] Timer 2 channel 2 input. Enable remap with TM2_R[5].

17 12 Module Pin No. QFN48 Pin No. Signal Direction Description 17 GND - Ground 18 GND - Ground SWCLK JTCK / Serial Wire clock input/output with debugger Selected when in Serial Wire mode (see JTMS description, Pin 35) JTAG clock input from debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 35) nternal pull-down is enabled PC2 / Digital / Enable with GP_DBGCFG[5] JTD SW PC3 JTD / JTAG data out to debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 35) Serial Wire utput asynchronous trace output to debugger Select asynchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GP_PCCFGL[11:8] Enable Serial Wire mode (see JTMS description, Pin 35) nternal pull-up is enabled Digital / Either Enable with GP_DBGCFG[5], or enable Serial Wire mode (see JTMS description) JTAG data in from debugger Selected when in JTAG mode (default mode, see JTMS description, Pin 35) nternal pull-up is enabled PC4 / Digital / Enable with GP_DBGCFG[5] JTMS SWD PC0 JRST / / High current JTAG mode select from debugger Selected when in JTAG mode (default mode) JTAG mode is enabled after power-up or by forcing NRST low Select Serial Wire mode using the ARM-defined protocol through a debugger nternal pull-up is enabled Serial Wire bidirectional data to/from debugger Enable Serial Wire mode (see JTMS description) Select Serial Wire mode using the ARM-defined protocol through a debugger nternal pull-up is enabled Digital / Either enable with GP_DBGCFG[5], or enable Serial Wire mode (see JTMS description, Pin 35) and disable TRACEDATA1 JTAG reset input from debugger Selected when in JTAG mode (default mode, see JTMS description) and TRACEDATA1 is disabled nternal pull-up is enabled RQD (1) Default external interrupt source D TRACEDA TA1 Synchronous CPU trace data bit 1 Select 2- or 4-wire synchronous trace interface in ARM core Enable trace interface in ARM core Select alternate output function with GP_PCCFGL[3:0]

18 13 Module Pin No. QFN48 Pin No Signal Direction Description PB7 ADC2 / High current Analog Digital / ADC nput 2 Enable analog function with GP_PBCFGH[15:12] RQC (1) Default external interrupt source C TM1_CH2 PB6 ADC1 / High current Analog Timer 1 channel 2 output Enable timer output in TM1_CCER Select alternate output function with GP_PBCFGH[15:12] Timer 1 channel 2 input (Cannot be remapped) Digital / ADC nput 1 Enable analog function with GP_PBCFGH[11:8] RQB External interrupt source B TM1_CH1 PB5 / Digital / Timer 1 channel 1 output Enable timer output in TM1_CCER Select alternate output function with GP_PBCFGH[11:8] Timer 1 channel 1 input (Cannot be remapped) ADC0 Analog ADC nput 0 Enable analog function with GP_PBCFGH[7:4] TM2CLK Timer 2 external clock input TM1MSK Timer 2 external clock mask input 27 GND - Ground 28 GND - Ground

19 The return data includes basic configuration info of module:

20 15 Pwr=-03:means TX is -03dBm; PMode=0002:means power mode is extra PA. : 1. -3dBm or -5dBm 2. : AT+SETPWRMDE=0002

21 16 :PCB antenna or U.FL(PEX)antenna. Use U.FL connector, it need extra exterior antenna, following command can configure module to use U.FL connector. AT+SETANT=01 Use PCB antenna, it doesn t need extra exterior antenna, following command can configure module to use PCB antenna AT+SETANT=00

22 REX3DP has 4 antennas, buyer need to confirm with sales about the type before purchasing Figure PCB antenna PCB antenna

23 18 Attention when using PCB antenna: (1 cm at least, suggest more than 2.7 cm) 3. User should try to avoid other components or line interfere PCB antenna when designing board: Wires or other components avoid surrounding PCB antenna PCB antenna should be extended to the board Don t use metal shell to cover the PCB antenna Figure Area supporting components Figure Simple antenna

24 U.FL connects SMA antenna Figure U.FL connector U.FL connector Remark: Figure antenna cable Figure SMA antenna Figure completing picture of SMA antenna

25 U.FL connects PCB antenna Figure connect PCB antenna Figure completing picture

26 When system voltage is 3.3V When system voltage is 5.0V

27 Figure JTAG SWD Figure SWD connection

28 23 Table 3-8. Relationship between JTAG and Zigbee module Pin No. 20-pin JTAG nterface SWD connecting pin No. Pin Number (Name) 1 2(VCC) 1(VCC) 1(VCC) 2(VCC) 3(nTRST) 4(GND) 5(JTD) 27 28(GND) 6(GND) 5(GND) 22(PC4) 7(JTMS) 7(SWD) 8(GND) 19(SWCLK) 9(JTCK) 6(SWCLK) 10(GND) 11(RTCK) 12(GND) 13(JTD) 14(GND) 15(nRESET) 15(RESET) 8(RESET) 16(GND) 17(DBGRQ) 18(GND) 19(DBGACK) 20(GND) 10(PA4) 9(PT_EN) 9(PA5) 10(PT_DATA) 3.8. Figure RX sensitivity

29 24 Figure Figure 3-23.

30 25 4. Manufacturer REX=REXENSE REX 3 D 57 U Serial 3=Zigbee serial(cortex TM -M3 Core) Package type D=DP S=SMD U=Ultra compact L=LED lighting Chip No. 51=EM351 57=EM357(default) 64=STM32W108CBU64 Antenna U=U.FL connector(default) B=PCB antenna L=L antenna P=Pin out S=SMA antenna H=Spring antenna

31 5. 26