CHY100 ChiPhy Family. Charger Interface Physical Layer IC. Product Highlights. Description

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Michael Baldwin
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1 ChiPhy Family Charger Interface Physical Layer IC Product Highlights Fully supports Quick Charge 2.0 specification Class A: 5 V, 9 V, and 12 V output voltage Class B: 5 V, 9 V, 12 V, and 20 V output voltage USB battery charging specification revision 1.2 compatible Automatic USB DCP shorting to line Default 5 V mode operation Supports TOPSwitch and TinySwitch Very low power consumption Below 1 mw at 5 V output Fail safe operation Adjacent pin-to-pin short-circuit fault Open circuit pin fault Feedback Network V2 BP U1 VOUT Typical Applications Battery chargers for smart phones, tablets, netbooks, digital cameras, and bluetooth accessories USB power output ports Figure 1. Typical Application Schematic. PI Description is a low-cost USB high-voltage dedicated charging port (HVDCP) interface IC for the Quick Charge 2.0 specification. It incorporates all necessary functions to add Quick Charge 2.0 capability to Power Integrations switcher ICs such as TOPSwitch or TinySwitch and other solutions employing traditional feedback schemes. supports the full output voltage range of either Class A or Class B. Optionally Class B can be inhibited for protecting the battery charger from accidental damage. Figure 2. Package Option. SO-8 (D Package) automatically detects whether a connected Powered Device (PD) is Quick Charge 2.0 capable before enabling output voltage adjustment. If a PD not compliant to Quick Charge 2.0 is detected the disables output voltage adjustment to ensure safe operation with legacy 5 V only USB PDs. March 201 This Product is Covered by Patents and/or Pending Patent Applications.

2 BYPASS (BP) BANDGAP EFEENCE () 6 V 3.9 V 2 V V OUTPUT INHIBIT V2 N3 CONTOL LOGIC (LOOKUP TABLE) S SET CL Q Q N5 N V kω N1 2 V N GOUND () PI Figure 3. Functional Block Diagram. Pin Functional Description GOUND () Pin Ground. Pin Open Drain input of output voltage adjustment switch. Active for 9 V, 12 V, and 20 V output setting. V2 Pin Open Drain input of output voltage adjustment switch. Active for 12 V, and 20 V output setting. Pin Open Drain input of output voltage adjustment switch. Active for 20 V output setting. D Package (SO-8) BP V PI BYPASS (BP) Pin Connection point for an external bypass capacitor for the internally generated supply voltage. Figure. Pin Configuration. EFEENCE () Pin Connected to internal band-gap reference. Provides reference current through connected resistor. DATA LINE Pin USB data line input. DATA LINE Pin USB data line input. 2 ev. C 03/1

3 Functional Description is a low-cost USB high-voltage dedicated charging port (HVDCP) interface IC for the Quick Charge 2.0 specification. It incorporates all necessary functions to add Quick Charge 2.0 capability to Power Integrations integrated switcher ICs such as TOPSwitch or TinySwitch. also supports other solutions with traditional feedback schemes like optocoupler and secondary reference regulator TL31 as depicted in Figure 5. Figure 5. D1 C1 U1 TL31 6 U3 C PI with Traditional Output egulation (CV Only). supports the full output voltage range of Quick Charge 2.0 Class A (5 V, 9 V, or 12 V) or Class B (5 V, 9 V, 12 V, or 20 V). It automatically detects either Quick Charge 2.0 capable powered devices (PD) or legacy PDs compliant with the USB Battery Charging Specification revision 1.2 and only enables output voltage adjustment accordingly. Shunt egulator The internal shunt regulator clamps the BYPASS pin at 6 V when current is provided through an external resistor ( BP in Figure 5). This facilitates powering of externally over the wide power supply output voltage range of 5 V to 20 V. ecommended values are BP =.53 kω and C BP = 220 nf. BP BYPASS Pin Undervoltage The BYPASS pin undervoltage circuitry resets the when the BYPASS pin voltage drops below 3.9 V. Once the BYPASS pin voltage drops below 3.9 V it must rise back to V to enable correct operation. V2 C BP BP U2 DAT_LKG EF VOUT eference Input esister EF at the EFEENCE pin is connected to an internal band gap reference and provides an accurate reference current for internal timing circuits. The recommended value is EF = 127 kω. Quick Charge 2.0 Interface At power-up turns on switch N5 (see Figure 3) in 20 ms or less after the BYPASS pin voltage has reached V. Switch N and output switches N1 to N3 remain off. This sets the default 5 V output voltage level. With and short-circuited the normal handshake between the AC-DC adapter (DCP) and powered devices (PD) as described in the USB Battery Charging Specification 1.2 can commence. After switch N5 has been turned on starts monitoring the voltage level at. If it continuously stays above V DAT(EF) (typ V) and below V SEL(EF) (typ. 2 V) for at least 1.25 seconds will enter Quick Charge 2.0 operation mode. If the voltage at drops any time below V resets the 1.25 seconds timer and stays in USB Battery Charging Specification 1.2 compatibility mode with a default output voltage of 5 V. Once has entered Quick Charge 2.0 operation mode switch N5 will be turned off. Additionally switch N is turned on connecting a kω pull-down resistor to. As soon as the voltage at has dropped low (<0.325 V) for at least 1 ms starts accepting requests for different AC-DC adapter output voltages by means of applied voltage levels at data lines and through the powered device. Table 1 summarizes the output voltage lookup table, corresponding AC-DC adapter output voltages and status of switches N1 to N3. Output Switch Status 0.6 V 0.6 V 12 V N1 = N2 = On, N3 = Off 3.3 V 0.6 V 9 V N1 = On, N2 = N3 = Off 3.3 V 3.3 V 20 V N1 = N2 = N3 = On 0.6 V 5 V (default) N1 = N2 = N3 = Off Table 1. Output Voltage Lookup Table. For Quick Charge 2.0 Class A support only, the pin has to be connected to the BYPASS pin (directly or through a resistor up to 100 kω). This will inhibit any requests for setting a 20 V output. At USB cable disconnect the voltage level at is pulled down by resistor DAT(LKG) (see Figure 5). Once it drops below V will turn on switch N5 (thereby short-circuiting and ) and turns off switches N1 to N. This sets the default output voltage of 5 V. The recommended value for DAT(LKG) = 390 kω. 3 ev. C 03/1

4 Absolute Maximum atings BYPASS Pin Voltage to 9 V EFEENCE Pin Voltage to 9 V /V2/ Pin Voltage to 9 V / Pin Voltage to 5 V BYPASS Pin Current ma /V2/ Pin Current ma / Pin Current... 1 ma Operating Junction Temperature...-0 C to 150 C Operating Ambient Temperature C to 105 C Storage Temperature C to 150 C Lead Temperature (1) C Notes: 1. 1/16 in. from case for 5 seconds. Parameter Symbol Conditions SOUCE = 0 V; T J = -20 C to 85 C (Unless Otherwise Specified) Min Typ Max Units Supply, eference and Protection Functions BYPASS Pin Voltage V BP 5 6 V Power-Up eset Threshold Voltage BYPASS Pin Source Current BYPASS Pin Shunt Voltage EFEENCE Pin Voltage HVDCP Functions V BP(ESET) V I BPSC V BP =.3 V, T J = 25 C N1 = N2 = N3 = Off 135 µa V BP(SHUNT) I BP = 3 ma V V V Data Detect Voltage V DAT(EF) V Output Voltage Selection eference 12 V / 20 V Output Inhibit Threshold Data Lines Short-Circuit Delay High Glitch Filter Time Output Voltage Glitch Filter Time Pull-Down esistance Switch N1 Switch N2 Switch N3 Switch N Switch N5 V SEL(EF) V V INH V BP -0.6 V T DAT(SHOT) T GLITCH(BC) DONE T GLITCH(V) CHANGE V OUT 0.8 V See Figure ms ms ms DM(DWN) kω DS(ON)N1 I N1 DS(ON)N2 I N2 DS(ON)N3 I N3 DS(ON)N I N DS(ON)N5 I N5 = 200 µa, V () 3.6 V 20 0 Ω Data Line Capacitance C DCP(PW) See Note A 1 nf NOTES: A. Guaranteed by design. Not tested in production. ev. C 03/1

5 A SO-8 (D Package) B 2.90 (0.193) BSC 0.10 (0.00) C A-B 2X DETAIL A D 8 5 2X (0.15) BSC 6.00 (0.236) BSC 0.10 (0.00) C D Pin 1 ID 1.27 (0.050) BSC 1.35 (0.053) 1.75 (0.069) 0.10 (0.00) 0.25 (0.010) ( ) 0.20 (0.008) C 2X 7X ( ) 0.25 (0.010) M C A-B D 7X C 0.10 (0.00) C SEATING PLANE SEATING PLANE C 1.0 (0.01) EF H 0.0 (0.016) 1.27 (0.050) 0.17 (0.007) 0.25 (0.010) 0-8 o GAUGE PLANE 0.25 (0.010) BSC DETAIL A eference Solder Pad Dimensions 1.5 (0.057).00 (0.157) 5.5 (0.215) Notes: 1. JEDEC reference: MS Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness.. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. D08A 1.27 (0.050) 0.60 (0.02) PI Part Ordering Information CHY 100 D ChiPhy Product Family 100 Series Number Package Identifier D SO-8 5 ev. C 03/1

6 evision Notes Date A Initial elease. 07/13 B Extended Ambient Temperature to -0 C. 01/1 C Added Note for Class A Charger on page 3. 03/1 For the latest updates, visit our website: Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWE INTEGATIONS MAKES NO WAANTY HEEIN AND SPECIFICALLY DISCLAIMS ALL WAANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WAANTIES OF MECHANTABILITY, FITNESS FO A PATICULA PUPOSE, AND NON-INFINGEMENT OF THID PATY IGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at. Power Integrations grants its customers a license under certain patent rights as set forth at Life Support Policy POWE INTEGATIONS PODUCTS AE NOT AUTHOIZED FO USE AS CITICAL COMPONENTS IN LIFE SUPPOT DEVICES O SYSTEMS WITHOUT THE EXPESS WITTEN APPOVAL OF THE PESIDENT OF POWE INTEGATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. 201, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters 525 Hellyer Avenue San Jose, CA 95138, USA. Main: Customer Service: Phone: Fax: usasales@powerint.com China (Shanghai) m 210, Charity Plaza, No. 88 North Caoxi oad Shanghai, PC Phone: Fax: chinasales@powerint.com China (ShenZhen) 3rd Floor, Block A, Zhongtou International Business Center, No. 1061, Xiang Mei d, FuTian District, ShenZhen, China, Phone: Fax: chinasales@powerint.com Germany Lindwurmstrasse Munich Germany Phone: Fax: eurosales@powerint.com India #1, 1th Main oad Vasanthanagar Bangalore India Phone: Fax: indiasales@powerint.com Italy Via Milanese 20, 3rd. Fl Sesto San Giovanni (MI) Italy Phone: Fax: eurosales@powerint.com Japan Kosei Dai-3 Bldg , Shin-Yokohama, Kohoku-ku Yokohama-shi Kanagwan Japan Phone: Fax: japansales@powerint.com Korea M 602, 6FL Korea City Air Terminal B/D, Samsung-Dong, Kangnam-Gu, Seoul, , Korea Phone: Fax: koreasales@powerint.com Singapore 51 Newton oad #19-01/05 Goldhill Plaza Singapore, Phone: Fax: singaporesales@powerint.com Taiwan 5F, No. 318, Nei Hu d., Sec. 1 Nei Hu Dist. Taipei 1193, Taiwan.O.C. Phone: Fax: taiwansales@powerint.com Europe HQ 1st Floor, St. James s House East Street, Farnham Surrey GU9 7TJ United Kingdom Phone: (0) Fax: (0) eurosales@powerint.com Applications Hotline World Wide Applications Fax World Wide

Product 3 BV DSS. CAP200DG 1000 V 100 nf to 6 mf 7.5 MW to 142 kw. May 2015

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