User Manual Pluto 5 Controller

Transcription

1 User Manual Pluto Controller Document No. 0- Issue Current Issue :- Issue nd September 00 Previous Issue :- Issue r th May 00 HEBER Ltd. 00. This document and the information contained therein is the intellectual property of HEBER Ltd and must not be disclosed to a third party without consent. Copies may be made only if they are in full and unmodified. File Name: H:\pluto\manuals\pluto controller.doc Document No. 0- Issue

2 Belvedere Mill Chalford Stroud Gloucestershire GL NT England Tel: + (0) 000 Fax: + (0) 0 support@heber.co.uk File Name: H:\pluto\manuals\pluto controller.doc Document No. 0- Issue

3 Page i CONTENTS INTRODUCTION... NEW IN THIS RELEASE... OVERVIEW... CIRCUIT SCHEMATIC DESCRIPTION.... SHEET.... SHEET.... SHEET.... SHEET.... SHEET.... SHEET.... SHEET.... SHEET.... SHEET....0 SHEET SHEETS, &... CIRCUIT OPERATION.... POWER SUPPLIES.... RESET AND POWER FAIL DETECTION.... BATTERY BACKUP.... THE MC0 PROCESSOR..... CPU Processor Module..... SIM0 System Integration Module..... DMA Controller Module..... Serial Module..... Timer Module.... FPGA EPROM SOCKETS / EPROM AUTOSELECT FEATURE EPROM ADDRESS LINE SCRAMBLING IN BIT MODE..... *C00 EPROMs..... *C0 EPROMs.... MEMORY EXPANSION.... OPEN DRAIN OUTPUTS, OP AUX OUTPUTS, AUX INPUTS, IP DIL SWITCHES.... SOFTWARE CONTROLLED INDICATOR LED.... ON-BOARD PUSH BUTTON.... MULTIPLEXER.... MULTIPLEXED LAMP CURRENT SENSE.... SOUND GENERATION.... STEREO AMPLIFIER AND VOLUME CONTROLS.... SERIAL....0 INTERNAL I C BUS Real Time Clock E PROM... Document No. 0- Issue

4 Page ii MACHINE OPERATION DRIVING REELS READING THE DIL SWITCHES READING THE SWITCH INPUTS INTERFACING TO COIN & NOTE ACCEPTORS.... INTERFACING TO COIN PAYOUT MECHANISMS.... DRIVING VACUUM FLUORESCENT DISPLAYS (VFD).... USING THE EXTERNAL I C BUS.... DRIVING METERS.... MAKING SOUNDS..... Single Channel/Single Speaker (Mono) Mode..... Dual Channel/Dual Speaker (Stereo) Mode..... Known DMA Problems....0 USING MULTIPLEXED LAMPS.... USING MULTIPLEXED LEDS.... USING THE MULTIPLEX EXPANSION CONNECTOR.... ADDING VIDEO CAPABILITIES... SOFTWARE DEVELOPMENT... CONNECTOR TYPES AND PIN OUTS.... SCHEDULE OF CONNECTOR TYPES.... P RS CHANNEL A.... P DATAPORT (RS CHANNEL B).... P POWER INPUT.... P MULTIPLEXED LAMP SINKS.... P ULTREX MULTIPLEXED LEDS.... P BOX HEADER MULTIPLEXED LEDS.... P MULTIPLEXED LAMPS SOURCES.... P ULTREX REELS P BOX HEADER REELS.... P ULTREX GENERAL #.... P BOX HEADER GENERAL #.... P ULTREX GENERAL #.... P BOX HEADER GENERAL #.... P0 LOUDSPEAKERS.... P MULTIPLEX EXPANSION.... P AUX OUTPUTS.... P EXTERNAL I C BUS.... P IO EXPANSION CARD CONNECTOR....0 P MEMORY EXPANSION CARD CONNECTOR.... P BACKGROUND DEBUG MODE CONNECTOR... Document No. 0- Issue

5 Page iii LIST OF TABLES Table. Allocation of MC0 Pins Controlled by SIM0 Module... Table. Allocation of MC0 Pins Controlled by DMA Module... Table. Allocation of MC0 Pins Controlled by Serial Module... Table. Allocation of MC0 Pins Controlled by Timer Module... Table. Possible EPROM Configurations... 0 Table. Re-Mapping of Address Lines in *C00 Mode... Table. Re-Mapping of EPROM Contents in *C00 Mode... Table. Re-Mapping of Address Lines in *C0 Mode... Table. Re-Mapping of EPROM Contents in *C0 Mode... Table 0. Mapping of Open Drain Outputs (OP0-) to TPIC Devices... Table. Mapping of Inputs IP0-... Table. Mapping of DIL Switch Inputs... Table. I C Slave Addresses for RTC, U0... Table. I C Slave Addresses for E PROM, U... Table. Recommended Reel Stepper Motor Drive Connections... 0 Table. AMP Ultrex Connector Part Numbers... Table. Tyco Box Header Connector Part Numbers... Table. AMP MTA-00 Connector Part Numbers... Table. AMP MTA- Connector Part Numbers... LIST OF FIGURES Figure - Schematic Sheet - Root Sheet... Figure - Schematic Sheet - CPU... Figure - Schematic Sheet - FPGA... 0 Figure - Schematic Sheet - Memory... Figure - Schematic Sheet - Sound... Figure - Schematic Sheet - Outputs... Figure - Schematic Sheet - Inputs... Figure - Schematic Sheet - Power Supply... Figure - Schematic Sheet IO Connectors... Figure 0 - Schematic Sheet 0 - Reset/Battery/RS... Figure - Schematic Sheet - Lamp Column/LED Digit Drives... Figure - Schematic Sheet - Lamp Row Drives... Figure - Schematic Sheet - LED Segment Drives... 0 Figure - Pluto Component Ident... Figure - Photograph of Pluto with Ultrex Connectors (Pluto U)... Document No. 0- Issue

6 Page INTRODUCTION The Pluto Controller board is a natural progression in the Pluto family of products. It builds on the proven reliability and technical excellence of previous Pluto boards and provides improved performance and flexibility at lower cost. This manual covers the detail of the hardware operation of Pluto Controller board, other boards in the system have their own manuals. NEW IN THIS RELEASE Section. has revised audio information. OVERVIEW The Pluto Controller board is a low cost, high performance single board controller for amusement machines. An reel machine with lamps, LED digits, Linewriter display, Coin Acceptors, Note Acceptors and Payout Hoppers can be controlled without any additional boards. Single channel sound can be played through one or two speakers. Two Channel (mono or stereo) sound is available by plugging in an additional IC. Pluto boards are supplied with either Ultrex or Box Header connectors. Pluto with Ultrex connectors is referred to as Pluto U. Pluto with Box Header connectors is referred to as Pluto B. These connectors and all the other connectors on the Pluto board are documented in Section - Connector Types and Pin Outs in this user manual. Add-on boards are available to increase the number of lamps by up to, LED Digits by up to as well as CGA/VGA Video and Memory Expansion. The numbering system on all Pluto boards is consistent, in that, where Lamps and LEDs are involved the product name has a suffix X/Y. X is the number of lamps and Y is the number of LED digits that that product drives. The Pluto Controller board is available as a Pluto / Controller and a Pluto / Controller. Document No. 0- Issue

7 Page CIRCUIT SCHEMATIC DESCRIPTION This section is a walk through of the Pluto Controller board (-0) circuit schematics, Figures - of this document. A detailed description is given in Section CIRCUIT OPERATION.. Sheet This sheet shows the interconnection between the remaining sheets of this drawing.. Sheet This sheet shows the following items: Motorola MC0 Processor. Pull-up resistors on Address Bus, Data Bus and other Control Signals. Push Button Switch, SW. P BACKGROUND DEBUG MODE connector.. Sheet This sheet shows the FPGA.. Sheet This sheet shows the following memory related circuits: Sockets for or EPROMs, U and U Kbytes Battery backed RAM, U and U P MEMORY EXPANSION connector for plug-in Memory Cards. Sheet This sheet shows the following sound related circuits: Standard Sound Channel #, U (OKI MSM). Optional Sound Channel #, U (OKI MSM). TDA0AQ Stereo Audio Amplifier. P0, LS connector for loudspeakers.. Sheet This sheet shows the Open Drain Outputs, OP0-.. Sheet This sheet shows the following circuits: External inputs, IP0- Two way DIL switches, SW and SW Document No. 0- Issue

8 Page. Sheet This sheet shows various Power Supply related functions: Current sensing +V Meter supply Power fail detection. Current sensing from Lamp Multiplex. Fuse and +V regulator. Voltage rail overvoltage and transient protection. P PWR IN power input connector. Sheet This sheet shows the following connectors. P REELS carries enough lines to run reels, including a sub set of the lamp multiplexer and power supplies for the motors. P and P are general purpose. P MULTIPLEX EXPANSION provides signals for the connection of Multiplex Expansion boards. P AUX OUTPUTS provides open drain TTL outputs, typically for driving VFD displays. P I C provides a connector for external I C expansion, e.g. E PROM modules. Note that the lines used to implement this connector are different to the lines allocated for the internal I C bus to U0 and U. P EXPANSION is a position for a daughter board for expansion..0 Sheet 0 This sheet shows the following circuits and connectors: Reset circuit and LED. Battery Backup for RAM and optional Real Time Clock. Optional I C Real Time Clock socket, U0, PCF. Optional I C E PROM socket, U, C0 ( bytes) or C0 (0 bytes). RS buffers. P RS is a general purpose RS serial communication port. P DATAPORT is the BACTA standard Dataport.. Sheets, & These sheets show the Multiplex Lamp and LED drive circuits and connectors. Sheet shows the Lamp Columns/Digits Sink drivers. Sheet shows the Lamp Row/Source drivers Sheet shows the LED Segment drivers P LAMP SINKS is the Lamp Array Column/Sink outputs P LED is the connector for the or LED digits. P LAMP SRC is the Lamp Array Row/Source outputs Document No. 0- Issue

9 Page CIRCUIT OPERATION This section describes how some elements of the circuit operate and their capabilities and limitations. A subsequent section deals with how the various capabilities of the board are used to implement specific amusement machine functions.. Power Supplies The Power Input to the board is on P. There are input voltages required, +V, -V and V or V for the lamp multiplex. The +V supply is fused by F (.A) as it comes on the board. From the un-fused (input) side, the +V is distributed to the Reel Connector, P where it may be used to provide the supply for the Stepper Motors. From the fused side, the +V is used for the following: Regulated via U to provide the Vcc (+V) supply for the board. This will draw up to 0mA from the +V rail. To provide the Power Supply for the Stereo Audio Amplifier, U. The load current drawn by this will depend on the audio volume, etc. but is not likely to exceed an average of about 00mA. Monitored by UB to detect imminent failure of the +V supply and cause a Level (Non- Maskable) Interrupt, NMI-. The interrupt will occur if the +V supply drops below approximately.v. To provide the Power Supply for the multiplexed LED drive circuits. With LED digits fitted and all having all segments illuminated, the current drain is likely to be between 00mA and 0mA. Distributed to various connectors, P, P, P, P, P and P for optional use by external circuits. When connecting external loads to the Fused +V outputs on P, P, P, P, P and P make sure that the total current drawn is within the rating of fuse F (.A), making due allowances for the other loads as described above. The V supply input provides the negative supply for the RS Transmitter Buffer, U, and the V supply required on the DATAPORT Connector, P. The Lamp Multiplex supply should be +V or +V, depending upon the duty cycle employed by the software. See Section.0, Using Multiplexed Lamps for more information. Transient suppressers (Tranzorbs) are fitted on the +V supply (fused side), -V supply and Vcc to protect these lines against any overvoltage.. Reset and Power Fail Detection TL0 device, U, (see Schematic Sheet 0 - Reset/Battery/RS), provides the system reset. At power up, the system is held in a reset state (RESET- low, RESET high) for about seconds. This time is determined by C. The processor may initiate a full hardware reset at any time by asserting Port B, pin 0 (PB0) low, which will trigger the TL0 via the RESIN- pin. The RESET lines will also be immediately asserted by the TL0 if the Vcc line drops below.v. While the system is in a reset state, i.e. RESET- is low, a red LED, LD, is illuminated. The power fail detection is a simple threshold detection on the V rail using one section of the quad comparator LM (UB), see Schematic Sheet - IO Connectors. When the +V input falls below a threshold of approximately.v, the output of the comparator goes low which causes a Level interrupt (NMI) to the processor. This will occur BEFORE the 0 regulator drops out of regulation and the Vcc line starts to drop, thus giving the processor a period of time to react before the RESET is asserted by the TL0, U. The main purpose of giving the Document No. 0- Issue

10 Page processor the NMI in advance of the RESET is to avoid the risk of an incomplete RAM write operation occurring if the RESET were to be asynchronously asserted while such an operation was being carried out. The time available between the assertion of NMI and the assertion of RESET will depend on the rate of fall of the +V line, which will obviously be dependent upon the power supply and the loading on the +V, but will typically be several milliseconds.. Battery Backup A backup battery, BT, is provided (see - Schematic Sheet 0 - Reset/Battery/RS) to allow the two RAMs U and U to retain data while the board is powered down and to keep the optional Real Time Clock chip, U0, running. BT is a two cell rechargeable NiMH (Nickel Metal Hydride) battery, capacity 0mA/hr. The circuit comprising BT, Q, R and R provides the battery trickle charge and switchover of the secured power supply rail, Vbatt. While Vcc is at V, current flows through the base-emitter junction of Q through R into the battery. On charge, the voltage on BT will be about.v so the current through R will be (-V BE -.)/00, about 0.mA. Thus Q will be turned ON and Vbatt will be a V CEsat below Vcc. Current will therefore also flow through R into Vbatt, (-V CEsat -.)/00, about 0.mA. Total trickle charge current is therefore =.ma. The specification of the cells calls for a trickle charge of between.0c and.0c. C is 0mA, so the acceptable range is between.ma and.ma. When power is removed, Vcc collapses to ground. The base-emitter junction of Q is now reverse biased and therefore no current flows through R and Q is OFF. Vbatt is now connected to the positive end of BT via R. The discharge current into the RAMs and RTC should not exceed 0µA, which will result in a voltage drop in R of less than 0.V. This gives a worst case battery life in excess of two months, and in practice much higher. When on battery backup it is vital that the RAMs are placed in the standby state by ensuring that the CS- line is high. Q and R achieve this. When the RESET- line goes low, which may occur either as a result of a Reset occurring or Vcc collapsing, Q turns OFF causing the CS- lines to the RAMs to be pulled to Vbatt by R.. The MC0 Processor Full details of the operation of the processor is given in the Motorola MC0 User Manual [see Adobe Acrobat File 0um.pdf, plus Addenda files 0um_ad.pdf and 0um_ad.pdf] The MC0 contains the following functional blocks: Document No. 0- Issue

11 Page.. CPU Processor Module The CPU is a processing core which is basically 000 code compatible but with a number of enhancements. For full details of operation please refer to both the Motorola MC0 User Manual and the Motorola M000 Family Programmers Reference Manual [see Adobe Acrobat File kprm.pdf]. All modern 000 Compilers and Assemblers have various options for the target CPU. When generating code for the Pluto System, the CPU option should be used. If the Compiler/Assembler is old it is possible that it may not have a CPU option. In this case, the Compiler (if used) should be run with the 000 option set. The assembler may be run in 00 mode which will allow the use of the MOVES command which is required during initialisation to set up the Module Base Address Register (MBAR) in the MC0. Care must be taken not to write code that calls any other 00 instructions that may not be implemented on the CPU. The Pluto Development Kit includes a suitable C Compiler and Assembler... SIM0 System Integration Module This module controls various aspects of the operation of the processor, such as configuration, clock, external bus, etc. When used in the Pluto System, the main considerations in the use of this module are:... Module Base Address Register Set the Module Base Address Register, MBAR, to a suitable address during initialisation. This sets the base address of all the internal module registers. In the example code it is set in Module except.asm to value 0xffff f000. There is nothing magic about this value, but obviously it must be set to an address that is clear of any other devices in the processor memory map. This register must be set before any other module initialisation is attempted.... Chip Selects Set-up the Chip Select outputs, CS0- to CS-. The Pluto System allocates these as follows: CS0 - is used to map the system programme memory. This consists of any EPROM fitted to the on-board EPROM sockets, U and U plus any extra EPROM or FLASH devices fitted to the Memory Expansion Connector, P. Exact mapping, within the area defined by CS0-, is carried out be the system FPGA. CS - is used to map the on-board, battery backed RAM and, if fitted, any external RAM on a memory card on connector P. CS - is used to map both the internal registers of the FPGA and the on-board, CS - is normally spare and is available on the expansion connector, P. Its main use is for the selection of the optional add-on CGA/VGA Video Card. After hardware reset, CS0- will be asserted for memory accesses anywhere in the memory map which allows the processor to boot. However, the chip selects must be programmed immediately after Reset and prior to any function or subroutine calls, because until they are, CS- will not be active and therefore it will not be possible for the processor to access RAM. Example code for setting up the pairs of Chip Select Base and Mask registers is given in Module except.asm... Periodic Interrupt Timer. The sim0_m.c Module in the Sample Software sets this timer to provide a high priority ms interrupt which is normally used by the software to provide basic system timing. This function is controlled by the PICR and the PITR. Document No. 0- Issue

12 Page... Clock Synthesiser Control The SYNCR controls the operation of the main processor clock. The MC0 is provided with a.khz reference to which the main clock is phase locked. After reset, the main clock defaults to.mhz. The maximum clock frequency of the standard MC0 is.mhz.... System Protection The SYPCR controls the bus monitors and software watchdog. Other safeguards in the design give adequate protection against programme malfunction as a result of noise, etc. The Software Watchdog feature is disabled, however, it could be used if required. The Bus Monitor should be enabled and may be left set at its default of clock cycles timeout.... SIM0 Module Pin Allocations Pins under the control of the SIM0 module are allocated as follows. Table. Allocation of MC0 Pins Controlled by SIM0 Module NAME PIN FUNCTION PA0/A- O To Expansion Connector P, Pin b, K pull-up & RESET to Sound Channel #, U PA/A/IACK- O To Expansion Connector P, Pin b, K pull-up & RESET to Sound Channel #, U PA/A/IACK- O To Expansion Connector P, Pin b, K pull-up & Drive for Indicator LED LD PA/A/IACK- 0 I To Expansion Connector P, Pin b, K pull-up & Push Button SW Input PA/A/IACK- To Expansion Connector P, Pin b, K pull-up & SCL line (I C) to RTC, U0 and E PROM, U PA/A/IACK- To Expansion Connector P, Pin b, K pull-up & SDA line (I C) to RTC, U0 and E PROM, U PA/A0/IACK- Drives S pin on SFX Channel # (U) K pull-up & MPX Lamp Current Sense Input PA/A/IACK- Drives S pin on SFX Channel # (U) K pull-up & MPX Lamp Short Circuit Sense Input PB0/MODCK O Drive LOW to initiate hardware reset. PB/IRQ-/CS- O CS- Maps RAM PB/IRQ-/CS- O CS- Maps FPGA registers and PB/IRQ- I Vmeter current sense input. PB/IRQ-/CS- To Expansion Connector P, Pin a PB/IRQ- To Expansion Connector P, Pin b, K pull-up PB/IRQ- To Expansion Connector P, Pin b, K pull-up PB/IRQ- 0 I IRQ-/NMI input from Power Fail Detection Circuit CS0-/AVEC- O CS0- Maps ROM, both on-board U/U and on Memory Expansion Connector (via FPGA). Document No. 0- Issue

13 Page.. DMA Controller Module The DMA Module provides DMA Channels. On the Pluto these are used for sending sound data from the Programme Memory to the OKI MSM Sound Chip(s). DMA Channel is used to send data to Sound Channel #, which is fitted as standard to the Pluto Board. DMA Channel is used for the optional add-on Sound Channel # if fitted (IC). The DMA channel should be set to work in following modes: External request Dual address Source address incrementing (Memory) Destination address not incrementing (FPGA sound register) Transfer size = byte Interrupt on completion Pins controlled by the DMA module are allocated as follows: Table. Allocation of MC0 Pins Controlled by DMA Module PIN NO. FUNCTION DREQ- I SFX Channel DMA request DACK- O No connection DONE- IO Not used, K pull-up DREQ- I SFX Channel DMA request DACK- O No connection DONE- IO Not used, K pull-up.. Serial Module The Serial Module provides Asynchronous Comms on Channels, Channel A and Channel B. It is functionally very similar to the / range of DUARTs. Channel A is buffered to RS levels and connected to connector P. Signals RX, TX, RTS and CTS are provided. Channel B is buffered to RS levels and connected to DATAPORT connector P. Signals RX, TX, RTS and CTS are provided. The Channel A signals are also made available on the TTL Expansion Connector, P, at TTL levels. Thus, alternative interfaces may be provided on an Add-on Board to allow, say, RS or Mars HII interfaces to be implemented. The exact set up of the Serial Module will obviously depend upon the functionality required. Document No. 0- Issue

14 Page Pins controlled by the Serial module are allocated as follows: Table. Allocation of MC0 Pins Controlled by Serial Module PIN NO. FUNCTION RXDA I RX DATA Channel A, P, Pin (RS level) & To IO Expansion Connector P, Pin c (TTL level) TXDA O TX DATA Channel A, P, Pin (RS level) & To IO Expansion Connector P, Pin c0 (TTL level) RXDB I RX DATA Channel B, DATAPORT P (RS level) TXDB O TX DATA Channel B, DATAPORT P (RS level) OP0/RTSA- O RTS Channel A, P, Pin (RS level) & To IO Expansion Connector P, Pin c (TTL level) OP/RTSB- O RTS Channel B, DATAPORT P (RS level) OP/RXRDYA- O SFX Channel # U, Pin S (Select Sample Rate) OP/TXRDYA- O SFX Channel # U, Pin S (Select Sample Rate) CTSA- I CTS DUART Channel A, P, Pin (RS level) & To IO Expansion Connector P, Pin c (TTL level) CTSB- I CTS Channel B, DATAPORT P (RS level).. Timer Module The Timer Module provides General Purpose Timers. The Pluto Board uses these to provide a variable duty-cycle signals on TOUT and TOUT that is used to control the volume setting on each channel of the TDA0AQ Stereo Audio Amplifier. Timer (TOUT) controls the volume of Sound Channel #. Timer TOUT) controls the volume of Sound Channel # if it is fitted. If Sound Channel # is not fitted, then Timer may be used for other purposes. See Section., Making Sounds for detailed information on the operation of the Volume Controls. Pins TGATE- and TGATE- are allocated as general purpose inputs which are used to read the SCL and SDA lines on the External I C Connector, P. Pins controlled by the Timer Module are allocated as follows: Table. Allocation of MC0 Pins Controlled by Timer Module PIN NO. FUNCTION TGATE- I Read External I C line SCL on P, Pin (inverted) TIN I Not Used Strapped To Vcc TOUT 0 O Variable Duty Cycle Volume Control SFX Channel # TGATE- I Read External I C Line SDA on P, Pin (inverted) TIN I Not Used - Strapped To Vcc TOUT O Variable Duty Cycle Volume Control SFX Channel # Document No. 0- Issue

15 Page 0. FPGA The Pluto Controller is fitted with an lead PLCC socket, position U, into which is plugged an FPGA. The standard FPGA type used is an Actel A0MX0-PL. The purpose of fitting an FPGA to the system is twofold. First, to allow the Pluto Controller to be uniquely configured for each user of the system to give commercial and software security (see the FPGA SECURITY MANUAL). Secondly, it allows particular advanced features, for example, the EPROM Autoselect and Multiplex dimming, to be economically implemented. The following main functions are carried out by the FPGA: Control automatic EPROM mode selection Generate control signals for on-board EPROM and RAM Generate control signals for Memory Expansion Connector P. Generate DMA requests and multiplex data for Sound Channels &. Control and drive of data to Multiplex Arrays, both on-board MPX and expansion MPX. Provide various levels of Software Security. Form an oscillator with.mhz resonator: Generate Main Clock, EXTAL for MC0 Generate clock for MC0 Serial Generate clock for OKI MSM devices, EPROM Sockets / EPROM Autoselect Feature The EPROM positions, U and U, are configured such that possible configurations of programme memory are possible (assuming no external memory expansion via P): Table. Possible EPROM Configurations U U Mode Configuration Total Size Addresses scrambled C00 omit bit k* Kbyte no C00 C00 bit K* Mbyte yes C0 omit bit 0k* Mbyte no C0 C0 bit 0k* Mbyte yes It is not necessary to change any links on the board in order to switch between different memory configurations. All relevant switching is carried out within the FPGA, which contains an EPROM Autoselect feature. After Power-up, during the reset period, the FPGA reads the top byte address of U. Data contained in this byte defines the memory configuration required and the FPGA sets up the control lines to the EPROM sockets accordingly, so that, at the end of reset, the processor is able to read the EPROM(s) correctly. Thus, after the final linked EPROM software module has been created, prior to being blown into EPROM, the top location of the memory must be overwritten with suitable data to signify the EPROM configuration that will be used. This is the feature referred to as EPROM Autoselect. A full operational description of this feature is given in the User manual for the FPGA in use on the Pluto Controller Board. As with the Pluto System, in order to facilitate the option to use either or EPROMs, i.e. run in bit or bit mode, it is necessary to have some scrambling of the address lines to the EPROMs when operating in bit mode. Therefore, prior to blowing bit EPROMs, the data must be re-arranged to compensate. A software utility is provided with the Pluto Development Kit to carry this out. Document No. 0- Issue

16 Page Note that this scrambling of address lines is applicable ONLY to sockets U and U on the Pluto Controller Board. Any EPROM sockets on Memory Expansion Cards are connected : to the address bus and do NOT require any special processing.. EPROM Address Line Scrambling in Bit Mode.. *C00 EPROMs In bit mode, running with * C00 EPROMs, the scrambling of the address lines cause the following effect on the memory mapping in the EPROMs. Note that this table applies to the re-mapping that occurs to the EPROM contents, rather than the actual address lines. Table. Re-Mapping of Address Lines in *C00 Mode 0 Address Bus EPROM Address A0 Not Used in Bit Mode A-A A-A A A Thus, for example, addresses will be translated as follows so the contents of the EPROM must be rearranged to compensate: Table. Re-Mapping of EPROM Contents in *C00 Mode 0 Access Address Will Read From This Location in EPROM C FFFC 000F FFF 000 FFFE 000F FFFC F FFFC 000F FFFA 000F FFFE 000F FFFE.. *C0 EPROMs In bit mode, running with * C0 EPROMs, the scrambling of the address lines cause the following effect on the memory mapping in the EPROMs. Note that this table applies to the re-mapping that occurs to the EPROM contents, rather than the actual address lines. Table. Re-Mapping of Address Lines in *C0 Mode 0 Address Bus EPROM Address A0 Not Used in Bit Mode A-A A-A A A A0 A0 Document No. 0- Issue

17 Page Thus, for example, addresses will be translated as follows so the contents of the EPROM must be rearranged to compensate: Table. Re-Mapping of EPROM Contents in *C0 Mode 0 Access Address Will Read From This Location in EPROM FFFC 000F FFF 000 FFFE 000F FFFC F FFFC 000F FFFA 000F FFFE 000F FFFA FFFC 00F FFF 00 FFFE 00F FFFC F FFFC 00F FFFA 00F FFFE 00F FFFA Document No. 0- Issue

18 Page. Memory Expansion Various optional memory cards may be fitted to the Memory Expansion Connector P. Seven lines from the FPGA are included along with data lines and address lines. The default functionality of the FPGA lines allows memory cards fitted with up to EPROM or FLASH devices to be accommodated along with a pair of RAM devices with no additional mapping components. If a memory card is fitted with V FLASH devices, then Write facilities are available. EPROM Autoselect is also available with devices fitted on a Memory Card.. Open Drain Outputs, OP0- A block of Open Drain Outputs, OP0-, are provided by off TPIC devices U-U (see Schematic Sheet - Outputs). These are memory mapped as the least significant byte of a block of words of address space. The chip select for these devices, CS_OP-, is provided by the FPGA. Consult the User Manual of the FPGA being used for exact mapping. Please note that the chips are bit wide, not byte wide. Thus, Bit 0 of each word drives one device, U: Bit drives U, etc. Table 0. Mapping of Open Drain Outputs (OP0-) to TPIC Devices Bit D D D D D D D D0 Pin U U U U U U U U Addr. Q OP OP OP OP0 OP OP OP OP Base+ Q OP OP OP OP OP OP0 OP OP Base+ Q OP OP OP OP OP OP OP OP0 Base+0 Q OP OP OP OP OP OP OP OP Base+ Q OP OP0 OP OP OP OP OP OP Base+ Q OP OP OP OP0 OP OP OP OP Base+ Q OP OP OP OP OP OP0 OP OP Base+ Q0 OP OP OP OP OP OP OP OP0 Base+0 Basically, the drive capability of these devices is 0mA per output, continuous, with all outputs ON. If less than outputs are ON in any one package, or any outputs are operating with a small load, the capacity of the other outputs increases. For example, at C, the TPIC can sink 00mA continuously from outputs. Please refer to the data sheet for the TPIC (tpic.pdf) for details. When allocating any output to a load greater than 0mA, consideration should be given to the loading on each device. See Section., Driving Reels for details on driving standard reel mechanism stepper motors. Note also that, because they are MOSFETs, the outputs are resistive (<Ω) and do not suffer from the minimum saturation voltage of about V which would be the case if they were darlingtons. Therefore, at low currents, they pull down close to Gnd and may be safely used to drive TTL Inputs, Switch Strobes, Coin Mechanism Enables, etc. Document No. 0- Issue

19 Page.0 AUX Outputs, AUX0- auxiliary TTL level open drain outputs are provided by U0 (see Schematic Sheet - IO Connectors). U0 is a TPICB which functions exactly the same as the TPIC devices used to drive OP0-, but with a lower drive capability (see data sheet tpicb.pdf ). They are memory mapped as the least significant bit of a block of bytes of address space at an address determined by the FPGA fitted to the board. See the appropriate FPGA User Manual for details. They are open drain outputs fitted with K pull-up resistors to Vcc. AUX0- are routed to connector P AUX OUTPUTS. AUX- are routed to Connector P I C.. Inputs, IP0- External inputs are catered for by input lines, IP0- (see Schematic Sheet - Inputs). Like the Open Drain outputs these are memory mapped as the least significant byte of a block of words of address space. Each input is provided with a K pull-up resistor to Vcc (+V) and feeds into a HC family device (rather than HCT). This give the inputs a low level threshold of <.V and a high threshold of >.V. The K resistor in series with the input protects the HC devices from noise spikes or high voltages on the inputs. The.V low threshold allows the inputs to be safely driven as a multiplexed array with a diode in series with each switch with the strobes generated using a number of the Open Drain Outputs, OP0-, described above. The inputs are mapped as shown in the following table. The top bits of each word are read as s and bits to contain the DIL Switch Settings (as described in the next section). The base address is defined by the FPGA. Table. Mapping of Inputs IP0- D- D- D D D D D D D D0 Base+ 0xF IP IP0 IP IP IP IP IP IP DIL SW Base+ 0xF IP IP IP IP0 IP IP IP IP Base+ 0xF IP IP IP IP IP IP0 P IP Base 0xF IP IP IP IP IP IP IP IP0 Document No. 0- Issue

20 Page. DIL Switches The Pluto board is equipped with two way DIL Switches, SW and SW. These are read at the same addresses as the Inputs (see preceding Section). Table. Mapping of DIL Switch Inputs D-D D D0 D D D-D0 Base+ 0xF SW: SW: SW: SW: IP- Base+ 0xF SW: SW: SW: SW: IP- Base+ 0xF SW: SW: SW: SW: IP- Base 0xF SW: SW: SW: SW: IP-0. Software Controlled Indicator LED LD is a green LED that may be turned on or off under software control (see Schematic Sheet - IO Connectors). The LED may be used to provide an indication that software is running or perhaps for fault diagnosis. The PORTA line from the MC0 SIM0 Module drives the LED. After reset, the PORTA pins are high impedance and pulled high by resistor network N. This signal passes through the inverter UF which thus turns ON the LED. Therefore, initially and with no action on the part of the software, the LED will be ON indicating that Vcc is present. If the software sets PORTA pin as an output and drives it low, the LED will go OFF. The PORTA pins are taken to the Expansion Connector P. Future Expansion Cards may use the PORTA pin for some other function, in which case this will have to be taken into consideration when operating the indicator LED.. On-board Push Button A Push Button Switch, SW, is provided on the board (see Schematic Sheet - CPU). The function of this switch is at the discretion of the user of the board. It is connected so as to pull the PORTA line from the MC0 SIM0 Module to Gnd when operated. The PORTA pins are taken to the Expansion Connector P. Future Expansion Cards may use the PORTA pin for some other function, in which case the possible interaction with SW will have to be taken into account.. Multiplexer The Pluto Controller board provides hardware assistance (within the FPGA) to the Processor allowing two * Multiplex Arrays (referred to below as MPX and MPX) to be controlled. From a logical or software point of view, these arrays are uncommitted and may be configured to be either Lamp or LED drives, depending on what interface components are fitted. When running the lamps from a V supply, a in duty cycle is employed on the column strobes (sinks) allowing the full capabilities of the two arrays, MPX and MPX to be utilised. If the multiplexed lamps are run from a V supply, a in duty cycle must be utilised and the useable size of the two arrays reduces to *. The Pluto / Controller Board is intended for customers who run with a V lamp supply and require the maximum drive capability of the board. It has ½ of MPX configured as a * () Lamp Drive Array and the other ½ configured as a * ( seven-segment digits) LED Drive Array. Document No. 0- Issue

21 Page The Pluto / Controller Board is intended for users who require less drive capability or who wish to run the lamps at V. It has ¼ of MPX configured as a * () Lamp Drive Array and the other ¼ configured as a * ( seven-segment digits) LED Drive Array. The other * Multiplex Array (MPX) is utilised by adding external low-cost Pluto Multiplex Expansion Boards, wired to Connector P. Each board only requires signal wires from P plus Power Supplies. Pluto Multiplex Expansion Boards will be available in a number of different sizes, but all based on providing additional * blocks of either Lamp or LED drivers. Thus, the basic Pluto configuration may be expanded externally by another blocks which may be any mix of Lamps or LEDs. Pluto Multiplex Expansion Boards may also be added to Multiplex Array MPX (which is already used by the on-board drivers). Thus, for example, the Pluto / Controller Board, running at V, could have Expansion Boards added to increase its drive capability to that of the Pluto / Controller Board. The Lamp Multiplex Drive Circuitry is designed to drive V, 00mA bulbs. However, it is permissible for a small number (up to ) of positions to drive either a higher power bulb (V, 0ma) or a pair of 00mA bulbs. These "high load" positions should be arranged such that no more than one is on any one Row or Column drive. Multiplex Array MPX has hardware assistance from the FPGA to enable dimming control. Dimming level may be set independently for each of the Column strobes, e.g. the lamps on one Column Strobe could be set to one brightness level while the lamps on a different Column Strobe could be set to another brightness. The overall basic timing of the multiplexing remains under software control allowing overdrive of lamps for special effects. Multiplex Array MPX may be optionally configured with its full * capacity without the availability of hardware assisted dimming, or with * capability with the hardware assisted dimming facility intact. This option is selected by a bit in the FPGA see the relevant FPGA User Manual for details. Dimming is achieved changing the data presented to the Lamp Row/LED Segment drives at an adjustable time within the ms strobe time. Thus each lamp/led has two bits of data associated with it in software the first bit is the data applied during the first part of the ms Strobe period, the second bit is applied during the second period. The duration of the period that the first bit is applied for may be set in units of / ms. The multiplex is software driven. Every ms, data for the next strobe is written to the FPGA which in turn formats and serialises the data before clocking out the MPX data to the on-board 0 shift registers (U,U,U0,U,U,U) and the MPX data, via P, to any Multiplex Expansion Boards used. The exact format of the data to be written each millisecond is determined by the design of the FPGA being used, but in general it is as follows. bits of MPX Row/Segment data. First period data. bits of MPX Row/Segment data. Second period data. bits of MPX Row/Segment data. First period data. bits of MPX Row/Segment data. Second period data. bits defining Column/Digit strobe number to activate. bits defining First Period duration (units of.s). Consult the User Manual of the actual FPGA in use for exact details of operation. Document No. 0- Issue

22 Page. Multiplexed Lamp Current Sense A facility is provided to allow the processor to check the / possible lamp positions of MPX to determine: a. Is a light bulb present? b. Is there a short circuit in this position? This facility is intended to be run at power up and, perhaps, as a production test. The facility cannot be used during normal operation of the machine. A resistance of approximately mω is implemented, as a copper track on the PCB, between common source connection of all the Lamp Column/LED Digit sinks, Q-0 and Gnd (see Schematic Sheet - Lamp Column/LED Digit Drives). The voltage across this resistor is compared against thresholds formed by resistor chain R, R and R by comparators UC and UD (see Schematic Sheet - Power Supply). These thresholds correspond to nominal currents of about ma and.a. The outputs of the comparators, UC and UD are connected to processor lines PORTA and PORTA. The current sensing comparators may be disabled by SFX_CLK being enabled. When SFX_CLK, a 0kHz clock, is enabled by setting a bit in the FPGA (see FPGA User Manual), the + inputs of the comparators are pulled up to about +V by D/C/C0 which forces the comparator outputs (which are open collector) OFF. In this state the lines PORTA and PORTA are free to be used as outputs driving the S & S pins of SFX Channel # or as required by any card fitted to the Expansion Connector, P. When the SFX-CLK is turned OFF (and forced low), any voltage on C/0 is discharged by R, and the current sensing circuit is enabled. With no current through the Column/Digit Sinks, both outputs PORTA/ will be LOW because V+ < V- on the comparators. When the current through the mω resistor exceeds a nominal ma, PORTA will go high. When the current exceeds a nominal.a, PORTA will also go high. The sequence of operation to test a lamp is as follows: Turn off SFX_CLK in FPGA to enable circuit. Turn off all Row/Digit drives on MPX. Ensure PORTA and PORTA both read 0 Turn on lamp to be tested on multiplex by writing appropriate data to FPGA. Start a ms timer. Loop watching lines PORTA and PORTA. If PORTA line goes high, there is a short circuit in this position, so immediately disable the multiplex drives by turning off Multiplex OE line in the FPGA. If PORTA line goes high but not PORTA, then there is a light bulb connected and apparently working. If ms timer times out without either line going high, then either no bulb present or it is open circuit. Record result and go on to next bulb. When complete, act as required on results. Re-enable SFX-CLK to allow Sound Channels to work. Document No. 0- Issue

23 Page. Sound Generation The sound generation circuits are shown on Schematic Sheet - Sound. U and (optionally) U are the source of Sound Channel & respectively with the audio output being pin 0, Aout. These OKI MSM devices are bit ADPCM D-A converters capable of running at sample rates of KHz, KHz, KHz or KHz. This rate is selected by software by setting levels on the S and S pins. On Channel (U) these pins are controlled by the OP and OP lines from the MC0 Serial Module. On Channel (U) these pins are controlled by the PORTA and PORTA lines from the MC0 SIM0 Module. The VCK- output from the MSM is a square wave at the sampling frequency selected by S and S. The MSM reads the bit sample immediately after the rising edge of VCK-. The VCK- from the MSM is connected to the FPGA where it is divided by to produce a DMA Request signal to the processor. Sound data is transferred, a byte at a time ( byte = * bit sound samples), to the appropriate register within the FPGA by the DMA Module if a sound is being played. The FPGA in turn presents alternately the high and low nibble to the MSM OKI chip. The sound channel requests a byte of data (via the FPGA) at half the sound sample rate. E.g., if the MSM has been set to run at KHz sample rate, the FPGA will issue DMA requests at KHz. These requests are issued continuously to the DMA Module, but in times of silence, the DMA channels are inactive and therefore no new data is transferred into the FPGA sound register. In this case, the user must ensure that the last data written to the FPGA sound register before a period of silence is 0x0. This will ensure that, during a silent period, the MSM is being continuously fed a repeated sequence of alternate 0x and 0x0 nibbles. This keeps the ADPCM converter in its quiescent state. If the sound data is generated using the Heber Sound Solutions software, the last byte of the data is always 0x0, so this condition will automatically be satisfied. Sound Channel (U) is fitted as standard and uses DMA Channel. Sound Channel (U) is optional and uses DMA Channel. The RESET pin of each channel is under individual software control. Pin PORTA0 drives SFX Channel # RESET. Pin PORTA drives SFX Channel # RESET. After Power Up, these pins will default to being inputs and therefore the Resistor network N will pull them High, holding both Sound Channels in a RESET state. Before the Sound Channels can be used, these two pins must be set as outputs by the SIM0.. Stereo Amplifier and Volume Controls The Stereo Amplifier is shown on Schematic Sheet - Sound. U is a Philips TDA0AQ Stereo Audio Amplifier with independent DC volume controls. Note that the loudspeaker outputs, on Connector P0, are bridge driven so neither of the loudspeaker wires may be connected to Gnd. The DC volume controls of the TDA0 work over the range 0.V(min) to.v (Max). The variable duty cycle outputs on pins TOUT/ from the two timers in the MC0 Timer Module are integrated by the combination of two K resistors and a µf capacitor (R0, R0, C on Channel : R0, R, C on Channel ) to provide the control voltage needed. The control voltage is given by the formula.*{duty cycle} where duty cycle is the proportion of the time that the TOUT Pin is HIGH. Normally, Sound Channel (U, DMA Channel ) feeds Amplifier Section (volume control - Timer Channel ) driving LS. Sound Channel (U, DMA Channel ) feeds Amplifier Section (volume control Timer Channel ) driving LS. A pin on the Loudspeaker Connector, P0, pin, which allows the output signal from Amplifier Channel to be fed back into the input of Amplifier Channel. This allows various alternative modes Document No. 0- Issue

24 Page of operation, for example, if only Sound Channel is fitted, then by linking the LS+ output to the feedback pin, the same signal can drive BOTH loudspeakers. See Section., Making Sounds below for a more detailed explanation of the different operational modes that are possible.. Serial P provides connections to RS Channel A, Data Receive & Transmit plus RTS/CTS. P provides connections to RS Channel B, Data Receive & Transmit plus RTS/CTS and is in the format specified by the BACTA standard. Operation of the above two ports is determined by the operation of the Serial Module in the MC0 Processor. Refer to the Serial Module Section of Motorola MC0 User Manual for a full explanation..0 Internal I C Bus An internal I C Bus is implemented using SIM0 Lines PORTA (SCL) and PORTA (SDA). This bus allows the processor to read and write the optional Real Time Clock chip, U0, and the optional E PROM, U. If neither of these devices is fitted, then these lines are also available on the Expansion Connector P and are free for other uses..0. Real Time Clock U0 is a position that accepts a Philips PCF I C Real Time Clock. The standard Pluto Controller has a socket fitted in this position along with the.khz Crystal, X. However, the PCF IC is NOT fitted as standard but is available as an optional extra or may be fitted by the user. The I C Slave Address of the RTC is as follows: Table. I C Slave Addresses for RTC, U0 READ: WRITE: 0xA 0xA0.0. E PROM U position is fitted with a socket that accepts an Industry Standard E PROM, C0 ( bytes) or C0 (0 bytes) with pin, which serves a different function on devices from different manufacturers, connected to. The Pluto Controller Boards, as standard, do not have an E PROM fitted but they are available as an optional extra or may be fitted by the user. We strongly recommend that, if a user supplies or fits his own devices, that only NMC0 or NMC0 devices should be used (manufactured by Fairchild or National Semiconductor). Heber cannot offer Technical Support for the use of devices from alternate manufacturers. To avoid a clash of I C addressing between the PCF RTC and the Cnn E PROM, A (Pin ) of the E PROM is strapped to Vcc and A0/A to and this socket is restricted to accepting devices no larger than the C0. Note, however, that there is no such size restriction on the devices that may be connected via P, the External I C Bus Connector. The I C Slave Address of each of the byte Page Blocks in the E PROM, U, is as follows: Table. I C Slave Addresses for E PROM, U BLOCK 0 C0 or C0 BLOCK C0 or C0 BLOCK C0 only BLOCK C0 only READ 0xA 0xAB 0xAD 0xAF WRITE 0xA 0xAA 0xAC 0xAE Document No. 0- Issue

25 Page 0 MACHINE OPERATION This section discusses how various standard amusement machine functions can be implemented.. Driving Reels Up to six V Stepper Motor Reel Mechanisms may be connected to the REEL connector, P. +V outputs are available for the motor common connection and /Vcc are available for the Opto supply. A * subset of the Lamp Multiplex is configured so up to lamps per reel may be accommodated, in either sinking or sourcing mode (depending on the wiring of the Reel Mechanism. inputs, IP0-, are provided for the Opto Inputs When driving stepper motor reels, because the maximum (static) current load of each winding is 00mA (assuming 0Ω, V windings), it is important to connect the motors to distribute the load evenly amongst the TPIC driver chips. The recommended method of connection is to wire the reel motors as follows: Table. Recommended Reel Stepper Motor Drive Connections REEL REEL REEL REEL REEL REEL OP0- OP- OP- OP- OP- OP0- This guarantees that a maximum of motor windings are driven simultaneously by any one TPIC device which is within the ratings of the device even under the worst case of a reel being stationary and unchopped. Of course, when the motor is running or is being chopped the average current drops significantly. Extra reels could be connected via pins on the other connectors. Providing the software chops the current to the reels when they are not spinning, an extra reels can be wired to OP- and OP- and should allow the TPICs to remain within their ratings. NB: The +V outputs on P Pins -0 are fed directly from the +V Input to the Pluto Board on P, Pin. It does not go via Fuse F on the board.. Reading the DIL Switches The state of the DIL Switches may be read at any time by reading the memory locations as described in Section... Reading the Switch Inputs The switch inputs may be read at any time by reading the memory locations as described in Section. above. In most applications, these inputs should be debounced in software. A typical debounce algorithm might be to read the switches every ms, but only register a change of state on the input after it has been stable for consecutive readings. It is possible to implement, say, a multiplexed switch input array by using, of the Open Drain Outputs OP0- as strobes and of the Inputs IP0-. In this case, a diode would need to be connected in series with each switch. Document No. 0- Issue

26 Page. Interfacing to Coin & Note Acceptors Most Coin or Note Acceptors have open collector ( sink to ground ) outputs. These may be connected directly to any of the Pluto Inputs (IP0-). Mechanism Enable or Control inputs may usually be driven directly from any of the Pluto Open Drain Output lines (OP0-).. Interfacing to Coin Payout Mechanisms Payout Hoppers that require relatively low drive currents, e.g. Coin Controls Universal Hopper, may be driven directly from an Open Drain Output. Higher current devices, such as 0Vac or Vdc Payout Solenoids, should be driven using Open Drain Outputs via a suitable Triac or Relay Interface Card. Heber produces a number of suitable interfaces.. Driving Vacuum Fluorescent Displays (VFD) The standard VFD/Linewriter display used in most Gaming/Amusement Machines is driven by TTL level signals, Clock, Data and Reset. Connector P has TTL level outputs which could drive up to display modules. The mapping of these outputs as the LSB of bytes makes it convenient for the software to implement the bitwise drive required.. Using the External I C Bus Connector P is intended for driving external boards containing I C Bus components. A common use for this could be the provision of a removable E PROM Module for use in Spain or any other country with a similar requirement. Heber have available a small PCB containing a NMC0 or NMC0 E PROM that plugs directly on to P. On this connector, the SDA line is driven by the Open Drain Output, AUX and may be read by the 0 Timer Module as the (inverted) TGATE- signal. Similarly, the SCL line is driven by AUX and read by TGATE.. Driving Meters Electromechanical Meters or Counters should be V DC parts. The common +V supply to them should be the Vmeter+ supply from Connector P ( ), pin B and each should be driven by an Open Drain Output (OP0-). As the meter is pulsed ON, the software should check that the Vmeter Current Sense Input has operated, i.e. that pin PORTB has gone high. Because of possible delays in responding to a meter being turned on it is recommended that the software checks the current sense pin immediately before the meter is turned OFF at the end of a pulse. To detect tampering or a failure of the current sense circuitry, the software should also check that the current sense pin goes LOW when no meter is operated.. Making Sounds Loudspeaker outputs on connector P0 are bridge driven, so do NOT connect either connection of a loudspeaker to ground or to any other loudspeaker drive. Ideally Ω loudspeaker(s) should be used, but higher impedance components could be used without any risk of damage to the amplifier. The use of or ohm loudspeakers should be avoided. Document No. 0- Issue

27 Page It is possible to run the sound in the following modes:.. Single Channel/Single Speaker (Mono) Mode This is the lowest cost option, using the standard Pluto Board with a single loudspeaker. The optional SFX Channel, U, is not fitted and only SFX Channel, U, is operational. A single loudspeaker is connected to LS pins ( & ) only. Pins,, should be left open... Dual Channel/Dual Speaker (Stereo) Mode In Stereo Mode, the optional second channel IC U is fitted and loudspeakers are used, connected to LS and LS pins. Pin is left open. Channel Volume Control will adjust the level of LS, Channel Volume Control will adjust the level of LS. In this mode true stereo sound effects may be reproduced, although the subjective effect heard by the player will depend upon the placement of the loudspeakers in the cabinet... Known DMA Problems The E version of the Motorola 0 mask that is current at the time of this manual being written (MC0PVE, Mask # GF) exhibits a DMA fault which can cause audible disturbances on a sound effect. This disturbance occurs when the memory area being transferred to the SFX Register in the FPGA includes the hexadecimal address range xxx FFxx. (x meaning any hexadecimal digit). Thus, to avoid this problem occurring, precautions should be taken when linking sound effect modules Into the final EPROM map. We suggest that, programme and EPROM size permitting, the area from hex to 000 FFFF (Kbytes) be reserved for the executable portion of the code, with sound effects commencing at hex address If the total EPROM size exceeds Mbyte, then no sound effect should include data in the range 00 FF00 to 00 FFFF. Similarly, with larger EPROM maps, regions at 00 FFxx, 00 FFxx, etc should also be avoided. There is NO problem with code execution in these areas, the only difficulty occurs when a Sound DMA transfer passes through these regions. We believe that these problems are reduced or eliminated when the Function Code Register (FCR) in the DMA Module is initialised to value 0xDD..0 Using Multiplexed Lamps On all Multiplex lamp outputs, the Column Drives, LC0-, SINK current to ground and the Row Drives, LR0-, SOURCE current from the Lamp Supply (+V or +V). Thus, any lamps should be connected between a Row and a Column drive with their series diodes orientated with the cathode towards the Column Drive. The choice of operation at V or V is determined by the Power Supply and the software. When running at V, the software will sequentially drive all Columns, LC0-, on a / duty cycle, each column being ON for ms and OFF for. When running at V, the software will sequentially drive only the first Columns (LC0-) on a / duty cycle, each column being ON for ms and OFF for. The Lamp Multiplex Drive Circuitry is designed to drive V, 00mA bulbs. However, it is permissible for a small number (up to ) of positions to drive either a higher power bulb (V, 0ma) or a pair of 00mA bulbs. These "high load" positions should be arranged such that no more than one is on any one Row or Column drive.. Using Multiplexed LEDs The multiplexed LED drive circuit is intended to be used with Common Cathode digits, either segment plus decimal point or segment. The common cathode connection of each digit should be Document No. 0- Issue

28 Page connected to a digit drive output, DIG0-, on connector P. Each digit drive output can drive two Segment Digits, the segment anodes for one connecting to drive SEG0- and the other to SEG-. By convention, segment a would connect to SEG0 or SEG. Alternatively, segment starburst digits can be used, in which case each digit output would drive one digit and the segment anodes should each be connected to one of the segment drive lines, SEG0-. The LED Digit drive circuitry shares the same Current Sink transistors as the Lamp Column drives. Thus, if the system is being driven in a / duty cycle to allow a V Lamp Supply, only Digit drive lines DIG0- are active (or the board is a Pluto /). In this case only Seven Segment LED digits may be driven from the controller.. Using the Multiplex Expansion Connector The outputs on P are all CMOS signals swinging between and +V. These signals may be connected to Pluto Multiplex Expansion Boards to increase the Lamp and/or LED drive capability of the system. See the PLUTO MULTIPLEX EXPANSION BOARD USER MANUAL for details of connection and operation.. Adding Video Capabilities A Calypso Video Card is available from Heber Ltd. which plugs directly onto the Pluto board via the DIN connectors P and P. See the CALYPSO USER MANUAL for details. The Calypso Video Card supersedes the Pluto CGA/VGA Video Card. For further information on the Pluto CGA/VGA Video Card refer to the PLUTO CGA/VGA BOARD USER MANUAL. Document No. 0- Issue

29 Page SOFTWARE DEVELOPMENT A number of options exist for the development and debug of software for use on Pluto. Software will normally be generated using a Cross Assembler, Cross Compiler and Linker package. A suitable package is included with the Pluto Development Kit. When software has been successfully compiled, assembled and linked, it may be tested and debugged using the Background Debug Mode facility built in to the 0 Processor. For full details of debugging, refer to the PLUTO DEVELOPMENT KIT QUICK START GUIDE and other documentation supplied with the Development Kit. Document No. 0- Issue

30 Page CONNECTOR TYPES AND PIN OUTS. Schedule of Connector Types There are two types of Pluto Board with either Ultrex or Box Header connectors, and other families of connectors: Pluto with Ultrex connectors is referred to as Pluto U Pluto with Box Header connectors is referred to as Pluto B Pluto U uses the following different families of connectors for connection to the cableform in the machine: AMPMTA-00..mm single in-line headers with friction lock and polarisation. AMP MTA-..mm single in-line headers with friction lock and polarisation. AMP Ultrex..mm dual row headers. way D Type Pluto B uses the following different families of connectors for connection to the cableform in the machine: AMPMTA-00..mm single in-line headers with friction lock and polarisation. AMP MTA-..mm single in-line headers with friction lock and polarisation. Tyco Box Header.mm dual row headers way D Type The actual part numbers of the board headers fitted to the Pluto PCBs along with the part numbers of suitable mating (cableform) parts are given in the following tables: Table. AMP Ultrex Connector Part Numbers Ident Description PCB Header AMP Part No. AMP IDC Connector Part Number - AWG Wire P W Ultrex P 0W Ultrex P 0W Ultrex P W Ultrex Table. Tyco Box Header Connector Part Numbers Ident Description PCB Header Tyco Part No. Tyco IDC Connector Part Number - AWG Wire P W Box Header P 0W Box Header P 0W Box Header P W Box Header Document No. 0- Issue

31 Page Ident Description PCB Header AMP Part No. Table. AMP MTA-00 Connector Part Numbers AMP IDC Connector Part Number AWG (0.mm ) (Colour Natural) P W MTA P W MTA P W MTA P0 W MTA P W MTA P W MTA P W MTA AWG Wire(0.mm ) (Colour Red) Table. AMP MTA- Connector Part Numbers Ident Description PCB Header AMP Part No. AMP IDC Connector Part Number AWG (0.mm ) (Colour Natural) P W MTA AWG Wire(0.mm ) (Colour Yellow) The above MTA-00 and MTA- IDC Connector Part Numbers are for illustration and are of the Feed-Through Receptacle without Polarising Tabs type. A number of alternatives exist that could also be used, for example Closed-End types. Please consult the relevant AMP information for an exhaustive list. If you have Internet Access, the information is also available on the AMP Web Site at Strain relief covers are also available.. P RS Channel A Reference: Type: Description: P Header W AMP MTA-00 RS Channel A RXA Input to Pluto TXA Output from Pluto CTSA Input to Pluto RTSA Output from Pluto +V Document No. 0- Issue

32 Page. P Dataport (RS Channel B) Reference: Type: Description: P W D Socket BACTA Dataport / RS Channel B nc RXB (Input to Pluto ) TXB (Output from Pluto ) CTSB (Input to Pluto) RTSB (Output from Pluto ) nc nc nc nc 0 -V nc nc nc nc nc nc nc 0 nc nc nc nc nc +V. P Power Input Reference: Type: Description: P Header W AMP MTA- Power -V Neg supply for RS buffers Ground Ground +V Main supply Ground Vmpx+ Lamp MPX supply, +V or +V Document No. 0- Issue

33 Page. P Multiplexed Lamp Sinks Reference: Type: Description: P Header W AMP MTA-00 Lamp Columns/Sinks LC0 Lamp Column/Sink 0 LC Lamp Column/Sink LC Lamp Column/Sink LC Lamp Column/Sink LC Lamp Column/Sink LC Lamp Column/Sink LC Lamp Column/Sink LC Lamp Column/Sink LC* Lamp Column/Sink (PLUTO / only) 0 LC* Lamp Column/Sink (PLUTO / only) LC0* Lamp Column/Sink 0 (PLUTO / only) LC* Lamp Column/Sink (PLUTO / only) LC* Lamp Column/Sink (PLUTO / only) LC* Lamp Column/Sink (PLUTO / only) LC* Lamp Column/Sink (PLUTO / only) LC* Lamp Column/Sink (PLUTO / only) nc No Connection nc No Connection * Column Sinks LC- are omitted on Pluto /. P Ultrex Multiplexed LEDs Reference: Type: Description: P Header W AMP Ultrex LED - Drive for or seven-segment LED Digits. Cathodes, Digit 0 DIG0 A B DIG Cathodes, Digit Cathodes, Digit DIG A B DIG Cathodes, Digit Cathodes, Digit DIG A B DIG Cathodes, Digit Cathodes, Digit DIG A B DIG Cathodes, Digit Cathodes, Digit DIG A B DIG Cathodes, Digit Cathodes, Digit 0 DIG0 A B DIG Cathodes, Digit Cathodes, Digit DIG A B DIG Cathodes, Digit Cathodes, Digit DIG A B DIG Cathodes, Digit Anodes, Segment 0 SEG0 A B SEG Anodes, Segment Anodes, Segment SEG A0 B0 SEG Anodes, Segment Anodes, Segment SEG A B SEG Anodes, Segment Anodes, Segment SEG A B SEG Anodes, Segment Anodes, Segment SEG* A B SEG* Anodes, Segment Anodes, Segment 0 SEG0* A B SEG* Anodes, Segment Anodes, Segment SEG* A B SEG* Anodes, Segment Anodes, Segment SEG* A B SEG* Anodes, Segment * Common Cathode Drives DIG- are omitted on Pluto / Document No. 0- Issue

34 Page. P Box Header Multiplexed LEDs Reference: Type: Description: P Header W Tyco Box Header LED - Drive for or seven-segment LED Digits. Not Used Not Used Cathodes, Digit 0 DIG0 DIG Cathodes, Digit Cathodes, Digit DIG DIG Cathodes, Digit Cathodes, Digit DIG DIG Cathodes, Digit Cathodes, Digit DIG 0 DIG Cathodes, Digit Cathodes, Digit DIG DIG Cathodes, Digit Cathodes, Digit 0 DIG0 DIG Cathodes, Digit Cathodes, Digit DIG DIG Cathodes, Digit Cathodes, Digit DIG DIG Cathodes, Digit Anodes, Segment 0 SEG0 0 SEG Anodes, Segment Anodes, Segment SEG SEG Anodes, Segment Anodes, Segment SEG SEG Anodes, Segment Anodes, Segment SEG SEG Anodes, Segment Anodes, Segment SEG* SEG* Anodes, Segment Anodes, Segment 0 SEG0* 0 SEG* Anodes, Segment Anodes, Segment SEG* SEG* Anodes, Segment Anodes, Segment SEG* SEG* Anodes, Segment * Common Cathode Drives DIG- are omitted on Pluto /. P Multiplexed Lamps Sources Reference: Type: Description: P Header W AMP MTA-00 Lamp Rows/Sources LR0 Lamp Row/Source 0 LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source 0 LR Lamp Row/Source LR0 Lamp Row/Source 0 LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source LR Lamp Row/Source Document No. 0- Issue

35 Page 0. P Ultrex Reels Reference: Type: Description: P Header 0W AMP Ultrex Reels - Connector for Stepper Motor Reel Mechanisms Lamp Column 0 LC0 A B LC Lamp Column Lamp Column LC A B LC Lamp Column Lamp Column LC A B LC Lamp Column Lamp Row 0 LR0 A B LR Lamp Row Lamp Row LR A B LR Lamp Row Lamp Row LR A B LR Lamp Row A B Open Drain Output 0 OP0 A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A0 B0 OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output 0 OP0 A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output 0 OP0 A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Input 0 IP0 A0 B0 IP Input Input IP A B IP Input Input IP A B IP Input +V A B +V +V A B +V +V A B +V Document No. 0- Issue

36 Page.0 P Box Header Reels Reference: Type: Description: P Header 0W Box Header Reels - Connector for Stepper Motor Reel Mechanisms Lamp Column 0 LC0 LC Lamp Column Lamp Column LC LC Lamp Column Lamp Column LC LC Lamp Column Lamp Row 0 LR0 LR Lamp Row Lamp Row LR 0 LR Lamp Row Lamp Row LR LR Lamp Row Open Drain Output 0 OP0 OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP 0 OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output 0 OP0 OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP 0 OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output 0 OP0 OP Open Drain Output Open Drain Output OP OP Open Drain Output Input 0 IP0 0 IP Input Input IP IP Input Input IP IP Input +V +V +V +V +V 0 +V Document No. 0- Issue

37 Page. P Ultrex General # Reference: P Type: Header 0W AMP Ultrex Description: General Purpose # Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output 0 OP0 A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output 0 OP0 A B OP Open Drain Output Open Drain Output OP A0 B0 OP Open Drain Output Open Drain Output OP A B OP Open Drain Output Open Drain Output OP A B OP Open Drain Output A B Input 0 IP0 A B IP Input Input IP A B IP Input Input IP A B IP Input Input IP A B IP Input Input IP A B IP Input Input 0 IP0 A B IP Input +V A0 B0 +V Document No. 0- Issue

38 Page. P Box Header General # Reference: P Type: Header 0W Box Header Description: General Purpose # Open Drain Output OP OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output 0 OP0 OP Open Drain Output Open Drain Output OP 0 OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output 0 OP0 OP Open Drain Output Open Drain Output OP 0 OP Open Drain Output Open Drain Output OP OP Open Drain Output Open Drain Output OP OP Open Drain Output Input 0 IP0 IP Input Input IP 0 IP Input Input IP IP Input Input IP IP Input Input IP IP Input Input 0 IP0 IP Input +V 0 +V Document No. 0- Issue

39 Page. P Ultrex General # Reference: P Type: Header W AMP Ultrex Description: General Purpose # Open drain Output OP A B OP Open drain Output Open drain Output 0 OP0 A B OP Open drain Output Open drain Output OP A B OP Open drain Output Open drain Output OP A B OP Open drain Output Open drain Output OP A B OP Open drain Output Open drain Output OP A B OP Open drain Output Open drain Output 0 OP0 A B OP Open drain Output Open drain Output OP A B OP Open drain Output A B Input IP A0 B0 IP Input Input IP A B IP Input Input 0 IP0 A B IP Input Input IP A B IP Input Input IP A B IP Input Input IP A B IP Input Input IP A B IP Input +V A B Vmeter Current Sensing +V. P Box Header General # Reference: P Type: Header W Box Header Description: General Purpose # Open drain Output OP OP Open drain Output Open drain Output 0 OP0 OP Open drain Output Open drain Output OP OP Open drain Output Open drain Output OP OP Open drain Output Open drain Output OP 0 OP Open drain Output Open drain Output OP OP Open drain Output Open drain Output 0 OP0 OP Open drain Output Open drain Output OP OP Open drain Output Input IP 0 IP Input Input IP IP Input Input 0 IP0 IP Input Input IP IP Input Input IP IP Input Input IP 0 IP Input Input IP IP Input +V Vmeter Current Sensing +V Document No. 0- Issue

40 Page. P0 Loudspeakers Reference: Type: Description: P0 Header W AMP MTA-00 Loudspeakers LS+ Loudspeaker, Channel LS- Loudspeaker, Channel MIX Channel mixer input LS+ Loudspeaker, Channel LS- Loudspeaker, Channel WARNING: Loudspeaker outputs are bridge driven and must NOT be connected ground.. P Multiplex Expansion Reference: Type: Description: P Header W AMP MTA-00 Multiplex Expansion MPX_DATA_A V CMOS Output MPX_DATA_A V CMOS Output MPX_STR_A V CMOS Output MPX_STR_B V CMOS Output MPX_CLK V CMOS Output MPX_STR V CMOS Output MPX_OE V CMOS Output. P Aux Outputs Reference: Type: Description: P Header W AMP MTA-00 Aux. Outputs AUX0 Open drain output, 0mA, K pull-up to +V AUX Open drain output, 0mA, K pull-up to +V AUX Open drain output, 0mA, K pull-up to +V AUX Open drain output, 0mA, K pull-up to +V AUX Open drain output, 0mA, K pull-up to +V AUX Open drain output, 0mA, K pull-up to +V +V Document No. 0- Issue

41 Page. P External I C Bus Reference: Type: Description: P Header W AMP MTA-00 External I C Bus AUX/SDA IC SDA line, TTL Open Collector, K Pull-up AUX/SCL IC SCL line, TTL Open Collector, K Pull-up +V. P IO Expansion Card Connector Reference: Type: Description: P DIN, C/ Vertical Plug Connector for IO Expansion Boards c b a D PORTA0 HALT- D PORTA CLKOUT D0 PORTA CS- D PORTA RESET- D PORTA BERR- D PORTA A0 D A A D AS- A RXDA- (TTL) DS- A 0 TXDA- (TTL) R/W- A CTSA- (TTL) DSACK0- A RTSA- (TTL) DSACK- +V A0 SIZ0 A SIZ A PB A PB Document No. 0- Issue

42 Page.0 P Memory Expansion Card Connector Reference: Type: Description: P DIN, C/ Socket Vertical Connector for Memory Expansion Boards a b c A A A A A A A0 A A A A A A A A A A A A A0* FPGA0 A D 0 FPGA D D FPGA D D FPGA D0 D FPGA D D FPGA D D FPGA D D D0 D D * NB. - Pin c, A0 is in fact the connection to Pin (ROM_P) of the on-board EPROMs, U & U, and is driven by the FPGA. For all memory accesses, excluding those to the ROM/EPROM area mapped by CS0-, the FPGA routes A0 to this pin. For all memory accesses to the ROM/EPROM area mapped by CS0-, the FPGA routes either Vcc, A or A0 to this pin, depending on the memory mode set in the FPGA. See Section., EPROM Sockets / EPROM Autoselect Feature for details of operation.. P Background Debug Mode Connector Reference: Type: Description: P 0W Low Profile Header Background Debug Mode Connector Only fitted to Software Development Boards DS- BERR- BKPT FREEZE RESET- IFETCH 0 IPIPE Document No. 0- Issue

43 Figure - Schematic Sheet - Root Sheet Page SHT - +V /CURRENT SENSE RESET- CS_OP- D[0..] A[0..] SHT - OPEN DRAIN OUTPUTS RESET- CS_OP- D[0..] A[0..] OP[0..] SEL[0..] OP[0..] SHT - CONNECTORS OP[0..] IP[0.. ] METER_SENSE VREF NMI- MPX_REF MPX_REF PORTA [0..] SFX_CLK METER_SENSE VREF NMI- MPX_REF MPX_REF PORTA [0..] SFX_CLK CS_IP- D[0..] 0_ SHT - INPUTS/DIL SW CS_IP- D[0..] SEL[0..] IP[0.. ] SEL[0..] IP[0.. ] CS_TTL- AS- DS- R/W- DSA CK0 - DSA CK - SIZ0 SIZ CS_TTL- AS- DS- R/W- DSA CK0 - DSA CK - SIZ0 SIZ SHT - MC0 CPU R/W- SIZ0 DSA CK0- EXTA L.MHZ CS0- CS- CS- CS- CLKOUT DREQ- DREQ- D[0..] DSA CK- SIZ A[0..] METER_SENSE NMI- POP POP TOUT TOUT HA LT- BERR- CTSA - RTSA - CTSB- RTSB- RXDA TXDA RXDB TXDB RESET- PB0 PB PB R/W- SIZ0 DSACK0 - EXTA L.MHZ CS0- CS- CS- CS- CLKOUT DREQ- DREQ- RESET D[0..] DSACK - SIZ A[0..] METER_SENSE NMI- PORTA [0..] POP POP TOUT TOUT HA LT- BERR- CTSA - RTSA - CTSB- RTSB- RXDA TXDA RXDB TXDB RESET- PB0 PB PB 0_ SHT - EPROM/RAM RAM_CS- RAM_WL- A[0..] RAM_WU- RAM_OE- D[0..] ROM_P ROM_OE- FPGA [0..] ROM_P 0_ FPGA [0..] SHT - LED SEG DRIVES MPX_CLK MPX_STR MPX_OE MPX_DATA_A MPX_STR_DATA_A MPX_DATA_A MPX_D_V CLK_V STR_V MPX_C_V OE_V MPX_A_V MPX_B_V STR_A_V SEG[0.. ] 0_D SHT - COL/DIG SINKS CLK_V SEG[0.. ] STR_V OE_V STR_A_V LC[0..] MPX_REF MPX_REF 0_B SHT - LAMP ROW SOURCES CLK_V MPX_B_V STR_V MPX_C_V OE_V MPX_D_V MPX_A_V LR[0..] 0_ SHT - FPGA R/W- CS_OP- SIZ0 CS_IP- DSACK0 - CS_TTL- EXTA L RA M_ WL-.MHZ RA M_ WU- CS0- RAM_OE- CS- ROM_ P CS- ROM_ OE- CS- ROM_P CLKOUT DREQ- DREQ- FPGA[0..] RESET SFX_VCK MPX_CLK MPX_STR D[0..] MPX_OE MPX_DATA_A MPX_DATA_A MPX_STR_DATA_A SFX_D[0..] SFX_D[0..] SFX_VCK A[0..] SFX_CLK 0_ SHT - SOUND SFX_CLK PORTA [0..] SFX_VCK POP SFX_D[0..] POP TOUT SFX_D[0..] TOUT SFX_VCK 0_ SHT 0 - RESET/BATT/RS/IC CTSA - VREF RTSA - CTSB- RAM_CS- RTSB- RXDA RESET TXDA RXDB TXDB RESET- PB0 PORTA [0..] CS_OP- CS_IP- CS_TTL- MPX_CLK MPX_STR MPX_OE MPX_DA TA_ A MPX_DA TA_ A MPX_STR_DATA_A SFX_CLK SFX_VCK SFX_D[0..] SFX_D[0..] SFX_VCK VREF RAM_CS- RESET PORTA [0..] RA M_ CS- A[0..] D[0..] SEG[0..] LC[0..] MPX_REF MPX_REF LR[0..] CS- CLKOUT RXDA TXDA CTSA - RTSA - RESET- D[0..] A[0..] PORTA [0..] TGA TE- TGA TE- PB PB BERR- HA LT- CS- CLKOUT RXDA TXDA CTSA - RTSA - RESET- D[0..] A[0..] PORTA [0..] TGA TE- TGA TE- PB PB BERR- HA LT- LC[0..] MPX_B_V MPX_C_V MPX_D_V LR[0..] PORTA [0..] PORTA [0..] 0_C 0_ SEL[0..] AS- DS- FC TGATE- TGATE- AS- DS- FC TGATE- TGATE- 0_A 0_. Belvedere Mill Chalford, Stroud Gloucestershire GL NT Tel: Fax: 0 0 Title PLUTO - ROOT SHEET, -00 Size Document Number Rev A -0 r Date: Monday, August, 00 Sheet of Document No. 0- Issue

44 Figure - Schematic Sheet - CPU Page PP PP PP PP PP PP PP PP IEEE. ACCESS TCK TMS TDI TDO IPIPE IFETCH FREEZE BKPT BERR- BACKGROUND DEBUG CONNECTOR P 0 RESET- DS- AS- R/W- BERR- BKPT TCK BR- BGACK- HA LT- N PB0 METER_SENSE PB PB PB DONE- DONE- RESET- N U LOW PROFILE HDR 0W FITTED FOR DEV. ONLY K* SIL K* SIL,,,, 0 TP PA D DSA CK0- DSA CK- TP0 PA D DREQ- TP PA D CLKOUT,0,0,0, DSACK0 - DSACK - BERR- HA LT- RESET- AS- DS- R/W- SIZ0 SIZ CS0- RXDA TXDA CTSA - RTSA - POP POP TGA TE- TOUT TGA TE- TOUT CLKOUT PP PP PP BR- BG- BGACK- 0 PB0 CS- CS- METER_SENSE, CS- PB PB NMI- PB0 CS- CS- METER_SENSE CS- PB PB PB CS0- RXDA TXDA CTSA - RTSA - POP POP RXDB TXDB CTSB- RTSB- TOUT TOUT PP PP PP DREQ- RXDB TXDB CTSB- RTSB- DONE- R0 0R.MHz R0 0R BERR- HA LT- RESET- AS- DS- R/W- SIZ0 SIZ FC0 FC FC FC AS DS R/W SIZ0 SIZ DSA CK0 DSA CK BERR HA LT RESET BR BG BGACK RMC MODCK/PB0 CS/IRQ/PB CS/IRQ/PB IRQ/PB CS/IRQ/PB IRQ/PB IRQ/PB IRQ/PB CS0/AVEC RXDA TXDA CTSA RTSA /OP0 RXRDYA /OP TXRDY A/OP RXDB TXDB CTSB RTSB/OP TGA TE TIN TOUT TGA TE TIN TOUT DREQ DA CK DONE CLKOUT TCK TMS TDI TDO BKPT FREEZE IPIPE IFETCH D0 D D D D D D D D D D0 D D D D D A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A/PA0 A/PA/IACK A/PA/IACK A/PA/IACK A/PA/IACK A/PA/IACK A0/PA/IACK A/PA/IACK DREQ DA CK DONE 0 0 D0 D D D D D D D D D D0 D D D D D A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A PORTA 0 PORTA PORTA PORTA PORTA PORTA PORTA PORTA DREQ- DONE- D[0..] A[0..] LD R RESET- RED K UF LD R PORTA GREEN K HC SW PORTA ON-BOARD PUSHBUTTON SW PUSHBUTTON PORTA [0..] PORTA[0..],,,0 N PORTA 0 PORTA PORTA PORTA PORTA PORTA PORTA PORTA K* SIL D0 D D D D D DREQ- D D D[0..],,,, A[0..],,, RESET L ED SOFTWAR E CONTROL LED LED A0 A A A A A A A N0 A A A0 A A A A A K* SIL N K* SIL N K* SIL EXTA L TP PA D EXTA L.KHz LC EMC FILTER 0 EXTA L XTAL V CCSYN C XFC PP X X SCLK.MHZ 0 MC0PV.MHZ TP PA D N D A D A D0 A D A D A0 D A D A D A K* SIL N K* SIL 00n PP C 00n., -00 C 00n C 00n C 00n C 00n C 00n C0 00n C 00n C 00n Belvedere Mill Chalfor d, Str oud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - CPU Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

45 Figure - Schematic Sheet - FPGA Page 0 R/W-, DSACK0 - SIZ0 0 RESET CS0- CS- CS- CS-,,,, D[0..] D[0..] CS_OP- CS_IP- RA M_ WL- RA M_ WU- RA M_ OE- ROM_ OE- ROM_ P D D D0 D D D FPGA [0..] FPGA [0..] A[0..] A[0..] A0 A A A A A A A A A0 A A A D D NC MODE (CLK) U 0 0 FPGA 0 FPGA FPGA FPGA FPGA FPGA FPGA SFX_D0 SFX_D SFX_D SFX_D FPGA 0 FPGA FPGA FPGA FPGA FPGA FPGA N K* SIL SFX_D[0..] SFX_VCK CS_TTL- SFX_D[0..] SFX_VCK CS_TTL- FPGA 0 0 SFX_D[0..] SFX_D[0..] SFX_D0 SFX_D SFX_D SFX_D ROM_ P ROM_ P SFX_VCK, SFX_CLK DREQ- DREQ-.MHZ EXTA L CLKOUT MPX_OE MPX_CLK MPX_STR MPX_DATA_A MPX_DATA_A MPX_STR_DATA_A R0 0M X R0.MHz C p 0R C p C 00n C 00n C 00n C 00n. Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - FPGA, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

46 Figure - Schematic Sheet - Memory Page,,,, D[0..] A[0..] D[0..] A[0..] ROM_ P ROM_ P VBATT VBATT ROM_ P ROM_ OE- A A A A A A A A A A0 A A A A A A A A ROM_ P ROM_ OE- 0 0 U A0 A A A A A A A A A A0 A A A A A A A A VPP OE CE D0 D D D D D D D 0 D0 D D D D D D D C 00n ROM_ P ROM_ OE- A A A A A A A A A A0 A A A A A A A A ROM_ P ROM_ OE- 0 0 U A0 A A A A A A A A A A0 A A A A A A A A VPP OE CE D0 D D D D D D D 0 D D D0 D D D D D C 00n 0 RA M_ WL- RA M_ CS- RA M_ OE- A A A A A A A A A A0 A A A A A 0 0 A0 A A A A A A A A A A0 A A A A WR CE OE VDD O0 O O O O O O O U D0 D D D D D D D VBATT C0 00n HMBLFP RA M_ WU- 0 RA M_ CS- RA M_ OE- A A A A A A A A A A0 A A A A A 0 0 A0 A A A A A A A A A A0 A A A A WR CE OE VDD O0 O O O O O O O U VBATT D D D0 D D D D D C 00n HMBLFP EPROM EPROMS - *C00 OR *C0 EPROM U/U - K* STATIC RAMS, SOP PINS, SET BY FPG A CS0- MODE ROM_P ROM_P 0 READ *C00 A0 0 READ *C00 A 0 READ *C0 A A0 0 READ *C0 A0 A NON-ROM CYCLE A0 A0/A x RESET MEMORY EXPANSION CONNECTOR A[0..] A[0..] A A A A FPGA 0 FPGA FPGA FPGA FPGA FPGA FPGA D0 A A A A A A A A A A0 A A A A A A PA A A A A A A A A A A0 A A A A A A A A A A A A A A A D D D0 D D D D B B B B B B B B B B0 B B B B B B PB B B B B B B B B B B0 B B B B B B ROM_ P (A0) A A A0 A A A A D D D D D D D D C C C C C C C C C C0 C C C C C C PC C C C C C C C C C C0 C C C C C C LINES FPGA0- HAVE THE FOLLOWING DEFAULT FUNC TIONS NAME FUNCTION FPGA0 IN MEM_CARD_PRESENT- FPGA OUT ROM_MAP_ FPGA OUT ROM_MAP_ FPGA OUT WU- (WRITE HIGH BYTE) FPGA OUT WL- (WRITE LOW BYTE) FPGA OUT RAM_CS- (CS- FOR EXPANSION RAM) FPGA OUT A DIN-W TY PE "C/" V ERT SKT DIN-W TY PE "C/" V ERT SKT DIN-W TY PE "C/" V ERT SKT,,,, D[0..] D[0..] FPGA[0..] FPGA [0..]. Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - MEMORY, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

47 Figure - Schematic Sheet - Sound Page SAMPLED SOUND CHANNEL # SAMPLED SOUND CHANNEL # C0 C SFX_D[0..] SFX_D[0..] U 00n SFX_D[0..] SFX_D[0..] U 00n PORTA [0..] POP POP POP POP SFX_S SFX_S SFX_D0 SFX_D SFX_D SFX_D D0 D D D S S VDD T T T T DA O,,,0 PORTA [0..] PORTA [0..] PORTA PORTA SFX_D0 SFX_D SFX_D SFX_D SFX_S SFX_S D0 D D D S S VDD T T T T DA O PORTA 0 RESET PORTA RESET SFX_CLK SFX_CLK XT AOUT 0 SFX_CLK SFX_CLK XT AOUT 0 XT VCK XT VCK MSM MSM SFX_VCK SFX_VCK R K % SFX_VCK SFX_VCK R K R0 K % C 0n C 0n R C K /0 R K +V C 00n C0 0/ U LS CONN ECTOR P0 LS+ LS- CH_MIX LS+ LS- HDR W AMP MTA C /0 C C /0 R0 K R0 K PP PP PP TOUT 0 - /0 R0 PP TOUT TDA0AQ C /0 R K K. Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - SOUND, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

48 Figure - Schematic Sheet - Outputs Page OP[0..] OP[0..] D0 SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP OP OP0 OP OP OP OP OP0 D SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP0 OP OP OP OP OP0 OP OP P P P P 0 0 P P P P 0 0 TPIC TPIC A[0..] A[0..] A UA HC UB D SEL0 SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP OP OP OP OP OP OP OP D SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP OP OP OP OP OP OP OP A A HC UC SEL SEL P P P P TPIC 0 0 P P P P TPIC 0 0 HC D SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP OP0 OP OP OP OP OP0 OP D SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP OP OP OP OP0 OP OP OP P P P P 0 0 P P P P 0 0 TPIC TPIC 0 CS_OP- RESET- D SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP OP OP OP OP OP OP OP D SEL0 SEL SEL U D Q0 Q S0 Q S Q S Q Q G Q CLR Q OP OP OP OP OP OP OP OP P P P P 0 0 P P P P 0 0 TPIC TPIC,,,, D[0..] D[0..] SEL[0..] SEL[0..]., -00 C 00n C 00n C 00n C 00n Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - OUTPUTS Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

49 Figure - Schematic Sheet - Inputs Page IP[0.. ] IP[0.. ],,,, D[0..] D[0..] D0 D D D D D D D C 00n C 00n U Y C0 C C C Y C0 C C C A B G G HC U0 Y C0 C C C Y C0 C C C A B G G HC U Y C0 C C C Y C0 C C C A B G G HC U Y C0 C C C Y C0 C C C A B G G HC SEL0 SEL SEL0 SEL SEL0 SEL SEL0 SEL R K % R K % R K % R K % R K % R K % R K % R K % R K % R K % R0 K % R K % R K % R K % R K % R K % R K % R K % R K % R K % R K % R K % R K % R0 K % R K % R K % R K % R K % R0 K % R K % R K % R K % IP IP IP IP0 IP IP IP IP N K* SIL IP IP IP0 IP IP IP0 IP IP N K* SIL IP IP IP IP N K* SIL IP IP IP IP IP0 IP IP IP IP IP IP IP N K* SIL D D D0 D U Y C0 C C C Y C0 C C C A B G G HC U Y C0 C C C Y C0 C C C A B G G HC 0 0 SEL0 SEL SEL0 SEL N K* SIL SW W DIL SW N K* SIL 0 SW W DIL SW 0 CS_IP- SEL[0..] SEL[0..] NOTE: SEL0- ARE INVERTED A-. Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - INPUTS, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

50 Figure - Schematic Sheet - Power Supply Page +V D UF00 R R METER DETECTION +V VMETER+ METER_SENSE METER_SENSE LC EMC FILTER +V UA + - R K % R K % R R K % PP PP R0 K PP R0 revisions: k -> 0k Feb 0k -> k Jul 00 NMI- POWER FAIL DETECTION UB + - LM VREF 0 R K % PP PP R K LM PP0 K % PP PP,,,0 PORTA [0..] PORTA [0..] UC R K % PP D N SFX_CLK SFX_CLK TP PA D PORTA + - PP R MPX_REF MPX_REF TP PA D Thresho ld - Lamp s hort cct. LM R K K +V TP PA D PORTA + - UD 0 PP PP MPX CURRENT SENSE +V_IN TP PA D Thresho ld - Lamp p resent LM R 0R C p C0 p MPX_ VSS MPX_REF MPX_REF +V_IN F.A F 0*MM LC EMC FILTER U LM0 VI VO VMOT+ +V -V -V +V_IN MPX_ VMPX+ P HDR W AMP MTA - POWER IN D0 SA C /0 C /0 D SA D SA. REGULATED +V Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - POWER SUPPLY, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

51 Figure - Schematic Sheet IO Connectors Page Heber Ltd. OP OP OP OP0 OP OP OP OP OP0 OP OP OP IP0 IP IP IP IP IP0 +V OP OP0 OP OP OP OP OP0 OP IP IP IP0 IP IP IP IP +V P A A A B A A B A A B A A B A A B A A B A A B A A B A0 A B A A0 B0 A A B A A B A A B A A B A A B A A B A A B A A B A0 A B A0 B0 HDR 0W P A A A B A A B A A B A A B A A B A A B A A B A A B A0 A B A A0 B0 A A B A A B A A B A A B A A B A A B A B HDR W B OP B OP B OP B OP B OP B OP B OP B OP B OP B0 OP B OP B OP B B IP B IP B IP B IP B IP B IP B0 +V B OP B OP B OP B OP B OP B OP B OP B OP B B0 IP B IP B IP B IP B IP B IP B IP B V METER+ LR[0..] LR[0..] LC[0..] LC[0..] REELS P LC0 A B LC A A B B LC A A B B LR0 A A B B LR A A B B LR A A B B A A B B OP0 A A B B OP A A B B OP A0 A B B0 OP A A0 B0 B OP A A B B OP0 A A B B OP A A B B OP A A B B OP A A B B OP A A B B OP0 A A B B OP A A B B IP0 A0 A B B0 IP A A0 B0 B IP A A B B VMOT+ A A B B VMOT+ A A B B A A B VMOT+ B A B LC LC LC LR LR LR OP OP OP OP OP OP OP OP OP OP OP OP IP IP IP VMOT+ VMOT+ VMOT+ CS_TTL- LC EMC FILTER TGA TE- CS_TTL- RESET- D A0 A A 0 U0 D Q0 Q S0 Q S Q S Q Q G Q CLR Q P 0 P P 0 P UE TPICB LC EMC FILTER R0 SDA SCL N0 K0* SIL TTL P +V HDR W AMP MTA-00 I C P HDR W AMP MTA-00 IP[0.. ] OP[0..] IP[0.. ] OP[0..] HDR 0W TGA TE- PP PP HC UD K PP PP R0 PP PP HC K PP PP,,,0 PORTA [0..] PORTA [0..],,,, D[0..] D[0..],0 RXDA TXDA,0 CTSA - RTSA - A[0..] RXDA TXDA CTSA - RTSA - PC D C D C C D0 C C D C C D C C D C C D C C D C C C C C0 C C C0 C C A0 C C A C C A C C A C C C DIN-W TY PE "R/" V ERT MALE A[0..] PB PORTA 0 B PORTA B B PORTA B B PORTA B B PORTA B B PORTA B B A B B AS- B B DS- B B R/W- B0 B DSA CK0 - B B0 DSA CK - B B SIZ0 B B SIZ B B PB B B PB B B B DIN-W TYPE "R/" VERT MALE AS- DS- R/W-, DSA CK0 - DSA CK - SIZ0 SIZ,0 PB PB HALT- CLKOUT CS- 0 RESET- BERR- HA LT- CLKOUT CS- RESET- BERR- A0 A A A A A EXP. +V A A A A A A A A A A0 A A A A A A PA A A A A A A A A A A0 A A A A A A DIN-W TYPE "R/" VERT MALE. Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - CONNECTORS, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

52 Figure 0 - Schematic Sheet 0 - Reset/Battery/RS Page BATTERY BACK-UP SM Q FMMT VBATT TP PA D TP PA D R K TP PA D R K BT.V NiMH C /0 PP PP R K Q N00 RA M_ CS-, TXDA RTSA - +V V+ A B B -V V- TXA TXB U +V P RS (PORT A) RESET- TXDB 0 C C TXC HDR W AMP MTA - 00 RTSB- D D TXD C p X Khz U0 OSCI VDD OSCO INT A0 SCL SDA PCF EEPROM U A0 A TST A SCL SDA C0/C0 INTERNA L IC BUS VBATT SCL SDA R0 0R R 0R PORTA PORTA PORTA [0..],, PORTA[0..],,, RXDA R CTSA - K RXDB CTSB- R K A B C D RXA RXB RXC RXD U 0 P 0 0 -V +V W D SOCKET DATAPOR T (PORT B ) PP PP POWER-ON RESET VREF RTC U,, RESET- RESET- RESET SENSE RESET RESIN- RESET RESET RESIN PB0 R K C 00n C 00n REF CT TL0 C 0/ C 00n. Belvedere Mill Chalfor d, Str oud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - RESET/BATTERY/RS, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of 0 Document No. 0- Issue

53 Figure - Schematic Sheet - Lamp Column/LED Digit Drives Page N K* SIL LC[0..] LC[0..] LC0 LC0 DIG0 STR_V STR_A_V CLK_V OE_V +V C 00n +V C 00n +v +v DIG0 DIG DIG DIG DIG DIG0 DIG DIG SEG0 SEG SEG SEG SEG SEG0 SEG SEG U0 STR D CLK OE VDD 0 U STR D CLK OE VDD 0 * A A A A A A A A A A0 A A A A A A Q Q Q Q Q Q Q Q QS QS Q Q Q Q Q Q Q Q QS QS P A A A A A A A A A A0 A A A A A A 0 0 B B B B B B B B B B0 B B B B B B B B B B B B B B B B0 B B B B B B SEG SEG SEG SEG SEG SEG SEG SEG HDR W AMP ULTREX or HDR W BOX HEADER (Pins / - no connection) DIG DIG DIG DIG DIG DIG DIG DIG R 0R R 0R N * K* SIL R 0R R0 0R R 0R R 0R * * R 0R R 0R R 0R R00 0R * * R 0R R 0R R 0R R0 0R * * R 0R R 0R * * Q BUK LC Q BUK LC Q BUK LC Q BUK LC Q BUK LC Q0 BUK LC Q BUK LC Q BUK LC * Q BUK LC * Q BUK LC0 * Q BUK LC * Q BUK LC * Q BUK LC * Q BUK LC * Q BUK LC * Q0 BUK LC LC LC LC LC LC LC LC LC LC0 LC LC LC LC LC D UF00 D UF00 D UF00 D UF00 D UF00 D UF00 D0 UF00 D UF00 * D UF00 * D UF00 * D UF00 * D UF00 * D UF00 * D UF00 * D UF00 * D UF00 DIG DIG DIG DIG DIG DIG DIG DIG DIG DIG0 DIG DIG DIG DIG DIG P LC0 LC LC LC LC LC LC LC LC LC 0 LC0 LC LC LC LC LC HDR W AMP MTA-00 LAMP COLUMNS(SINKS) D-D Changed from N00 to UF00 March, 00 DIG[0..] SEG LED DRIVE ( DIGIT) OR S EG LED DRIVE ( DIGIT) MPX_REF MPX_REF * - THESE COMPONENTS OMITTED ON PLUTO /. (DRIVE FOR LC-/DIG-) Rsense milliohms Copper Track MPX_REF MPX_REF SEG[0.. ] SEG[0..] MPX_. Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - LAMP COLUMN/LED DIGIT DRIVES, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

54 Figure - Schematic Sheet - Lamp Row Drives Page VMPX+ N K* SIL C 00n R K R K R K R K R K R K Q BC Q BC Q BC Q BC Q BC Q BC Q R K R K R K R K R K R K R0 K R VMPX+ Q TIP Q0 TIP Q TIP Q TIP Q TIP Q TIP Q TIP Q TIP LR0 LR LR LR LR LR LR LR LR0 LR LR LR LR LR LR LR LR LR LR0 LR LR LR LR LR LAMP ROWS(SOURCE) P 0 HDR W AMP MTA-00 BC Q K MPX_C_V MPX_D_V U STR D CLK OE VDD 0 Q Q Q Q Q Q Q Q QS QS C 00n 0 R K R K R K R K R K R K BC PP PP Q BC Q BC Q BC Q BC Q BC Q BC Q R K R K R K R K R0 K R K R K R N K* SIL VMPX+ VMPX+ VMPX+ Q TIP Q TIP Q TIP Q0 TIP Q TIP Q TIP Q TIP Q TIP LR LR LR0 LR LR LR LR LR LR[0..] BC Q0 STR_V MPX_A_V CLK_V OE_V MPX_B_V +V U STR D CLK OE VDD 0 +V Q Q Q Q Q Q Q Q QS QS 0 R K R0 K VMPX+ VMPX+ VMPX+ VMPX+ VMPX+ VMPX+ VMPX+ VMPX+ +V +V PP0 PP PP PP R0 K R K VMPX+ VMPX+ VMPX+ VMPX+ VMPX+ LR[0..] K BC. Belvedere Mill Chalford, Stroud, GL NT Tel: + (0) 000 Fax: + (0) 0 Title PLUTO - LAMP ROW DRIVES, -00 Size Document Number Rev A -0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

55 Figure - Schematic Sheet - LED Segment Drives Page 0 MPX_OE MPX_CLK MPX_STR MPX_DATA_A MPX_DATA_A MPX_STR_DATA_A MPX_B_V U AI AO BI BO CI CO 0 DI DO EI EO FI FO MODE VDD 0 +V OE_V CLK_V STR_V MPX_A_V MPX_A_V STR_A_V +V U STR D CLK OE VDD 0 OE_V, CLK_V, STR_V, MPX_A_V STR_A_V Q Q Q Q Q Q Q Q QS QS 0 +V Q BC Q BC Q BC Q BC Q BC Q BC R 0R R 0R R 0R R 0R R 0R R 0R R SEG0 SEG SEG SEG SEG SEG SEG MPX_C_V +V Q BC 0R R SEG C 00n Q BC 0R +V +V Q BC R0 0R R SEG SEG MPX_D_V +V U STR D CLK OE VDD 0 Q Q Q Q Q Q Q Q QS QS C 00n 0 Q0 BC Q BC Q BC Q BC Q BC 0R R 0R R 0R R 0R R 0R R SEG0 SEG SEG SEG SEG Q BC 0R R SEG Q BC 0R SEG[0..] SEG[0..] MPX_A_V UA MPX_A_V 0 UB LC STR_A_V CLK_V STR_V OE_V UC 0 UD 0 UE 0 0 UF 0 LC LC LC0 LC P HDR W 0. KK MULTIPLEX EXPANSION HEBER L TD. Belvedere Mill Chalfor d, Str oud, GL NT Tel: + (0) 000 Fax: + (0) 0 0 LC +V VDD Title PLUTO - LED SEGMENT DRIVES, -00 Size Document Number Rev A - 0 r Date: Tuesday, August, 00 Sheet of Document No. 0- Issue

56 Figure - Pluto Component Ident Page Document No. 0- Issue

57 Figure - Photograph of Pluto with Ultrex Connectors (Pluto U) Page Document No. 0- Issue