Terminating buses in computer designs

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Evelyn Flynn
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1 Terminating buses in computer designs Computer designers now combine many functions that put interface devices in signal paths between subsystems. Check all possible states and transitions that you could encounter at each subsystem boundary. By Lee Sledjeski Senior Applications Engineer Fairchild Semiconductor Input ESD P1 N1 VDD Q1 BiCMOS CMOS P2 N2 To output stage(s) To maintain reliability in a typical computer system that is idle or being reconfigured, you must design system interconnects such that they maintain (or transition to) a valid logic level. You can use several methods to maintain a bus or transition it to a predetermined logic level: 1. Terminating pull-up resistors 2. Thevenin termination 3. Pull-up/down resistors 4. Bus-hold 5. Central bus arbitration unit Use the technique most appropriate for the application. Allowing the interconnect to loiter at an indeterminate voltage level causes system faults or bit errors which can show up in one of several ways. If the floating condition is allowed to persist, it could generate lots of heat, thus overstressing the afflicted device and disabling the system. Figure 1: Take a look at the CMOS and BiCMOS input structures. It s easy to see how a floating condition could disable the entire system. Input ESD P1 N1 P2 N2 To output stage(s) Simple evaluation of modern CMOS and BiCMOS (figure 1) IC input circuitry clearly shows the potential danger. A similar study of the circuit layout topology reveals that the steady-state current caused by the floating input condition exceeds current density limits for the metal bussing around the input transistors. Floating nets are like antennae for system noise. They are ideal candidates for coupling unintended system noise from one signal to an adjacent signal. Since the floating net is unterminated, electric fields from nearby signals constantly effect the potential (voltage) on the net. This energy induces a selfsustaining oscillation that results in IC and system failure. Priorities and constraints If you are a typical engineer working on a new computer design, you are always working to optimize a system given a particular set of product requirements and time-to-market constraints. Exactly how, or to what degree, you prioritize individual pieces of the final design specification changes with each passing project. The ability to reuse pieces of hardware and software from a previous design also weighs heavily in the final solution. Here s a list of constraints common to products ranging from portable electronics to giant telecommunication switches:

2 What s Online VTT To access the articles listed below, use their titles in the new Keyword Search feature available on EE Online at PII µp PII µp 56Ω Zero-delay logic addresses PC design challenges Address data and control BX chipset GTLP processor bus Figure 2: GTLP pull-up Pentium II processor bus with North Bridge. This scheme is a byproduct of GTL technology and its need for external termination. PCMCA bridges and standards for Windows 98 and beyond Designing large capacity switching systems for video applications 1. Active and standby power consumption 2. Signal termination requirements 3. Mixed supply voltage operation 4. Support for partial system powerdown and live insertion At first glance it is obvious certain solutions (pull-up/down and bus hold) will offer advantages in small batterypowered devices. Other solutions (pull-up and Thevenin terminations) suit the needs of larger equipment. This is really only half the story. You must also apply the same set of constraints and priorities to most system components. This includes driver and receiver technology for bus interface functions, especially since integrated solutions to the floating bus problem are becoming more versatile and common. The following sections detail each of the methods, explaining the benefits and potential issues with each implementation. PCI Bus Address data and control Main memory Audio LAN System I/O North bridge Bus arbitration SCSI Termination resistors The latest generation of PCs (figure 2) use a processor bus architecture that incorporates Gunning Transceiver Logic (GTL), or GTL Plus (GTLP). This configuration uses the bus termination itself to provide and maintain a valid logic level on the bus during periods of inactivity or arbitration between bus master devices. An open-drain I/O has no internal capability to pull the bus up. Moreover, the external termination directs the low-to-high (LH) transition. Therefore only two possible logic states 0 or 1 can exist, unlike contemporary CMOS logic which allows 0, 1, or high impedance (Hi- Z). Other bus architectures, such as VTH= VDD * R 2 /(R 1+R 2 ) VDD VME, use the termination voltage to provide a valid logic level on an idle bus (figure 3). The resistive termination offers a Thevenin equivalent voltage greater than 2V, thereby keeping the bus above or transitioning the bus through the dangerous indeterminate region between 0.8V and 2V. Besides providing a valid logic level, the termination tends to damp out any reflections or noise on the backplane signal lines. This scheme works best with asymmetrical output drivers capable of sinking heavy dc loads. The dc bias of the termination requires the active driver on the backplane to supply a substantial amount of current to maintain a valid logic 0. Another type of solution is often R1 Thevenin voltage Figure 3: VME backplane with Thevenin termination. This architecture uses the termination voltage to provide a valid logic level on the bus while idle. Multimedia 2D/3D graphics engine Figure 4: PCI bus arbitration with North Bridge. This architecture uses a combination of bus-master drive and pull-down resistors. R2

3 OE VREF A0-A9 VCC 50kΩ used to complement the termination resistors. It uses the bus-master or bus-arbitration unit to actively drive the bus to a known state during inactive periods. PCI is an example of a bus architecture that uses a combination of bus-master drive and pulldown resistors. Figure 4. Pull-down resistors A typical example of this arrangement is in a preliminary Double Data Rate (DDR) SDRAM specification. Busswitch ICs are defined to incorporate a pull-down resistor for the DDR module data bus. This resistor ensures SDRAM ICs on the module will never draw excessive current due to a floating memory system data bus. The design question then becomes straightforward. You should ask, What edge-rate will the pull-down resistor impose on a SDRAM input and will this be a problem? You can calculate this answer, given the input and board capacitance on a given trace along with the pull-down resistor value. 10kΩ 1bit of ten (10) B0-B9 Figure 5: DDR bus switch with pull-down and pull-up resistors, which ensure that SDRAM ICs on the module will never draw excessive current due to a floating bus. The highest density SDRAM modules commonly used today have a 256MB capacity. Utilizing 64Mb memory technology, these modules are populated with up to 36 memory devices. This configuration requires two memory I/Os on each data bit shown in figure 5. With an I/O capacitance of 6.5pF per memory device and about 2 inches of PCB trace, the total capacitance (at 2pF/ inch) on each bit of the B-Port will be 17pF. The time constant of this RC network is 170ns. You can I IN (µa) Bus-hold current LVT FSC -500 V IN (Volts) approximate the fall time (T f ) with the formula: T f = RC/0.67V cc = 77ns/V With modern logic devices, input slew rate is generally specified between 0-10ns/V. As you can see from the calculations above, it is all but impossible to guarantee an edge rate of 10ns/V and maintain a reasonable dc power consumption per bit on the bus in a multi-drop arrangement. Remember the system will consume dc power for approximately 50 percent of the signal lines whenever the bus is active. It is only during the single transition to inactivity in which a slow rising/falling signal due to a relatively large (around 10kΩ) pulldown resistor value will consume system power. This power is consumed in the form of an increased I CCT current component for every listener on the bus. In the DDR SDRAM example shown in figure 5, you would need a pull-down resistor value of 1kΩ to I/O pin Output buffer stage Input buffer stage Bus-hold input cell Figure 6: Bus-hold input (or I/O). This technique is used on several low-voltage logic families to provide IC inputs and I/Os with a means to re-drive the incoming signal back out the input. Driver output I OH(OD) I OL(OD) Input Input Input Input Input Input Figure 7: Bus-hold overdrive current path, indicating how this technique impacts the dynamic drive requirements of all outputs on the bus. guarantee an input edge rate below 10ns/V. This lower resistance would increase the total power dissipation on the SDRAM module by 400mW or over 750mW (in some extreme cases). Fortunately, the synchronous nature of this bus architecture tolerates the slow fall times imposed by the 10kΩ pulldown resistor. You can thus save a significant amount of system power.

4 Bus-hold considerations Bus-hold is an active feedback technique (figure 6) used on several low-voltage logic families to provide IC inputs and I/Os with a means to re-drive the incoming signal back out the input. While this sounds complicated, it is conceptually quite simple and is very effective in some system applications. The bus-hold option imposes its own set of current requirements. Even though bus-hold can overcome the LVT16245 I BHL=200µA C I OH =-300µA I C =100µA PCMCIA Given I C= C*dV/dt dt = (C*dv)/IC dt= (25pF*1.5V) / 100µA dt = 375nS Maximum step out Output voltage AC step out Propagation delay Figure 8: The impact of bus-hold devices on AC performance in a PC Card application. Switch-point at 1.5V-bus hold releases latch T/R 1 OE1 problem of increased listener I CCT during transitions to bus inactivity, it adds an entirely new component to system power consumption. Bus-hold impacts the dynamic drive requirements of all outputs on the bus. It does so by imposing an additive (depends on the number of bus-hold devices) overdrive current requirement (figure 7). Outputs must contend with the bushold devices and overpower them to ensure proper signal transitions and transmission. This additive current limits the practicality of bus-hold equipped devices in a large multidrop bus architecture and portable designs containing devices with output drive specifications (I OL /I OH ) of less than 4mA. Pull-down versus bus-hold A good way to compare bus-hold and pull-down resistor solutions is to T/R 2 A 0-7 B 0-7 B 8-15 A 8-15 OE1 Figure 9: The pull-down resistor is connected only when the terminating device is disabled or inactive, which indicates there are no data transfers between the PC Card and palmtop computer. OE2 OE2 examine a palmtop computing application. The PCMCIA (or PC Card) standard has defined a 68-pin modular interface that supports common add-on functionality like modem and LAN cards. The PC Card connector is a common feature found in palmtop computers. As shown in V CC =3.3V V CC =5V LVT K on card PCMCIA Given a last state of FFFF'h Potential "3-state" current = 24mA I CC current figure 8, using a part like the LVT16245 forces the tiny drivers in the PC Card to overcome a relatively large bus-hold current opposing the change of state on the PC Card bus. Normally, the drive characteristics of bus-interface devices easily overcome the bus-hold devices. However, battery-powered PC Cards don t require large dynamic currents. In fact, larger output drivers would draw more dynamic power and have a detrimental effect on battery life. If you use an integrated pull-down solution instead of a bus-hold device, you reduce the PC Card current demand from a maximum of +/-200µA to just +/-5µA. Clever integration of the pull-down resistor incorporates a sense line to the enable circuitry (figure 9). The PC Card interface has standards for 3V and 5V card types. This means Input voltage Bus hold high 1.5 ma I /Input CC 500 µa Spec 20 µa Spec Typical CMOS Figure 10: In mixed-voltage operation with more than a single common V CC associated with any particular bus, pull-up resistors and bus-hold circuits are impractical and incomplete solutions.

5 3V or 5V cards will need to interface and communicate with the 3V logic, a classic mixed-voltage bus scenario. Mixed-voltage buses whether found in portable systems striving for lowpower operation or communication systems having a life span of over ten years need special consideration. With more than a single common V CC associated with any particular bus, pull-up resistors and bus-hold circuits are impractical and incomplete solutions. The bus-hold circuitry cannot hold the bus higher than the V CC of the parent device (figure 10). Allowing the bus to remain at 3V can cause significant levels of I CC or I CCT due to input stages of 5V devices being partially turned on. Which method works best The best methodology for controlling logic levels on an idle bus is still the venerable passive resistor. Active techniques, like bus-hold, can constrain future system upgrades to a specific operating voltage or overpower weak output drivers in modular battery-powered applications. Even with the passive resistor, some techniques will work better in mixed-voltage applications. Pulling up to 5V through a resistor will result in a current path to the 3V supply through the active output structures of the low-voltage devices. This current, although small, could transmit the 5V potential on the 3V CC supply rail. This voltage and current may be high enough to damage sensitive semiconductor devices like memories and microprocessors manufactured with deepsubmicron process technology. This leaves the pull-down resistor as the methodology of choice. You may your comments on this article to Lee Sledjeski at Lee.Sledjeski@ fairchildsemi.com, or Fax:

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