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2 , DS1, July 2000 PEB20256 Multichannel Newtork Interface Controler for HDLC/PPP MUNICH256 V2.1 DataCom Never stop thinking.

3 Edition Published by Infineon Technologies AG, St.-Martin-Strasse 53, D München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

4 MUNICH256 Revision History: DS1 Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at ABM, AOP, ARCOFI, ARCOFI -BA, ARCOFI -SP, DigiTape, EPIC -1, EPIC -S, ELIC, FALC 54, FALC 56, FALC -E1, FALC -LH, IDEC, IOM, IOM -1, IOM -2, IPAT -2, ISAC -P, ISAC -S, ISAC -S TE, ISAC -P TE, ITAC, IWE, MUSAC -A, OCTAT -P, QUAT -S, SICAT, SICOFI, SICOFI -2, SICOFI -4, SICOFI -4 C, SLICOFI are registered trademarks of Infineon Technologies AG. ACE, ASM, ASP, POTSWIRE, QuadFALC, SCOUT are trademarks of Infineon Technologies AG.

5 Application Note

6 Table of Contents Page 1 Introduction PCI bus access description Assumptions Bus load calculation PCI Bus Utilization results Conclusion Application Note

7 Table of Contents Page Application Note

8 List of Figures Figure 1 PCI Bus Utilization of the MUNICH256F on a 33 MHz PCI bus with one DS3 link ( Mbit/s, up to 256 channels) 15 Figure 2 PCI Bus Utilization of the MUNICH256F on a 33 MHz PCI bus with 256 channels of 64 kbit/s full duplex 16 Page Application Note

9 List of Figures Page Application Note

10 Introduction 1 Introduction The Channelized HDLC Controller with integrated T1/E1 Framers (MUNICH256F) is a highly integrated protocol controller that implements HDLC/PPP processing and T1/E1 frame alignment for 28 T1 / 21 E1 physical ports and 256 channels. A memory management unit and the DMA controller are optimized to transfer data to a PCI interface by minimizing the bus load. On-chip buffers of 32 kbyte FIFO in transmit direction and 12 kbyte FIFO in receive direction allow high bus latencies and ensure a low PCI bus load with good burst performance. Typical applications are the HDLC/PPP termination of up to 256 logical channels belonging to a channelized DS3 line (44 Mbit/s) or a channelized STM0/STS1. Each channel can be assigned to an arbitrary number of timeslots of a T1/E1 line. An other main application consists of a multiple T1/E1 card. The bus load of a single channel is calculated as the relation of the data transfer time on the PCI bus and on the serial interface and then multiplied by the number of used channels. The entire bus load is determined by the bit rate of each channel and the frame length. Application Note

11 PCI bus access description 2 PCI bus access description In order to minimize the PCI bus utilization, a particular attention has to be paid to the following parameters: The size of the descriptor must be minimized. The descriptor must be read and updated only once per frame and stored on chip by the device. A linked list structure enables a very efficient way (with only one pointer change from the CPU) to send a received packet. The number of overhead accesses for each frame must be minimized because the bus utilization increases with short frames. Free Queues or Ready Queues increase the overhead in terms of register accesses. The number of PCI accesses for interrupt handling must be minimized. All these parameters have been studied in detail for the M256F and the implemented memory management provides a minimized PCI bus load. The transmit and receive data, the transmit and receive descriptors and the interrupt status queues are located in the shared memory. Both the M256F and the CPU operate on these data structures. Each logical channel has its dedicated linked list of descriptors and data for transmit and receive direction. This data structure type allows a channel specific address range that can be specified by the CPU and provides an optimized way to transfer a received data packet to a transmit linked list. For data transmission and reception, the CPU only operates on the shared memory. As long as the HOLD bit is not set in the descriptor, the M256F will process the linked list and assume the next descriptor is valid. In transmit operation if the CPU has no more data to sent for a particular channel, it will set the HOLD bit in the last transmit descriptor. When new data is available, the CPU writes the action request command register. Therefore, in normal operation, the CPU performs no PCI access to the M256F to send or receive data. Eight different interrupt queues are implemented for an easier prioritization of receive, transmit or error handling interrupt functions. The interrupt source for each channel can be associated to one of the eight interrupt queues. For each interrupt source, a mask bit for interrupt vector generation and a mask bit for interrupt pin generation can be programmed. In the following calculation it is assumed that one interrupt source is serviced per direction and that the CPU polls the corresponding interrupt queue in the shared memory. In this operation, the CPU performs no PCI access to the M256F for interrupt handling. For each transmitted frame the M256F will perform following master accesses on the PCI bus: Application Note

12 PCI bus access description read the transmit descriptor (control word, next pointer and data pointer), burst of 3 words. read the user data (access time depending on the burst length and on the frame length). optional write to the transmit descriptor (one control word). This transfer is included in the calculations below. write an interrupt vector (one word). For each received frame following PCI transactions are initiated by the M256F: read the receive descriptor (control word, next pointer and data pointer), burst of 3 words. write the user data (access time depending on the burst length and on the frame length). write the receive descriptor (one control word). write an interrupt vector (one word). Application Note

13 Assumptions 3 Assumptions Concerning frame rate the following calculation is based on the worst case requirements. It assumes back-to-back traffic with CRC-16 and shared flags. It is assumed that the complete frame is associated with one descriptor. It is assumed that one interrupt source is serviced for each direction (frame received and frame completely sent) and that the CPU polls the interrupt vectors in the shared memory. Following assumptions are done concerning the PCI bus accesses: One turn around cycle is inserted between the address and data cycle for each read access. No turn around cycle is inserted between the address and data cycle for each write access. One turn around cycle is inserted at the end of each PCI access. The number of initializing wait states in read direction is 7. The number of initializing wait states in write direction is 1. No other wait states are inserted by the PCI bridge. These values are typical values for PCI bridges. The arbitration time is not taken into account. The access time for a read transfer of n data words is A + T + wir + n * D + T, where A is the address cycle time (30 ns), T is the turn around cycle time (30 ns), D is the data cycle time (30 ns) and wir the initializing wait states for a read cycle. The access time for a write transfer of n data words is A + wiw + n * D + T where wiw is the initializing wait states for a write cycle. Application Note

14 Bus load calculation 4 Bus load calculation Table 1 Acronyms Parameter Description b r Bit rate (bit/s) f l Frame length (number of bytes, multiples of 4 * d bl ) d bl w ir w iw t PCI t rd t td t i t RDescr t TDescr t s b l A T D Data burst length Number of wait states (initializing read) Number of wait states (initializing write) Total transfer time on PCI Transfer time for receive user data Transfer time for transmit user data Transfer time for one interrupt vector Transfer time for receive descriptor Transfer time for transmit descriptor Transfer time on serial interface PCI Bus load Address cycle (30 ns) Turn around cycle (30 ns) Data Cycle (30 ns) The total PCI bus transfer time for the transmission and reception of one frame is given by following expression: t PCI = t rd + t td + 2 t i + t RDescr + t TDescr and the PCI bus load by t rd + t td + 2 t i + t RDescr + t TDescr b l = t s Application Note

15 Bus load calculation The time needed to transmit/receive data on the serial interface (simultaneously) is expressed by (time in ns with CRC-16 and shared flag): f l bit 10 t s = b r 9 The transfer time for writing receive user data is the following (time in ns): t rd = f l A + w 4 d iw + d bl D + T bl The transfer time for reading transmit user data is expressed by (time in ns): t td = f l A + T + w 4 d ir + d bl D + T bl The transfer time for writing an interrupt vector is (time in ns): t i = A + w iw + D + T The transfer time for reading and writing back the receive descriptor is the following (time in ns): t RDescr = A + T + w ir + 3 D + T + A + w iw + D + T The transfer time for reading and writing back the transmit descriptor is expressed by (time in ns): t TDescr = A + T + w ir + 3 D + T + A + w iw + D + T Application Note

16 PCI Bus Utilization results 5 PCI Bus Utilization results The following calculations are made with typical PCI bridge latencies (7 clock cycles of wait state for a read transaction and 1 clock cycle of wait state for a write transaction). The bus load is first calculated for a channelized DS3 application where up to 256 channels are assigned to a total serial data rate of 44 Mbit/s. The results are basically independent from the number of channels used, i.e. the bus utilization for an application with 256 channels running at about 168 kbit/s each is the same as for 1 channel running at 44 Mbit/s. The graph shows the PCI bus load of one MUNICH256F device for a burst length of 8, 16 and 32 words. PCI Bus Utilization (%) 35,00 30,00 25,00 20,00 15,00 10,00 5,00 0, words burst 16 words burst 32 words burst Frame Length (bytes) Figure 1 PCIload.xls PCI Bus Utilization of the MUNICH256F on a 33 MHz PCI bus with one DS3 link ( Mbit/s, up to 256 channels) The main bus load factor is the frame length. The support of 16 words of burst length decreases the bus load by 3% in the average. Even with an average frame length of 32 bytes and a burst length of 8 words, the bus utilization of one MUNICH256F device remains under 33%. Note that the PCI bus utilisation decreases proportional to increasing bus speed; for example 33% bus utilization on a 33 MHz platform corresponds to 22% in a 50 MHz PCI environment. The second calculation is made for 256 channels with a data rate of 64 Kbit/s. The graph shows the PCI bus utilization of one M256F device for a burst length of 8, 16 and 32 words. In this case the bus load remains under 12.5% for an average frame length of 32. Application Note

17 PCI Bus Utilization results PCI Bus Utilization (%) 14,00 12,00 10,00 8,00 6,00 4,00 2,00 0, words burst 16 words burst 32 words burst Frame Length (bytes) PCIload.xls Figure 2 PCI Bus Utilization of the MUNICH256F on a 33 MHz PCI bus with 256 channels of 64 kbit/s full duplex Application Note

18 Conclusion 6 Conclusion Depending on the application (number of channels and channel data rate) between two and six M256F devices can be connected to a common PCI bus. Especially for short frames (32 bytes) the use of optimized data structures (with a minimized number of CPU accesses) has a bigger influence than the burst size on the PCI bus. A PCI burst length of 16 words is a good compromise between internal buffer size and bus utilization. However the burst threshold is programmable for each channel and a higher burst length can be programmed for channels with a higher data rate or if less than 256 logical channels are active. Application Note

19 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction. Dr. Ulrich Schumacher Published by Infineon Technologies AG

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