Lecture 9 - Virtual Memory
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1 CS 152 Computer Architecture and Engineering Lecture 9 - Virtual Memory Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory
2 Administrivia PS2 and lab 2 due Wednesday next week (March 2 nd ) Quiz 2 is on Monday March 7th 2
3 Last time in Lecture 9 Protection and translation required for multiprogramming Base and bounds was early simple scheme Page-based translation and protection avoids need for memory compaction, easy allocation by OS But need to indirect in large page table on every access Can use multi-level page table to hold translation/protection information, but implies multiple memory accesses per reference Can use translation lookaside buffer () to cache address translations (sometimes known as address translation cache) Still have to walk page tables on miss, can be hardware or software talk Virtual memory uses DRAM as a cache of disk memory, allows very cheap main memory 3
4 Question of the Day How would you design a prefetcher? 4
5 Memory Management Can separate into orthogonal functions: Translation (mapping of virtual address to physical address) Protection (permission to access word in memory) Virtual memory (transparent extension of memory space using slower disk or flash storage) But most modern systems provide support for all the above functions with a single page-based system 5
6 Modern Virtual Memory Systems Illusion of a large, private, uniform store Protection & Privacy several users, each with their private address space and one or more shared address spaces page table <-> name space OS user i Demand Paging Provides the ability to run programs larger than the primary memory Primary Memory Secondary Storage Hides differences in machine configurations The price is address translation on each memory reference VA mapping PA 6
7 Physical Memory 31 Hierarchical Page Table Virtual Address p1 p2 offset 0 10-bit L1 index Root of Current Page Table (Processor Register) 10-bit L2 index p1 Level 1 Page Table page in primary memory page in secondary memory PTE of a nonexistent page p2 Level 2 Page Tables offset Data Pages 7
8 PC Page-Based Virtual-Memory Machine (Hardware Page-Table Walk) Page Fault? Protection violation? Virtual Address Inst. Physical Address Inst. Cache D Decode E + M Page Fault? Protection violation? Virtual Address Data Physical Address Data Cache W Miss? Page-Table Base Register Miss? Hardware Page Table Walker Physical Address Memory Controller Physical Address Physical Address Main Memory (DRAM) Assumes page tables held in untranslated physical memory 8
9 Address Translation: putting it all together Virtual Address Lookup hardware hardware or software software miss hit Page Table Walk Protection Check the page is memory memory denied permitted Where? Page Fault (OS loads page) Update SEGFAULT Protection Fault Physical Address (to cache) 9
10 Page Fault Handler When the referenced page is not in DRAM: The missing page is located (or created) It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from disk Could be different thread of the same address space If no free pages are left, a page is swapped out Pseudo-LRU replacement policy, implemented in software Since it takes a long time to transfer a page (msecs), page faults are handled completely in software by the OS Untranslated addressing mode is essential to allow kernel to access page tables 10
11 Handling VM-related exceptions PC Inst Inst. Cache D Decode E + M Data Data Cache W miss? Page Fault? Protection violation? miss? Page Fault? Protection violation? Handling a miss needs a hardware or software mechanism to refill Handling a page fault (e.g., page is on disk) needs a restartable exception so software handler can resume after retrieving page Precise exceptions are easy to restart Can be imprecise but restartable, but this complicates OS software Handling protection violation may abort process But often handled the same as a page fault 11
12 Address Translation in CPU Pipeline PC Inst Inst. Cache D Decode E + M Data Data Cache W miss? Page Fault? Protection violation? miss? Page Fault? Protection violation? Need to cope with additional latency of : slow down the clock? pipeline the and cache access? virtual address caches parallel /cache access 12
13 Virtual-Address Caches CPU VA PA Physical PA Cache Primary Memory Alternative: place the cache before the CPU VA Virtual Cache VA PA Primary Memory (StrongARM) one-step process in case of a hit (+) cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) aliasing problems due to the sharing of pages (-) maintaining cache coherence (-) (see later in course) 13
14 Virtually Addressed Cache (Virtual Index/Virtual Tag) Virtual Address Virtual Address PC Physical Address Inst. Cache D Decode E + M Miss? Inst. Instruction data Translate on miss Page-Table Base Register Memory Controller Main Memory (DRAM) Data Cache Hardware Page Table Walker Physical Address Miss? Data W Physical Address 14
15 Question What is the benefit of separating instruction and data s? And the downside? 15
16 Aliasing in Virtual-Address Caches Page Table Tag Data VA 1 Data Pages VA 1 1st Copy of Data at PA PA VA 2 2nd Copy of Data at PA VA 2 Two virtual pages share one physical page Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General Solution: Prevent aliases coexisting in cache Software (i.e., OS) solution for direct-mapped cache VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in direct-mapped cache (early SPARCs) 16
17 Question How can we parallelize and cache access? Cache 17
18 Concurrent Access to & Cache (Virtual Index/Physical Tag) VA PA VPN L b k PPN Page Offset Virtual Index Direct-map Cache 2 L blocks 2 b -byte block Tag hit? Index L is available without consulting the =>cache and accesses can begin simultaneously! Tag comparison is made after both accesses are completed Cases: L + b = k, L + b < k, L + b > k = Physical Tag Data 18
19 Virtual-Index Physical-Tag Caches: Associative Organization VA VPN a L = k-b b 2 a Virtual Index k Direct-map 2 L blocks Direct-map 2 L blocks PA PPN Tag Page Offset What about fully-set associative? = hit? How does this scheme scale to larger caches? Phy. Tag After the PPN is known, 2 a physical tags are compared 2 a = Data 19
20 Question Does virtual tag, physical index make sense? 20
21 Concurrent Access to & Large L1 The problem with L1 > Page size VA VPN a Page Offset b Virtual Index VA 1 VA 2 PPN a PPN a L1 PA cache Direct-map Data Data PA PPN Page Offset b = hit? Tag Can VA 1 and VA 2 both map to PA? If they differ in the lower a bits alone, and share a physical page. 21
22 A solution via Second Level Cache CPU RF L1 Instruction Cache L1 Data Cache Unified L2 Cache Memory Memory Memory Memory Usually a common L2 cache backs up both Instruction and Data L1 caches L2 is inclusive of both Instruction and Data caches Inclusive means L2 has copy of any line in either L1 22
23 VA Anti-Aliasing Using L2 [MIPS R10000,1996] VPN a Page Offset b into L2 tag Virtual Index VA 1 VA 2 PPN a PPN a L1 PA cache Direct-map Data Data PA PPN Page Offset b Tag Suppose VA1 and VA2 both map to PA and VA1 is already in L1, L2 (VA1 VA2) After VA2 is resolved to PA, a collision will be detected in L2 (L2 is in physical space). VA1 will be purged from L1 and L2, and VA2 will be loaded no aliasing! PPN = hit? PA a 1 Data Direct-Mapped L2 23
24 Anti-Aliasing using L2 for a Virtually Addressed L1 VA VPN Page Offset b Virtual Index & Tag VA 1 VA 2 Data Data PA PPN Page Offset b L1 VA Cache Tag Physical Index & Tag Physically-addressed L2 can also be used to avoid aliases in virtuallyaddressed L1 PA VA 1 Virtual Tag Data L2 PA Cache L2 contains L1 24
25 Atlas Revisited One PAR for each physical page PAR s contain the VPN s of the pages resident in primary memory Advantage: The size is proportional to the size of the primary memory PPN PAR s VPN What is the disadvantage? How does this work with caches? Is a necessary? 25
26 Hashed Page Table: Approximating Associative Addressing PID VPN d Virtual Address Offset hash + PA of PTE Page Table Base of Table Hashed Page Table is typically 2 to 3 times larger than the number of PPN s to reduce collision probability. What does this mean? It can also contain DPN s for some non-resident pages (not common) If a translation cannot be resolved in this table then the software consults a data structure that has an entry for every existing page (e.g., full page table) VPN PID PPN VPN PID DPN VPN PID Primary Memory 26
27 Power PC: Hashed Page Table VPN d 80-bit VA hash Base of Table Offset Each hash table slot has 8 PTE's <VPN,PPN> that are searched sequentially If the first hash slot fails, an alternate hash function is used to look in another slot All these steps are done in hardware! Hashed Table is typically 2 to 3 times larger than the number of physical pages The full backup Page Table is managed in software + PA of Slot Page Table VPN VPN PPN Primary Memory 27
28 VM features track historical uses: Bare machine, only physical addresses One program owned entire machine Batch-style multiprogramming Several programs sharing CPU while waiting for I/O Base & bound: translation and protection between programs (supports swapping entire programs but not demand-paged virtual memory) Problem with external fragmentation (holes in memory), needed occasional memory defragmentation as new jobs arrived Time sharing More interactive programs, waiting for user. Also, more jobs/second. Motivated move to fixed-size page translation and protection, no external fragmentation (but now internal fragmentation, wasted bytes in page) Motivated adoption of virtual memory to allow more jobs to share limited physical memory resources while holding working set in memory Virtual Machine Monitors Run multiple operating systems on one machine Idea from 1970s IBM mainframes, now common on laptops e.g., run Windows on top of Mac OS X Hardware support for two levels of translation/protection Guest OS virtual -> Guest OS physical -> Host machine physical 28
29 Virtual Memory Use Today - 1 Servers/desktops/laptops/smartphones have full demandpaged virtual memory Portability between machines with different memory sizes Protection between multiple users or multiple tasks Share small physical memory among active tasks Simplifies implementation of some OS features Vector supercomputers have translation and protection but rarely complete demand-paging (Older Crays: base&bound, Japanese & Cray X1/X2: pages) Don t waste expensive CPU time thrashing to disk (make jobs fit in memory) Mostly run in batch mode (run set of jobs that fits in memory) Difficult to implement restartable vector instructions 29
30 Virtual Memory Use Today - 2 Most embedded processors and DSPs provide physical addressing only Can t afford area/speed/power budget for virtual memory support Often there is no secondary storage to swap to! Programs custom written for particular memory configuration in product Difficult to implement restartable instructions for exposed architectures 30
31 Question of the Day How would you design a prefetcher? 31
32 Acknowledgements These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) MIT material derived from course UCB material derived from course CS252 32
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