Using Flexible-LVDS Circuitry in Mercury Devices

Transcription

1 Using Flexible-LVDS Circuitry in Mercury Devices November 2002, ver. 1.1 Application Note 186 Introduction With the ever increasing demand for high bandwidth and low power consumption in the telecommunications market, designers are relying on differential standards such as LVDS to accelerate their I/O performance. LVDS, a low-voltage swing, general-purpose I/O standard, has highspeed, low-power, and low-noise advantages. With the incorporated Flexible-LVDS TM and True-LVDS TM circuitry in Mercury TM devices, designers can easily use the advantages of LVDS to create highperformance systems. Mercury programmable logic devices (PLDs) have an integrated differential high-speed interface and serializer/deserializer (SERDES) circuitry which includes four high-speed I/O banks with data transfer rates up to 1.25 gigabits per second (Gbps). Each I/O bank has up to 9 channels, offering up to 18 differential input channels and 18 differential output channels. These banks use techniques such as clock data recovery (CDR) to enable high-speed systems. The following documents provide information on Mercury device highspeed I/O standard features and functions. They also explain how system designers can take advantage of these standards to increase system efficiencies and bandwidth. Application Note 130 (CDR in Mercury Devices) provides information on how to use CDR in Mercury devices. Application Note 131 (Using General-Purpose PLLs with Mercury Devices) provides information on clock distribution using general-purpose phase-locked loops (PLLs) in Mercury device. Application Note 134 (Using Programmable I/O Standards in Mercury Devices) describes how to use the I/O standards supported in Mercury devices. Application Note 159 (Using HSDI in Source-Synchronous Mode in Mercury Devices) describes how to use the dedicated SERDES in Mercury devices in source-synchronous mode. Altera Corporation 1 AN

2 Flexible-LVDS Differential I/O Interface In addition to the high-speed I/O banks, Mercury devices offer 99 Flexible-LVDS input channels and 100 Flexible-LVDS output channels, which use internal PLLs to transmit or receive data up to 400 megabits per second (Mbps). Flexible-LVDS pins are distributed across the 12 nonhigh-speed differential interface (HSDI) I/O banks for easy board routing accessibility (see Figure 11). Flexible-LVDS circuitry only needs a 100-Ω termination resistor at the input of the receiver pin and does not require complicated resistor networks onboard, thereby saving valuable board space. 1 While EP1M350 devices support Flexible-LVDS pins, EP1M120 devices do not. LVDS and LVPECL signaling are supported on the receiver side and LVDS signaling is supported on the transmitter side of the Flexible-LVDS pins. When using these channels, you can build a SERDES using logic elements (LEs). This application note describes how to build the SERDES. Flexible-LVDS I/O Interface Review Flexible-LVDS interfaces are enhanced in the Mercury EP1M350 device with the use of dedicated double data rate (DDR) circuitry. Single data rate (SDR) circuitry samples data only at the positive edge of the clock. DDR circuitry captures data on both the positive and negative edges, providing twice the transfer rate of SDR. The EP1M350 device s shift registers, on-chip PLLs, and input/output elements (IOEs) can perform serial-to-parallel conversions on the incoming data and parallel-to-serial conversion on the outgoing data. The differential I/O driver in the IOE has high noise immunity, low power consumption, and low electromagnetic interference (EMI). Clock Domains in Mercury Devices Mercury EP1M350 devices have four general-purpose PLLs with advanced features that can be used for Flexible-LVDS circuitry (for more information on Mercury device PLLs, see Application Note 131 (Using General-Purpose PLLs with Mercury Devices). Each PLL is driven by a dedicated clock pin. Four dedicated global clock lines and six dedicated fast I/O lines share up to 12 internal PLL inputs. 2 Altera Corporation

3 Figure 1 shows the PLL connections to dedicated global clock and fast I/O lines. Figure 1. Dedicated Global Clock & Fast Line Connections for EP1M350 Devices Dedicated Fast Global Clocks I/O Lines G1 G3 F1 F3 F5 CLK3 CLKLK_FBIN3 CLKLK_OUT3 FAST3 inclock clock0 PLL3 clock1 fbin clock_ext clock2 clock0 inclock clock1 PLL1 clock2 clock_ext fbin CLK1 CLKLK_FBIN1 CLKLK_OUT1 FAST1 CLK4 CLKLK_FBIN4 CLKLK_OUT4 FAST4 inclock clock0 PLL4 clock1 fbin clock_ext clock2 G2 G4 F2 F4 F6 clock0 inclock clock1 PLL2 clock2 clock_ext fbin CLK2 CLKLK_FBIN2 CLKLK_OUT2 FAST2 The Mercury device IOE selects the clock, clear, clock enable, and output enable controls from a network of I/O control signals called the peripheral control bus. The peripheral control bus uses high-speed drivers to minimize signal skew across devices. In addition to the four global clock signals, Mercury IOE register clock input can be fed by six fast global signals and two row fast I/O signals. Flexible-LVDS I/O Receiver Operation The Flexible-LVDS I/O receiver uses the Mercury device s DDR input circuitry (a register pair and latch) to receive high-speed serial data. Figure 2 shows an IOE configuration for a DDR input. The DDR input circuitry consists of a pair of registers and a latch. The registers are used to capture the high-speed serial data. One register captures the data on the positive edge of the higher-frequency clock (generated by PLL) and the DDR input/output (DDRIO) latch feeds the other register. Figure 3 shows the DDR timing relation between the incoming serial data and the lower-frequency clock. In this example, the inclock signal is running at half the speed of the incoming data. However, other combinations are possible. Figure 4 shows the DDR input and the other modules used in a Flexible-LVDS receiver design to interface with the system logic. Altera Corporation 3

4 Figure 2. IOE Configured for DDR Input Associated LAB Local Interconnect Two Row Local Fast Signals Six Fast Global Signals Four Dedicated Clocks V CCIO Optional PCI Clamp Column and Priority Column OE Register D Q V CCIO Programmable Pull-Up ENA CLRN/PRN Chip-Wide Reset Input Register D Q Input Pin to Input Register Delay Bus-Hold Circuit ENA CLRN/PRN D PRN Q ENA Latch Priority Row (for Associated Logic Array Block (LAB) Row) Row (for Associated LAB Row) 4 Altera Corporation

5 Figure 3. DDR Timing Relation Between Incoming Serial Data & Lower- Frequency Clock inclock datain B0 A0 B1 A1 B2 A2 B3 A3 latch_out dataout_l dataout_h XX B0 B1 B2 XX B0 B1 B2 XX A0 A1 A2 B3 Figure 4. Flexible-LVDS Receiver Interface DDR Input Circuit datain DFF dataout_h Shift Register Latch Register Mercury Logic Array latch_out dataout_h DFF Shift Register Clock inclock PLL 1 2 Flexible-LVDS I/O Transmitter Operation The Flexible-LVDS I/O transmitter uses the Mercury device s DDR output circuitry (a register pair and a multiplexer) to transmit high-speed serial data. Figure 5 shows an IOE configuration for a DDR output. The registers capture the parallel data from the logic array on the higherfrequency clock (generated by PLL), and the multiplexer transmits the data in synchronization with the higher-frequency clock. Altera Corporation 5

6 Figure 5. IOE Configured for DDR Output Associated LAB Local Interconnect Two Row Local Fast Signals Six Fast Global Signals Four Dedicated Clocks OE Register D Q ENA CLRN/PRN V CCIO Optional PCI Clamp Chip-Wide Reset V CCIO Programmable Pull-Up Output Register D Q ENA CLRN/PRN 0 1 Output Propagation Delay Drive Strength Control Open-Drain Output Slew Control Bus-Hold Circuit Figure 6 shows the DDR timing relation between the parallel data and the lower-frequency clock. In this example, the inclock signal is running at half the speed of the data. However, other combinations are possible. Figure 7 shows the DDR output and the other modules used in a Flexible-LVDS transmitter design to interface with the system logic. 6 Altera Corporation

7 Figure 6. DDR Timing Relation Between Parallel Data & Clock inclock dataout_l dataout_h dataout B0 B1 B2 B3 A0 A1 A2 A3 XX A0 B0 A1 B1 A2 B2 A3 Figure 7. Flexible-LVDS I/O Transmitter Interface DDR Output Circuit D0, D2 Shift Register DFF Mercury Logic Array dataout_l dataout dataout_h D1, D3 Shift Register DFF 1 PLL 2 1 inclock Quartus II Implementation Designing with Flexible-LVDS I/O banks requires the ddio megafunction in the Altera Quartus II software. To receive or transmit high-speed data, designers must implement other functions such as serial shift registers and PLLs. The following sections discuss an example design that consists of both a receiver and a transmitter circuit in VHDL for I/O buffers. This design is also available on the Altera web site at Although this example is for 8-bit-wide systems, it can easily be modified for other widths. Altera Corporation 7

8 Building an 8-Bit Flexible-LVDS Receiver The DDR input register receives the serial data and separates the odd-bit and even-bit data. The odd- and even-bit data are deserialized using the shift register pair. A third register, clocked by the low-frequency clock, drives the parallel data to the system design and logic array. Figure 8 shows all the modules necessary for a single Flexible-LVDS channel to receive serial data. Figure 8. Complete Receiver Module inclk pll_clk_en serial_input clk_en PLL (1) pll1 (1) inclock clock0 inclocken clock1 locked inst DDR Input (2) flex_lvds_input datain[0] dataout_h[0] inclock dataout_l[0] inclocken ddio input inst1 clk1 output h[0] l[0] datah[3] datal[3] datah[2] datal[2] datah[1] datal[1] datah[0] datal[0] inst11 inst15 inst12 inst16 inst13 inst17 inst14 inst18 data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] clk_en l[0] Shift Registers 1 Shift Registers 2 Third Set of Registers lpm_shiftrega lpm_shiftrega DFF left shift left shift clock clock PRN enable shiftin q[3..0] datal[3..0] clk_en h[0] enable shiftin q[3..0] datah[3..0] data[7..0] D Q inst3 inst2 clk1 CLRN inst4 dataout[7..0] Notes to Figure 8: (1) PLL block and clock0 frequency multiplication factor = 4; clock1 frequency multiplication factor = 1. (2) The registers in the IOE should be set to power up low. The DDR input (altddio_in) block captures the serial data and parses the data into two outputs. The general-purpose PLL block generates the higher-frequency clock () for the deserialization registers and the lower-speed clock for the register that feeds the parallel data to the internal logic. The inclk signal is multiplied by a factor of four, generating the clock signal required by the shift registers for deserializing the data. The multiplication factor may be changed for different deserializing factors. 8 Altera Corporation

9 The PLL output clocks a pair of shift registers, which convert data from serial to parallel. The even data bits 0, 2, 4, and 6 and the odd data bits 1, 3, 5, and 7 are generated by the two shift registers. The shift registers deserialize the data, which is then fed through a third set of registers before it drives the system design and core logic. PLL clk1 generates the slow clock in order to clock the third set of registers. Eight wires reconstruct the data bits and make the connection between the Flexible-LVDS circuitry and the third set of registers. Building an 8-bit Flexible-LVDS Transmitter The DDR registers receive the separated odd-bits and even-bits of the output data and recombines them into serial data. The DDR output module uses a higher-frequency clock generated by the general-purpose PLL module to transmit the serial data. A counter triggers the shift register to receive data every fourth clock cycle. Figure 9 shows all the modules necessary for a single Flexible-LVDS channel to transmit serial data. Altera Corporation 9

10 Figure 9. Complete Transmitter Module eq[3] datah[3..0] clk_en eq[3] datal[3..0] clk_en Shift Register 1 Serializer left shift load data[3..0] clock shiftout enable inst1 Shift Register 2 Serializer left shift load data[3..0] clock shiftout enable inst3 PLL (1) hout lout in1 in3 in5 in7 in6 in4 in2 in0 data[7] data[5] data[3] data[1] data[6] data[4] data[2] data[0] inst19 inst20 inst21 inst22 inst23 inst24 inst25 inst26 datah[3] datah[2] datah[1] datah[0] datal[3] datal[2] datal[1] datal[0] inclk inclock pll1 clock0 pll_clk_en inclocken locked output lpm_counter inst4 hout Lout DDR Output (2) flex_lvds_out datain_h[0] dataout[0] datain_l[0] serial_out clock inst2 eq[] eq[15..0] clk_en outclock outclocken inst ddio output Notes to Figure 9: (1) PLL block and clock0 frequency multiplication factor = 4. (2) The registers in the IOE should be set to power up low. The inclk signal is multiplied by a factor of four, generating the clock signal, which the shift registers require to serialize the data. A pair of shift registers is clocked by to serialize the data. Data bits 0, 2, 4, and 6 are connected to the input of one shift register, and data bits 1, 3, 5, and 7 are connected to the input of the other shift register. The DDR output (altddio_out) block captures data on both clock edges and combines the data to a single output. 10 Altera Corporation

11 Assigning I/O Standards to Flexible-LVDS Pins in the Quartus II Software Flexible-LVDS pins in EP1M350 devices are dual-purpose pins; by default, the Quartus II software implements these pins as single-ended LVTTL. To use these dual-purpose Flexible-LVDS pins as differential I/O pins, the designer has to manually make the I/O assignment. Follow the steps below to make I/O assignments for the Flexible-LVDS receiver and transmitter pins: 1. Open or create a project. 2. Choose Compiler Settings (Processing menu). 3. Click the Chips & Devices tab. 4. Select Mercury as the target device family. 5. Select the target device in the Available list of devices. 6. Click the Assign Pins button. 7. Select the Flexible-LVDS pin to which you want to make an I/O assignment from the Available pins & existing assignments list. 8. If there is an existing assignment to the selected pin, click Delete (under Assignment) to delete the node name assignment from the pin. 9. Assign a new node name to the pin or change the existing node name assignment for the pin (under Assignment) by typing a node name in the Pin name box or copying the node name to the Assign Pins dialog box with the Node Finder. 10. Select the I/O standard as LVDS or LVPECL and click Add. 11. Repeat steps 6 to 10 for each additional Flexible-LVDS pin assignment you want to make, change, or delete. 12. Click OK in the Assign Pins dialog box, Apply, and OK in the Compiler Settings window. In addition to the Assign Pins dialog box, you can assign I/O standards using the Assignment Organizer dialog box (Tools menu). The advantage of using the Assign Pins dialog box is that you can set pin and I/O standard assignments in one dialog box. Figure 10 shows the Assign Pins dialog box with both pin and I/O standard assignments. Altera Corporation 11

12 Figure 10. Assign Pins Dialog Box When using Flexible-LVDS I/O pins, designers cannot place non-lvds output pins in the adjacent two I/O pins of the receiver and transmitter blocks in the same I/O bank. This requirement only applies to the I/O banks that share the same V CCIO. Switching outputs on these pins could affect the LVDS pins and degrade the performance. The only exception is the PLL LOCK pin, because it only toggles infrequently. Figure 11 shows the Mercury device I/O bank layout. Banks 5 through 16 have dualpurpose Flexible-LVDS pins. 12 Altera Corporation

13 Figure 11. I/O Bank Layout Notes (1), (2) ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB (3) Bank 1/Receiver Bank 2/Transmitter Bank 3/Receiver Bank 4/Transmitter Associated I/O Row and LAB Row Bank 5 Bank 6 Bank 7 Bank 8 Associated I/O Row and LAB Row Bank 9 Bank 10 Bank 11 Bank 12 Associated I/O Row and LAB Row Bank 13 Bank 14 Bank 15 Bank 16 Associated I/O Row and LAB Row ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB ESB Notes to Figure 11 (1) The following banks are not shown: Bank 17 (contains dedicated configuration and control pins), Bank 18 (contains dedicated JTAG pins: TCK, TDI, TDO, TMS, and TRST), Bank 19 (contains CLKLK_OUT1p/n and its output power), Bank 20 (contains CLKLK_OUT2p/n and its output power), Bank 21 (contains CLKLK_OUT3p/n and its output power), and Bank 22 (contains CLK_OUT4p/n and its output power). (2) Banks 1 and 3 can have their own V CCIO and V REF setting. Banks 2, and 4 through 16 must have the same V CCIO power. Banks 5 through 16 must have the same V CCIO power, but can have unique V REF settings. (3) ESB: embedded system block. Conclusion Revision History Mercury devices provide a comprehensive differential signaling solution by offering up to 18 channels of HSDI support as well as up to 100 channels of Flexible-LVDS support. The HSDI support addresses topof-the-line performance requirements and can be configured either in CDR mode, with support for data rates as high as 1.25 Gbps, or in sourcesynchronous mode in a True-LVDS solution. The Flexible-LVDS channels enable a wide variety of high-performance applications, and address both the LVDS and LVPECL I/O standards. Flexible-LVDS can be easily implemented through the use of the DDR registers built into the IOE in conjunction with internally dedicated buffers, and can support data rates of up to 400 Mbps. This combination produces an unmatched flexibility and a comprehensive bandwidth solution. The information contained in the AN 186: Using Flexible-LVDS Circuitry in Mercury Devices version 1.1 supersedes information published in previous versions. Version 1.1 The following changes were made to the AN 186: Using Flexible-LVDS Circuitry in Mercury Devices version 1.1: Updated the transmit or receive value to 400 Mbps from 624 Mbps. Altera Corporation 13

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