Using MAX 3000A Devices as a Microcontroller I/O Expander
|
|
- Abel Cox
- 6 years ago
- Views:
Transcription
1 Using MAX 3000A Devices as a Microcontroller I/O Expander August 2003, Ver 1.0 Application Note 265 Introduction Advantages of Using MAX 3000A Devices Many microcontrollers and microprocessors limit I/O ports and pins to conserve pin counts and reduce package sizes. For many microcontroller (e.g., PIC, 051, and SX) or microprocessor basedsystems, the system design requires more I/O ports or pins than the microcontroller provides. To increase the number of I/O pins without changing the microcontroller, I/O expansion provides a solution. With up to 20 I/O pins and MultiVolt TM I/O capability, Altera MAX 3000A devices allow you to implement microcontroller I/O expansion in microcontroller or microprocessorbased systems. This application note explains how to implement a microcontroller I/O expander in MAX 3000A devices. A key advantage of using MAX 3000A devices as a microcontroller I/O expander is the integration of logic functions across your entire board. The flexibility of a programmable device means that not only can the I/O expansion function be implemented, but other functions can be integrated such as LED drivers or busbridging logic. This integration allows you to reduce component count across the board, minimizing cost and maximizing board space efficiency. Another advantage in using MAX 3000A devices is the MultiVolt I/O capability which enables MAX 3000A devices to interface to 5.0V, 3.3V, and 2.5V I/O pins. This capability allows you to implement voltagelevel shifting to interface older 5.0V devices with newer 3.3V or 2.5V devices or microcontrollers. The large numbers of I/O pins on MAX 3000A devices make it an ideal device for microcontroller I/O expansion. Table 1 shows the maximum user I/O pins available in MAX 3000A devices. The maximum I/O pins available are 20 which translates to 26, bit ports. Additionally, insystem programmability (ISP) means that these features come with the flexibility of reprogrammability on the board. Table 1. Maximum User I/O Pins in MAX 3000A Devices EPM3032A EPM3064A EPM312A EPM3256A EPM3512A Maximum User I/O Pins Altera Corporation 1
2 Implementing a Microcontroller I/O Expander in MAX 3000A Devices The I/O expander design example includes four ports (A, B, C, and D) which can be independently programmed as I/O ports. Each port is bits wide and is bidirectional, becoming an input port when tristated. You can connect the microcontroller unit (MCU) port to or from any port (A, B, C, or D) to perform read and write operations. Figure 1 shows the block diagram of the design example for the microcontroller I/O expander. Figure 1. Block Diagram for Microcontroller I/O Expander Design Example in MAX 3000A Devices Input Data Latch Port A Port B MCU Port I/O Ports 4 2 I/O Setting Data Register 2 4 I/O Ports Output Data Latch Port C Port D CS RST CONF LOAD WR RD MODE 2 Altera Corporation
3 Table 2 lists all the functions of the input and output pins. Table 2. Input & Output Pins in a Microcontroller I/O Expander Example Design I/O Name Type Description Active MCU port Bidirectional bit bidirectional data lines that interface with the MCU data bus. The bit data can be written into or read out of the microcontroller I/O expander on the WR and RD signals. Configuration data is also transmitted through this port. The MODE signal determines whether the MCU port is a data or address bus. CS Input Input signal to select the device. Low RST Input Input signal to reset the device and all internal Low registers. CONF Input This control signal stores the sddress[5..0] from the MCU port on the falling edge of CONF into the configuration registers. Data on address[7..6] is ignored. (The operation will be discussed later in this application note.) LOAD Input This control signal stores the address[1..0] from the MCU port on the falling edge of LOAD into configuration registers. Data on address[7..2] is ignored. (The operation will be discussed later in this application note.) WR Input Input signal that causes the data on the MCU port to be written to the enabled port (A, B, C, or D). RD Input Input signal that enables the data bus transfer to the MCU port from the enabled port (A, B, C, or D). MODE Input Tristates the MCU port when this signal is high. The MCU port setting (input or output) depends on the configuration registers when MODE is low. Port A Bidirectional bit, generalpurpose I/O port that can be programmed to either output or input mode. Port B Bidirectional bit, generalpurpose I/O port that can be programmed to either output or input mode. Port C Bidirectional bit, generalpurpose I/O port that can be programmed to either output or input mode. Port D Bidirectional bit, generalpurpose I/O port that can be programmed to either output or input mode. Low Low Low Low Altera Corporation 3
4 Functional Description The microcontroller I/O expander operates as a slave that sends and receives data through the MCU port. Data is sent through the I/O expander at the hightolow transition of the WR signal (with CS set to low) and received at the hightolow transition of the RD signal (with CS set to low). Write Mode In write mode, the selected port (A, B, C, or D) is configured as an output port and the MCU port as an input port. Therefore, when the RW signal changes from high to low (with CS set to low), the data from the MCU port is written into the output data latch of the selected port. Read Mode In read mode, the selected port (A, B, C, or D) is configured as an input port and the MCU port as an output port. When the RD signal changes from high to low (with CS set to low), the data from the selected port is written into the input data latch of the MCU port. 1 During read and write operation, the MODE signal control pin must be set to low. See Design Verification on page 6 for an example of read and write operations. Configuration of the Microcontroller I/O Expander Configuration of the microcontroller I/O expander is used to determine whether the port is input or output and enabled or disabled. Activation of the new configuration occurs with a single configuration pulse of the CONF signal. Data controlling the microcontroller I/O expander is stored in a set of 6bit registers. Data to be written into these registers, consisting of 4 bits for I/O port configuration data and 2 bits for the enabled port address data, is placed on the input address bus (MCU port) with the MODE signal set to high and the CS signal set to low. Input data is stored in the configuration registers at the hightolow transition of the CONF signal input pin with the CS signal set to low. This transition causes the state of the microcontroller I/O expander to be set to the selected configuration. When the LOAD signal is asserted from high to low (with CS set to low), only 2 bits of the enabled port address data (bit1 and bit0) are stored in the configuration registers. Use the LOAD signal when you need to select the enabled port to perform read or write operation instead of configuring the ports. Figure 2 shows the functionality of every bit in the address bus during configuration mode. 4 Altera Corporation
5 Figure 2. I/O Expander Address Bus Configuration Function A7 A6 A5 A4 A3 A2 A1 A0 bit 76: bit 5: bit 4: bit 3: bit 2: bit 10: A7:A6: No functionality A5: Port D configuration bit 0 = Configured as input 1 = Configured as output A4: Port C configuration bit 0 = Configured as input 1 = Configured as output A3: Port B configuration bit 0 = Configured as input 1 = Configured as output A2: Port A configuration bit 0 = Configured as input 1 = Configured as output A1:A0: Port Address Table 3 shows the address contents to enable the particular I/O ports. Table 3. Port Addresses A1:A0 Port 00 A 01 B 10 C 11 D MCU port direction, input or output, cannot be directly configured by the user. It is configured internally by the selected enabled port. For example, if the enabled port is in input mode, the MCU port is set to an output mode. However, you can use the MODE signal control pin to tristate the MCU port so that it becomes an input port, allowing you access to the configuration registers. Reset mode is also supported in the microcontroller I/O expander reference design. When the RST signal is asserted (with CS set to low), the contents of all registers are reset to zero and the entire I/O expander is in its initial state, where all the ports (including the MCU port) are set to input mode. Altera Corporation 5
6 MAX 3000A Implementation The microcontroller I/O expander design example was targeted to 12macrocell MAX 3000A devices (EPM312ATC100) using the Quartus II software. The design utilization in the 12macrocell MAX 3000A device is shown in Table 4. The data in Table 4 shows that there is sufficient resources (I/O pins and macrocells) remaining in the device for the implementation of the other logic in the system. Table 4. Microcontroller I/O Expander EPM312A Utilization Resource Available Used Utilization (%) Macrocells Flipflops I/O Pins Design Verification Design verification of a microcontroller I/O expansion was accomplished by using the Quartus II software. The design was verified both in functional and timing simulation in MAX 3000A devices (EPM312ATC100). Figures 3 and 4 show the timing simulation of the microcontroller I/O expansion during read and write operation. 6 Altera Corporation
7 Figure 3. Microcontroller I/O Expansion Write Mode Timing Simulation Configure the Microcontroller I/O Expander The HightoLow Transition of the WR Signal Creates New Output Values Change the Enabled Port The WR Signal Creates New Output Values With all the I/O pins in tristate mode, each port is initialized. After initialization, Port A and Port B are configured as output, Port C and Port D are configured as input, and Port B is enabled for write operation. When the WR signal asserts a hightolow transition, the MCU port data (146) is latched to the output Port B. In the last section of simulation, Port A is enabled at the hightolow transition of the LOAD signal. When the WR signal asserts a hightolow transition, the MCU port data (10) is latched to the output Port A. Altera Corporation 7
8 Figure 4. Microcontroller I/O Expansion Read Mode Timing Simulations The RD Signal Creates New Output Values Configure the Microcontroller I/O Expander The HightoLow Transition of the WR Signal Creates New Output Values Change the Enabled Port With all the I/O pins in tristate mode, each port is initialized. After initialization, all ports (A, B, C, and D) are configured as input and Port C is enabled for read operation. When the read signal asserts a hightolow transition, the Port C data is latched to the MCU port. While in the last part of the simulation, Port D is enabled at the hightolow transition of the LOAD signal. When the RD signal asserts a hightolow transition, the Port D data (146) is latched to the MCU port. Altera Corporation
9 Microcontroller I/O Expander Applications Figures 5 shows how to increase the microcontroller s I/O ports using the I/O expander. This microcontroller I/O expander can be targeted or modified to target to any bit microcontroller (e.g., PIC and 051). Figure 5. Application of Microcontroller I/O Expander Microcontroller I/O Expander RD output WR output RD WR Port A CS output LOAD output CS LOAD Port B CONF output MODE output CONF MODE Port C RST output Microcontroller I/O Port RST MCU Port Port D Conclusion With up to 20 I/O pins and MultiVolt I/O capability, Altera MAX 3000A devices allow you to implement microcontroller I/O expansion in a single device. MAX 3000A devices enable you to design custom microcontroller I/O expanders with additional features other than the example provided in this application note. Altera Corporation 9
10 101 Innovation Drive San Jose, CA (40) Applications Hotline: (00) 00EPLD Literature Services: Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Printed on recycled paper 10 Altera Corporation
Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander
Using MAX II & MAX 3000A Devices as a Microcontroller I/O Expander March 2004, ver 2.0 Application Note 265 Introduction Advantages of Using MAX II & MAX 3000A Devices Many microcontroller and microprocessors
More informationMatrices in MAX II & MAX 3000A Devices
Crosspoint Switch Matrices in MAX II & MAX 3000A Devices March 200, ver. 2.0 Application Note 29 Introduction With a high level of flexibility, performance, and programmability, you can use crosspoint
More informationImplementing LED Drivers in MAX Devices
Implementing LE rivers in MAX evices ecember 2002, ver. 1.0 Application Note 286 Introduction Commercial LE river Chips iscrete light-emitting diode (LE) driver chips are common on many system boards.
More informationActive Serial Memory Interface
Active Serial Memory Interface October 2002, Version 1.0 Data Sheet Introduction Altera Cyclone TM devices can be configured in active serial configuration mode. This mode reads a configuration bitstream
More informationImplementing LED Drivers in MAX and MAX II Devices. Introduction. Commercial LED Driver Chips
Implementing LE rivers in MAX and MAX II evices October 2008 AN-286-2.3 Introduction iscrete LE driver chips are common on many system boards. Altera MAX II, MAX 7000B, MAX 7000A, MAX 3000A, and MAX 7000S
More informationDSP Development Kit, Stratix II Edition
DSP Development Kit, Stratix II Edition August 2005, Development Kit version 1.1.0 Errata Sheet This document addresses known errata and documentation changes the DSP Development Kit, Stratix II Edition
More informationUsing the Nios Development Board Configuration Controller Reference Designs
Using the Nios Development Board Controller Reference Designs July 2006 - ver 1.1 Application Note 346 Introduction Many modern embedded systems utilize flash memory to store processor configuration information
More informationEstimating Nios Resource Usage & Performance
Estimating Nios Resource Usage & Performance in Altera Devices September 2001, ver. 1.0 Application Note 178 Introduction The Excalibur Development Kit, featuring the Nios embedded processor, includes
More informationSimulating the PCI MegaCore Function Behavioral Models
Simulating the PCI MegaCore Function Behavioral Models August 2001, ver. 1.0 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,
More informationWhite Paper Configuring the MicroBlaster Passive Serial Software Driver
White Paper Configuring the MicroBlaster Passive Serial Software Driver Introduction The MicroBlaster TM software driver is designed to configure Altera programmable logic devices (PLDs) through the ByteBlasterMV
More informationIntroduction. Design Hierarchy. FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow
FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow February 2002, ver. 2.0 Application Note 171 Introduction To maximize the benefits of the LogicLock TM block-based design methodology in the
More informationFPGA Design Security Solution Using MAX II Devices
White Paper FPGA Solution Using MAX II Devices Introduction SRAM-based FPGAs are volatile devices. They require external memory to store the configuration data that is sent to them at power up. It is possible
More informationSimple Excalibur System
Excalibur Solutions Simple Excalibur System August 2002, ver. 1.0 Application Note 242 Introduction This application note describes a simple Excalibur system design that consists of software running on
More informationUsing the Serial FlashLoader With the Quartus II Software
Using the Serial FlashLoader With the Quartus II Software July 2006, ver. 3.0 Application Note 370 Introduction Using the Joint Test Action Group () interface, the Altera Serial FlashLoader (SFL) is the
More informationSimultaneous Multi-Mastering with the Avalon Bus
Simultaneous Multi-Mastering with the Avalon Bus April 2002, ver. 1.1 Application Note 184 Introduction The Excalibur Development Kit, featuring the Nios embedded processor version 2.1 supports an enhanced
More informationPOS-PHY Level 4 MegaCore Function
POS-PHY Level 4 MegaCore Function November 2004, MegaCore Version 2.2.2 Errata Sheet Introduction This document addresses known errata and documentation changes for version v2.2.2 of the POS-PHY Level
More informationUTOPIA Level 2 Slave MegaCore Function
UTOPIA Level 2 Slave MegaCore Function October 2005, Version 2.5.0 Release Notes These release notes for the UTOPIA Level 2 Slave MegaCore function contain the following information: System Requirements
More informationCyclone II FPGA Family
ES-030405-1.3 Errata Sheet Introduction This errata sheet provides updated information on Cyclone II devices. This document addresses known device issues and includes methods to work around the issues.
More informationNios Soft Core Embedded Processor
Nios Soft Core Embedded Processor June 2000, ver. 1 Data Sheet Features... Preliminary Information Part of Altera s Excalibur TM embedded processor solutions, the Nios TM soft core embedded processor is
More informationEnhanced Configuration Devices
Enhanced Configuration Devices October 2007, Version 1.2 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices
More informationTable 1 shows the issues that affect the FIR Compiler v7.1.
May 2007, Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the Altera, v7.1. Errata are functional defects or errors, which may cause an Altera MegaCore function
More informationFPGAs Provide Reconfigurable DSP Solutions
FPGAs Provide Reconfigurable DSP Solutions Razak Mohammedali Product Marketing Engineer Altera Corporation DSP processors are widely used for implementing many DSP applications. Although DSP processors
More informationAIRbus Interface. Features Fixed width (8-, 16-, or 32-bit) data transfers (dependent on the width. Functional Description. General Arrangement
AIRbus Interface December 22, 2000; ver. 1.00 Functional Specification 9 Features Fixed width (8-, 16-, or 32-bit) data transfers (dependent on the width of the data bus) Read and write access Four-way
More informationPOS-PHY Level 4 POS-PHY Level 3 Bridge Reference Design
Level 4 Bridge Reference Design October 2001; ver. 1.02 Application Note 180 General Description This application note describes how the Level 4 Bridge reference design can be used to bridge packet or
More informationWhite Paper Using the MAX II altufm Megafunction I 2 C Interface
White Paper Using the MAX II altufm Megafunction I 2 C Interface Introduction Inter-Integrated Circuit (I 2 C) is a bidirectional two-wire interface protocol, requiring only two bus lines; a serial data/address
More informationArria II GX FPGA Development Board
Arria II GX FPGA Development Board DDR2 SODIMM Interface 2011 Help Document DDR2 SODIMM Interface Measurements were made on the DDR2 SODIMM interface using the Board Test System user interface. The Address,
More informationFFT/IFFT Block Floating Point Scaling
FFT/IFFT Block Floating Point Scaling October 2005, ver. 1.0 Application Note 404 Introduction The Altera FFT MegaCore function uses block-floating-point (BFP) arithmetic internally to perform calculations.
More informationDSP Builder. DSP Builder v6.1 Issues. Error When Directory Pathname is a Network UNC Path
March 2007, Version 6.1 Errata Sheet This document addresses known errata and documentation changes for DSP Builder version 6.1. Errata are functional defects or errors which may cause DSP Builder to deviate
More informationNios PIO. General Description. Functional Description
Nios PIO January 2003, Version 3.1 Data Sheet General Description Functional Description The Nios parallel input/output (PIO) module is an Altera SOPC Builder library component included in the Nios development
More informationSimulating the Reed-Solomon Model
July 2000, ver. 1 Simulating the Reed-Solomon Model with the Visual IP Software User Guide Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera, and
More informationExcalibur Solutions DPRAM Reference Design
Excalibur Solutions DPRAM Reference Design August 22, ver. 2.3 Application Note 173 Introduction The Excalibur devices are excellent system development platforms, offering flexibility, performance, and
More informationTable 1 shows the issues that affect the FIR Compiler, v6.1. Table 1. FIR Compiler, v6.1 Issues.
December 2006, Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the Altera FIR Compiler, v6.1. Errata are functional defects or errors, which may cause an Altera
More informationNios II Embedded Design Suite 6.1 Release Notes
December 2006, Version 6.1 Release Notes This document lists the release notes for the Nios II Embedded Design Suite (EDS) version 6.1. Table of Contents: New Features & Enhancements...2 Device & Host
More informationRapidIO MegaCore Function
March 2007, MegaCore Function Version 3.1.1 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.1. Errata are functional defects
More informationNios DMA. General Description. Functional Description
Nios DMA January 2003, Version 1.1 Data Sheet General Functional The Nios DMA module is an Altera SOPC Builder library component included in the Nios development kit. The DMA module allows for efficient
More informationVideo and Image Processing Suite
Video and Image Processing Suite December 2006, Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the MegaCore functions in the Video and Image Processing Suite,
More informationRapidIO Physical Layer MegaCore Function
RapidIO Physical Layer MegaCore Function April 2005, MegaCore version 2.2.1 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.2.1 of the RapidIO Physical
More informationByteBlaster II Parallel Port Download Cable
ByteBlaster II Parallel Port Download Cable December 2002, Version 1.0 Data Sheet Features Allows PC users to perform the following functions: Program MAX 9000, MAX 7000S, MAX 7000AE, MAX 7000B, MAX 3000A,
More informationSimulating the PCI MegaCore Function Behavioral Models
Simulating the PCI MegaCore Function Behavioral Models February 2003, ver. 1.2 Application Note 169 Introduction Altera intellectual property (IP) MegaCore functions are developed and pre-tested by Altera,
More informationUsing Flexible-LVDS I/O Pins in
Using Flexible-LVDS I/O Pins in APEX II Devices August 2002, ver. 1.1 Application Note 167 Introduction Recent expansion in the telecommunications market and growth in Internet use have created a demand
More informationLegacy SDRAM Controller with Avalon Interface
Legacy SDRAM Controller with Avalon Interface January 2003, Version 1.0 Data Sheet Introduction PTF Assignments SDRAM is commonly used in cost-sensitive applications requiring large amounts of memory.
More informationDecember 2002, ver. 1.3 Application Note 191. Six individual interrupts Six-bit priority scheme Five-bit priority scheme plus one individual interrupt
Excalibur Solutions Using the Interrupt Controller December 22, ver..3 Application Note 9 Introduction This document describes the operation of the interrupt controller for the Excalibur devices, particularly
More informationFigure 1. Device Package Ordering Information for Stratix, Stratix GX, Cyclone, APEX 20KC, APEX II, Mercury & Excalibur Devices EP1S 25 F 780 C 5 N
April 2003, ver. 15 Altera Devices Figures 1 and 2 explain the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes.
More informationDDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller October 2005, Compiler Version 3.3.0 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.0 contain the following information: System
More informationAN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current
AN 547: Putting the MAX II CPLD in Hibernation Mode to Achieve Zero Standby Current January 2009 AN-547-10 Introduction To save power, the MAX II CPLD can be completely powered down into hibernation mode
More informationZBT SRAM Controller Reference Design
ZBT SRAM Controller Reference Design for APEX II Devices December 2001, ver. 1.0 Application Note 183 Introduction As communication systems require more low-latency, high-bandwidth interfaces for peripheral
More informationPCI Express Multi-Channel DMA Interface
2014.12.15 UG-01160 Subscribe The PCI Express DMA Multi-Channel Controller Example Design provides multi-channel support for the Stratix V Avalon Memory-Mapped (Avalon-MM) DMA for PCI Express IP Core.
More informationDesign Verification Using the SignalTap II Embedded
Design Verification Using the SignalTap II Embedded Logic Analyzer January 2003, ver. 1.0 Application Note 280 Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera
More informationAN423: Configuring the MicroBlaster Passive Serial Software Driver
AN423: Configuring the MicroBlaster Passive Serial Software Driver June 2008, version 1.1 Introduction The MicroBlaster TM software driver configures Altera programmable logic devices (PLDs) in passive
More informationDDR & DDR2 SDRAM Controller
DDR & DDR2 SDRAM Controller December 2005, Compiler Version 3.3.1 Release Notes These release notes for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1 contain the following information: System
More informationBenefits of Embedded RAM in FLEX 10K Devices
Benefits of Embedded RAM in FLEX 1K Devices January 1996, ver. 1 Product Information Bulletin 2 Introduction Driven by the demand to integrate many more digital functions in a single device, custom logic
More informationEnhanced Configuration Devices
Enhanced Configuration Devices July 2008, Version 1.3 Errata Sheet Introduction Intel-Flash- Based EPC Device Protection f This errata sheet provides updated information on enhanced configuration devices
More informationExcalibur Solutions Using the Expansion Bus Interface. Introduction. EBI Characteristics
Excalibur Solutions Using the Expansion Bus Interface October 2002, ver. 1.0 Application Note 143 Introduction In the Excalibur family of devices, an ARM922T processor, memory and peripherals are embedded
More informationSONET/SDH Compiler. Introduction. SONET/SDH Compiler v2.3.0 Issues
January 2005, Compiler Version 2.3.0 Errata Sheet Introduction This document addresses known errata and documentation changes for version 2.3.0 of the SONET/SDH Compiler. Errata are design functional defects
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler May 2006, Compiler Version 3.3.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 3.3.1.
More informationWhite Paper AHB to Avalon & Avalon to AHB Bridges
White Paper AHB to & to AHB s Introduction For years, system designers have been manually connecting IP peripheral functions to embedded processors, taking anywhere from weeks to months to accomplish.
More informationPCI Express Compiler. System Requirements. New Features & Enhancements
April 2006, Compiler Version 2.1.0 Release Notes These release notes for the PCI Express Compiler version 2.1.0 contain the following information: System Requirements New Features & Enhancements Errata
More informationIntroduction. Synchronous vs. Asynchronous Memory. Converting Memory from Asynchronous to Synchronous for Stratix & Stratix GX Designs
Converting from synchronous to Synchronous for Stratix & Stratix GX esigns November 2002, ver. 2.0 pplication Note 210 Introduction The Stratix TM and Stratix GX device families provide a unique memory
More informationImplementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs
Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs WP-01146-1.2 White Paper Since their introduction in the mid-1980s and across all end markets, CPLDs have been design
More informationNios Embedded Processor UART Peripheral
Nios Embedded Processor UART Peripheral March 2001, ver. 1.1 Data Sheet General Description The Nios universal asynchronous receiver/transmitter UART implements simple RS-232 asynchronous transmit and
More informationAN 549: Managing Designs with Multiple FPGAs
AN 549: Managing Designs with Multiple FPGAs October 2008 AN-549-1.0 Introduction Managing designs that incorporate multiple FPGAs raises new challenges that are unique compared to designs using only one
More informationE3 Mapper MegaCore Function (E3MAP)
MegaCore Function (E3MAP) March 9, 2001; ver. 1.0 Data Sheet Features Easy-to-use MegaWizard Plug-In generates MegaCore variants Quartus TM II software and OpenCore TM feature allow place-androute, and
More informationToolflow for ARM-Based Embedded Processor PLDs
Toolflow for ARM-Based Embedded Processor PLDs December 2000, ver. 1 Application Note Introduction The Excalibur embedded processor devices achieve a new level of system integration from the inclusion
More informationRapidIO MegaCore Function
March 2007, MegaCore Function Version 3.1.0 Errata Sheet This document addresses known errata and documentation issues for the Altera RapidIO MegaCore function version 3.1.0. Errata are functional defects
More informationDSP Builder Release Notes
April 2006, Version 6.0 SP1 Release Notes These release notes for DSP Builder version 6.0 SP1 contain the following information: System Requirements New Features & Enhancements Errata Fixed in This Release
More informationStratix FPGA Family. Table 1 shows these issues and which Stratix devices each issue affects. Table 1. Stratix Family Issues (Part 1 of 2)
January 2007, ver. 3.1 Errata Sheet This errata sheet provides updated information on Stratix devices. This document addresses known issues and includes methods to work around the issues. Table 1 shows
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler march 2007, Compiler Version 7.0 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version 7.0.
More informationSimulating Nios II Embedded Processor Designs
Simulating Nios II Embedded Processor Designs May 2004, ver.1.0 Application Note 351 Introduction The increasing pressure to deliver robust products to market in a timely manner has amplified the importance
More informationSimulating the ASMI Block in Your Design
2015.08.03 AN-720 Subscribe Supported Devices Overview You can simulate the ASMI block in your design for the following devices: Arria V, Arria V GZ, Arria 10 Cyclone V Stratix V In the Quartus II software,
More informationWhite Paper. Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core. Introduction. Parameters & Ports
White Paper Introduction Floating-Point FFT Processor (IEEE 754 Single Precision) Radix 2 Core The floating-point fast fourier transform (FFT) processor calculates FFTs with IEEE 754 single precision (1
More informationNios II Embedded Design Suite 7.1 Release Notes
Nios II Embedded Design Suite 7.1 Release Notes May 2007, Version 7.1 Release Notes This document contains release notes for the Nios II Embedded Design Suite (EDS) version 7.1. Table of Contents: New
More informationRLDRAM II Controller MegaCore Function
RLDRAM II Controller MegaCore Function November 2006, MegaCore Version 1.0.0 Errata Sheet This document addresses known errata and documentation issues for the RLDRAM II Controller MegaCore function version
More informationT3 Framer MegaCore Function (T3FRM)
MegaCore Function August 2001; ver. 1.02 Data Sheet Features Achieving optimum performance in the Altera APEX TM 20K device architecture, the multi-featured MegaCore Function meets your innovative design
More informationCORDIC Reference Design. Introduction. Background
CORDIC Reference Design June 2005, ver. 1.4 Application Note 263 Introduction The co-ordinate rotation digital computer (CORDIC) reference design implements the CORDIC algorithm, which converts cartesian
More informationArria II GX FPGA Development Board
Arria II GX FPGA Development Board Overview 2011 Signal Integrity Report Introduction Signal Integrity Analysis The ArriaII GX development kit board has several high speed interfaces. Each of these interfaces
More informationUsing Flexible-LVDS Circuitry in Mercury Devices
Using Flexible-LVDS Circuitry in Mercury Devices November 2002, ver. 1.1 Application Note 186 Introduction With the ever increasing demand for high bandwidth and low power consumption in the telecommunications
More informationByteBlaster II Download Cable User Guide
ByteBlaster II Download Cable User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com UG-BBII81204-1.1 P25-10324-00 Document Version: 1.1 Document Date: December 2004 Copyright
More informationImplementing LVDS in Cyclone Devices
Implementing LVDS in Cyclone Devices March 2003, ver. 1.1 Application Note 254 Introduction Preliminary Information From high-speed backplane applications to high-end switch boxes, LVDS is the technology
More informationWhite Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices
Introduction White Paper The Need for a High-Bandwidth Memory Architecture in Programmable Logic Devices One of the challenges faced by engineers designing communications equipment is that memory devices
More informationFFT MegaCore Function
FFT MegaCore Function March 2007, MegaCore Version 6.1 Errata Sheet This document addresses known errata and documentation issues for the FFT MegaCore function version 6.1. Errata are functional defects
More informationDDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler August 2007, Compiler Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the DDR and DDR2 SDRAM Controller Compiler version
More informationFor Quartus II Software. This Quick Start Guide will show you how to set up a Quartus
Quick Start Guide For Quartus II Software This Quick Start Guide will show you how to set up a Quartus II project, enter timing requirements, and compile the design into an Altera device. 1 Three-Step
More informationPOS-PHY Level 4 MegaCore Function (POSPHY4)
POS-PHY Level 4 MegaCore Function (POSPHY4) August 2001; ver. 1.00 Data Sheet Introduction Optimized for the Altera APEX TM II device architecture, the POS-PHY level 4 MegaCore function (POSPHY4) interfaces
More informationRemote Drive. Quick Start Guide. System Level Solutions, Inc. (USA) Murphy Avenue San Martin, CA (408) Version : 0.1.
Remote Drive Quick Start Guide, Inc. (USA) 14100 Murphy Avenue San Martin, CA 95046 (408) 852-0067 http://www.slscorp.com Version : 0.1.1 Date : July 17, 2007 Copyright 2007,.All rights reserved. SLS,
More informationIncreasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface
Increasing Productivity with Altera Quartus II to I/O Designer/DxDesigner Interface Steven Strell Senior Applications Engineer, Altera Corporation (408) 544-7624 sstrell@altera.com 1 Abstract Today s high-speed,
More information24K FFT for 3GPP LTE RACH Detection
24K FFT for GPP LTE RACH Detection ovember 2008, version 1.0 Application ote 515 Introduction In GPP Long Term Evolution (LTE), the user equipment (UE) transmits a random access channel (RACH) on the uplink
More informationUsing VCS with the Quartus II Software
Using VCS with the Quartus II Sotware December 2002, ver. 1.0 Application Note 239 Introduction As the design complexity o FPGAs continues to rise, veriication engineers are inding it increasingly diicult
More informationWhite Paper Understanding 40-nm FPGA Solutions for SATA/SAS
White Paper Understanding 40-nm Solutions for /SAS This white paper describes the and SAS protocols, how the protocols are used, explains the value and SAS in terms of usage in an, and illustrates how
More informationImplementing FIR Filters
Implementing FIR Filters in FLEX Devices February 199, ver. 1.01 Application Note 73 FIR Filter Architecture This section describes a conventional FIR filter design and how the design can be optimized
More informationUsing DCFIFO for Data Transfer between Asynchronous Clock Domains
Using DCFIFO for Data Transfer between Asynchronous Clock Domains, version 1.0 Application Note 473 Introduction In the design world, there are very few designs with a single clock domain. With increasingly
More informationStratix II vs. Virtex-4 Performance Comparison
White Paper Stratix II vs. Virtex-4 Performance Comparison Altera Stratix II devices use a new and innovative logic structure called the adaptive logic module () to make Stratix II devices the industry
More informationSONET/SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM)
July 2001; ver. 1.01 SONET/SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) Data Sheet Features Performs synchronous optical network (SONET)/synchronous digital hierarchy (SDH) framing and transport
More informationSameFrame Pin-Out Design for FineLine BGA Packages
SameFrame Pin-Out Design for Packages June 1999, er. 1 Application Note 90 Introduction A key adantage of designing with programmable logic is the flexibility which allows designers to quickly modify or
More informationExercise 1 In this exercise you will review the DSSS modem design using the Quartus II software.
White Paper DSSS Modem Lab Background The direct sequence spread spectrum (DSSS) digital modem reference design is a hardware design that has been optimized for the Altera APEX DSP development board (starter
More informationNios Timer. General Description. Functional Description
Nios Timer July 2003, Version 3.2 Data Sheet General Description Functional Description The Nios Timer module is an Altera SOPC Builder library component included in the Nios development kit. This SOPC
More informationDesign Guidelines for Using DSP Blocks
Design Guidelines for Using DSP Blocks in the Synplify Software April 2002, ver. 1.0 Application Note 193 Introduction Altera R Stratix TM devices have dedicated digital signal processing (DSP) blocks
More informationUsing MicroC/OS-II RTOS with the Nios II Processor Tutorial Preliminary Information
Using MicroC/OS-II RTOS with the Nios II Processor Tutorial Preliminary Information 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Copyright 2004 Altera Corporation. All rights
More informationUsing Verplex Conformal LEC for Formal Verification of Design Functionality
Using Verplex Conformal LEC for Formal Verification of Design Functionality January 2003, ver. 1.0 Application Note 296 Introduction The Altera Quartus II software, version 2.2, easily interfaces with
More informationDesigning with ESBs in APEX II Devices
Designing with ESBs in APEX II Devices March 2002, ver. 1.0 Application Note 179 Introduction In APEX TM II devices, enhanced embedded system blocks (ESBs) support memory structures, such as single-port
More informationMAX 10 User Flash Memory User Guide
MAX 10 User Flash Memory User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-M10UFM 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents MAX 10 User Flash Memory
More information