CSR1025 LGA Production Information Data Sheet 80-CE982-1 Rev. AA July 6, 2017 Qualcomm Technologies International, Ltd.

Transcription

1 CSR1025 LGA Production Information Data Sheet 80-CE982-1 Rev. AA July 6, 2017 Qualcomm Technologies International, Ltd. Device description Applications Bluetooth low energy technology single-mode SoC with G.722 audio codec Supported by Qualcomm Bluetooth Low Energy toolset and applications 16 bit RISC MCU, 256 KB internal SPI flash, 80 KB RAM, 192 KB ROM, 60 KB OTP 33 digital PIO, 2 analog AIO, SPI, I²C, I²S, quadrature decoders, 3D shutter/led PWM modules, key scanner, LCD glass drive, IR encoder, 10 bit auxiliary ADC Ultra low-power Bluetooth low energy technology radio v4.2 specification compliant radio 60-lead 8 x 8 x 0.75 mm 0.5 mm pitch LGA System architecture Bluetooth low energy technology: HID: keyboards, mice, touchpads, advanced remote controls with voice activation Sports and fitness sensors: heart rate, runner/cycle speed and cadence Health sensors: blood pressure, thermometer and glucose meters Mobile accessories: watches, proximity tags, alert tags and camera controls Smart home: heating/lighting control Qualcomm Mesh connectivity: Internet of Things control Ecosystem Bluetooth low energy technology Radio and Modem I/O UART LED PWM MCU PIO ROM OTP RAM MTP AIO Debug Flash 16 MHz Clock Generation LCD 2 I C / SPI 2 IS Qualcomm BlueCore, CSR chipsets, and Qualcomm Bluetooth Low Energy are products of Qualcomm Technologies International, Ltd. Qualcomm Mesh is a product of Qualcomm Technologies, Inc. Other Qualcomm products referenced herein are products of Qualcomm Technologies International, Ltd. Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. BlueCore and CSR are trademarks of Qualcomm Technologies International, Ltd., registered in the United States and other countries. Qualcomm Mesh is a trademark of Qualcomm Incorporated. Other product and brand names may be trademarks or registered trademarks of their respective owners. This technical data may be subject to U.S. and international export, re-export, or transfer ("export") laws. Diversion contrary to U.S. and international law is strictly prohibited. Qualcomm Technologies International, Ltd. (formerly known as Cambridge Silicon Radio Limited) is a company registered in England and Wales with a registered office at: Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom. Registered Number: VAT number: GB , 2015, 2016, 2017 Qualcomm Technologies International, Ltd. All rights reserved.

2 General description CSR1025 LGA is Qualcomm Technologies International, Ltd. (QTIL)'s latest generation Bluetooth low energy technology single-mode platform device with ultra low power consumption. CSR1025 LGA enables customer applications of up to 60 KB to be stored on chip for optimal power consumption. Qualcomm Bluetooth Low Energy technology enables ultra low-power connectivity and basic data transfer for applications previously limited by the power consumption, size constraints, and complexity of other wireless standards. The Qualcomm Bluetooth Low Energy platform provides everything required to create a Bluetooth low energy technology product with RF, baseband, MCU, qualified Bluetooth v4.2 specification stack, and customer application running on a single IC. Bluetooth low energy technology enables connectivity and data transfer to leading smartphone, tablet, and personal computing devices including ios, Android, Windows Phone 8, and Blackberry OS10 devices. Qualcomm Mesh places the smartphone at the center of the Internet of Things enabling an almost unlimited number of Bluetooth low energy technology enabled devices to be simply networked together and controlled directly from a single smartphone, tablet, or PC. CSR1025 LGA supports profiles for health and fitness sensors, watches, keyboards, mice, and advanced remote controls. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 2

3 Device details Ultra low-power Bluetooth low energy technology radio Single pin RF connection (50 Ω impedance in Tx and Rx modes) Requires no external RF components a Operates from a single crystal Bluetooth v4.2 specification compliant Bluetooth transmitter 4 dbm RF transmit power b Tx power control No external power amplifier or Tx/Rx switch required Bluetooth receiver dbm sensitivity -92 dbm Rx Boost mode available: Enhances Rx sensitivity at higher receive current cost -5 dbm maximum input level sensitivity Integrated channel filters Digital demodulator for improved sensitivity and cochannel rejection Fast AGC for enhanced dynamic range Bluetooth stack QTIL protocol stack runs on the integrated MCU: Support for Bluetooth v4.2 specification features: Master and slave operation Including encryption Software stack in firmware includes: GAP L2CAP Security manager Generic attribute protocol Attribute profile Bluetooth low energy technology profile support Synthesizer Fully integrated synthesizer requires no external VCO varactor diode, resonator, or loop filter Baseband and software Integrated MAC for all packet types enables packet handling without the need to involve the MCU Audio Digital microphone input I²S port for PCM I/O G.722 Codec Physical interfaces 32 digital flexible PIO 1 digital static PIO 2 analog AIO UART SPI interface Debug SPI interface for programming I²C controller 4 x quadrature decoders PWM 3D shutter control 5 x LED PWMs Keyboard scanner LCD glass drive 10 bit auxiliary ADC IR encoder Auxiliary features Battery monitor 6 power modes Power management features include software shutdown and hardware wake-up Wake-up power management from any PIO Integrated switch-mode power supply Linear regulator (internal use only) AES-128 Watchdog timer Memory 256 KB internal flash 64 KB (Code) and 16 KB (Data) RAM 192 KB ROM 60 KB OTP 256 Byte MTP Battery Battery input voltage 3.6 V to 1.4 V Temperature specification Operating temperature -30 to 85 ºC Package 60-lead 8 x 8 x 0.75 mm, 0.5 mm pitch LGA Single side routing pinout optimized a b Certain antennas with gain may require a simple filter. From Qualcomm Bluetooth Low Energy SDK onwards. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 3

4 CSR1025 LGA functional block diagram RF UART I/O LED PWMs Bluetooth Radio LDO SMPS VDD_BAT AIO PWM 3D Shutter PWM Driver Bluetooth low energy technology Modem and LC AUX / CLK / PSU Control Flexible PIO Mapping Keyboard Scanner Quadrature Decoders AES-CCM and AES Encryption LCD Segment Display Driver IR Encoder RAM Arbiter RAM 64 KB Code Clock Generation XTAL_IN I²S Audio DMA Digital Microphone RAM 16 KB Data G.722 Codec Code Data I²C / SPI Control State Machine MCU ROM Interrupt Timer Optional Cache OTP Internal Flash Debug Debug MTP xio CSR1025 LGA functional block diagram 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 4

5 Ordering information Device Package Type Size Shipment method Order number CSR1025 LGA LGA 60-lead (Pb free) 8 x 8 x 0.75 mm 0.5 mm pitch Tape and reel CSR1025A05 ILLQ R Minimum order quantity is 2 kpcs. Supply chain: QTIL's manufacturing policy is to multisource volume products. For further details, contact your local sales account manager or representative. QTIL contacts General information Information on this product Customer support for this product Details of compliance and standards Help with this document qcsales@qti.qualcomm.com createpoint.qti.qualcomm.com product.compliance@qti.qualcomm.com document.feedback@qti.qualcomm.com 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 5

6 Revision history Revision Date Change reason 1 October 2013 Initial release. Alternative document number CS DS. 2 August 2015 Updated information for Lead Customer Engineering Sample (LCES) release. 3 October 08, 2015 Updated information for Engineering Sample release. 4 October 09, 2015 Updated Peripheral Interfaces information. 5 March 2016 Updated to Pre-production Information. 6 May 10, 2016 Updated to Production Information. 7 May 13, 2016 Revised RF information. 8 May 19, 2016 Updated Corporate Branding. 9 June 2016 Updated Document References. 10 October 06, 2016 Addition of 4 dbm information. 11 October 12, 2016 Updated Current Consumption Description. AA July 2017 Updated Document Versioning, Legal Information, and Qualcomm Style. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 6

7 Status information QTIL Product Data Sheets progress according to the following formats: Advance Information, Engineering Sample, Pre-production Information, and Production Information. The status of this document is Production Information. Advance Information Information for designers concerning QTIL product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. Engineering Sample Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by QTIL without notice. Pre-production Information Pinout and mechanical dimension specifications finalized. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All electrical specifications may be changed by QTIL without notice. Production Information Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. Production Data Sheets supersede all previous document versions. Device implementation As the feature-set of the CSR1025 LGA is firmware build-specific, see the relevant software release note for the exact implementation of features on the CSR1025 LGA. Life support policy and use in safety-critical applications QTIL products are not authorized for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. QTIL will not warrant the use of its devices in such applications. QTIL environmental and RoHS compliance CSR1025 LGA devices meet the requirements of Directive 2011/65/EU of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). CSR1025 LGA devices are free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. For more information, see QTIL Environmental declaration statement for QTIL semiconductor products. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 7

8 Contents General description... 2 Device details... 3 CSR1025 LGA functional block diagram... 4 Ordering information... 5 QTIL contacts... 5 Revision history... 6 Status information... 7 Device implementation... 7 Life support policy and use in safety-critical applications... 7 QTIL environmental and RoHS compliance Package information CSR1025 LGA pinout diagram Device terminal functions Device terminal functions (Radio) Device terminal functions (Synthesizer and oscillator) Device terminal functions (PIO port) Device terminal functions (Test and debug) Device terminal functions (Power supplies and control) Device terminal functions (Unconnected terminals) Package dimensions PCB design and assembly considerations Typical solder reflow profile Bluetooth modem RF port RF receiver RSSI RF transmitter Power amplifier Bluetooth radio synthesizer Baseband Physical layer hardware engine Clock generation Clock architecture Crystal oscillator: XTAL_IN and XTAL_OUT CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 8

9 Contents Crystal specification Sleep clock Operating modes Active mode Radio-on mode Deep Sleep modes Deep Sleep: 16 KB Data RAM and 64 KB RAM Retention mode Deep Sleep: 16 KB Data RAM Retention mode Deep Sleep: No RAM Retention and External Interrupts and Timer Enabled (Hibernate) mode Deep Sleep: No RAM Retention and External Interrupts Enabled (Dormant) mode Microcontroller, memory, and baseband logic Microcontroller Memory RAM code and data (Internal) ROM (Internal) OTP (Internal) MTP (Internal) Flash (Internal) Peripheral interfaces I²C interface SPI interface SPI debug interface (QTIL proprietary) Instruction cycle Multislave operation UART (General) UART configuration settings UART configuration while in Deep Sleep PWMs D shutter control PWM LED control PWM LCD glass driver Key scanner Quadrature decoders Infrared output Audio Digital microphone G.722 codec bit auxiliary ADC CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 9

10 Contents 7 Auxiliary features Battery monitor Temperature sensor Programmable I/O ports, PIO, and AIO General PIO Static PIO AIO bit auxiliary ADC Digital pin states on initial power-up LCD glass mid-rail drive Analog properties of the PIO PIO configuration options CSR1025 LGA software stack Power control and regulation Switch-mode regulator Reset CSR1025 LGA example application schematic Electrical characteristics Absolute maximum ratings Recommended operating conditions Input/output terminal characteristics Switch-mode regulator RF linear regulator Digital I/O terminals AIO ESD protection Current consumption Environmental declaration statement for QTIL semiconductor products Tape and reel information Tape orientation Tape dimensions Reel information Moisture sensitivity level Document references Terms and definitions CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 10

11 Tables Table 1-1: CSR1025 LGA device terminal functions (Radio) Table 1-2: CSR1025 LGA device terminal functions (Synthesizer and oscillator)...14 Table 1-3: CSR1025 LGA device terminal functions (PIO port) Table 1-4: CSR1025 LGA device terminal functions (Test and debug) Table 1-5: CSR1025 LGA device terminal functions (Power supplies and control) Table 1-6: CSR1025 LGA device terminal functions (Unconnected terminals)...17 Table 1-7: CSR1025 LGA package dimensions table Table 3-1: Crystal specification...24 Table 6-1: Instruction cycle for an SPI transaction Table 6-2: UART signals Table 6-3: UART configuration settings Table 8-1: CSR1025 LGA 10 bit auxiliary ADC...41 Table 8-2: Pin states on initial power-up Table 8-3: CSR1025 LGA PIO configuration options Table 12-1: CSR1025 LGA absolute maximum ratings Table 12-2: CSR1025 LGA recommended operating conditions Table 12-3: CSR1025 LGA switch-mode regulator Table 12-4: CSR1025 LGA RF linear regulator...50 Table 12-5: CSR1025 LGA input voltage levels Table 12-6: CSR1025 LGA output voltage levels Table 12-7: CSR1025 LGA input and tri-state Table 12-8: CSR1025 LGA AIO Table 12-9: CSR1025 LGA ESD handling ratings...51 Table 13-1: Current consumption Table 14-1: Restricted substances present in QTIL products...53 Table 15-1: CSR1025 LGA tape dimensions Table 15-2: CSR1025 LGA reel dimensions CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 11

12 Figures CSR1025 LGA functional block diagram... 4 Figure 1-1: CSR1025 LGA pinout diagram Figure 1-2: CSR1025 LGA package dimensions diagram Figure 3-1: CSR1025 LGA clock architecture Figure 3-2: Crystal driver circuit Figure 5-1: Baseband digits block diagram Figure 6-1: Peripheral interfaces block diagram Figure 6-2: SPI timing diagram Figure 6-3: Example keyboard matrix 3 x 2 size Figure 6-4: CSR1025 LGA audio Figure 6-5: 10 bit auxiliary ADC reference Figure 9-1: Software architecture Figure 11-1: CSR1025 LGA example application schematic Figure 15-1: CSR1025 LGA tape orientation Figure 15-2: CSR1025 LGA tape dimensions Figure 15-3: CSR1025 LGA reel dimensions CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 12

13 1 Package information CSR1025 LGA is available in a 8 x 8 x 0.75 mm 60-lead LGA package. 1.1 CSR1025 LGA pinout diagram The CSR1025 LGA IC has 60 pins, numbered sequentially in an anticlockwise (counterclockwise) direction, starting from lead 1. Orientation from Top of Device qfv Figure 1-1 CSR1025 LGA pinout diagram 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 13

14 Package information 1.2 Device terminal functions The leads on the CSR1025 LGA are grouped into various terminal functions. The device terminal functions include: Radio Synthesizer and oscillator PIO port Test and debug Power supplies and control Unconnected terminals Device terminal functions (Radio) Table 1-1 CSR1025 LGA device terminal functions (Radio) Radio Lead Pad type Supply domain Description RF 7 RF VDD_RF Antenna port for Bluetooth transmitter / receiver Device terminal functions (Synthesizer and oscillator) Table 1-2 CSR1025 LGA device terminal functions (Synthesizer and oscillator) Synthesizer and oscillator Lead Pad type Supply domain Description XTAL_IN 10 Analog VDD_RF Reference clock input. XTAL_OUT 9 Analog VDD_RF Drive for clock crystal Device terminal functions (PIO port) Table 1-3 CSR1025 LGA device terminal functions (PIO port) PIO port Lead Pad type Supply domain Description PIO[32] 34 Digital: Bidirectional with programmable strength internal pull-up / pull-down PIO[31] 33 Digital: Bidirectional with programmable PIO[30] 38 Digital: Bidirectional with programmable PIO[29] 37 Digital: Bidirectional with programmable Static programmable I/O line 32. General programmable I/O line 31. General programmable I/O line 30. General programmable I/O line CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 14

15 Package information Table 1-3 CSR1025 LGA device terminal functions (PIO port) (cont.) PIO port Lead Pad type PIO[28] 36 Digital: Bidirectional with programmable PIO[27] 35 Digital: Bidirectional with programmable PIO[26] 59 Digital: Bidirectional with programmable PIO[25] 58 Digital: Bidirectional with programmable PIO[24] 57 Digital: Bidirectional with programmable PIO[23] 56 Digital: Bidirectional with programmable PIO[22] 55 Digital: Bidirectional with programmable PIO[21] 54 Digital: Bidirectional with programmable PIO[20] 53 Digital: Bidirectional with programmable PIO[19] 52 Digital: Bidirectional with programmable PIO[18] 50 Digital: Bidirectional with programmable PIO[17] 49 Digital: Bidirectional with programmable PIO[16] 32 Digital: Bidirectional with programmable PIO[15] 31 Digital: Bidirectional with programmable PIO[14] 30 Digital: Bidirectional with programmable PIO[13] 5 Digital: Bidirectional with programmable PIO[12] 4 Digital: Bidirectional with programmable Supply domain Description General programmable I/O line 28. General programmable I/O line 27. General programmable I/O line 26. General programmable I/O line 25. General programmable I/O line 24. General programmable I/O line 23. General programmable I/O line 22. General programmable I/O line 21. General programmable I/O line 20. General programmable I/O line 19. General programmable I/O line 18. General programmable I/O line 17. General programmable I/O line 16. General programmable I/O line 15. General programmable I/O line 14. General programmable I/O line 13. General programmable I/O line CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 15

16 Package information Table 1-3 CSR1025 LGA device terminal functions (PIO port) (cont.) PIO port Lead Pad type Supply domain Description PIO[11] 3 Digital: Bidirectional with programmable PIO[10] 2 Digital: Bidirectional with programmable PIO[9] 1 Digital: Bidirectional with programmable PIO[8] 60 Digital: Bidirectional with programmable PIO[7] 48 Digital: Bidirectional with programmable PIO[6] 47 Digital: Bidirectional with programmable PIO[5] 46 Digital: Bidirectional with programmable PIO[4] 45 Digital: Bidirectional with programmable PIO[3] 43 Digital: Bidirectional with programmable PIO[2] 42 Digital: Bidirectional with programmable PIO[1] 41 Digital: Bidirectional with programmable PIO[0] 40 Digital: Bidirectional with programmable General programmable I/O line 11. General programmable I/O line 10. General programmable I/O line 9. General programmable I/O line 8. General programmable I/O line 7. General programmable I/O line 6. General programmable I/O line 5. General programmable I/O line 4. General programmable I/O line 3. General programmable I/O line 2. General programmable I/O line 1. General programmable I/O line 0. AIO[1] 13 Unidirectional analog VDD_AUX Analog programmable input line. AIO[0] 14 Unidirectional analog VDD_AUX Analog programmable input line Device terminal functions (Test and debug) Table 1-4 CSR1025 LGA device terminal functions (Test and debug) Test and debug Lead Pad type Supply domain Description SPI_PIO# 39 Input with strong internal pull-down Logic high switches PIO[3:0] to Debug SPI operation, low to PIO mode. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 16

17 Package information Device terminal functions (Power supplies and control) Table 1-5 CSR1025 LGA device terminal functions (Power supplies and control) Power supplies and control Lead Description VDD_BAT 16 Positive supply from the battery. SMPS_LX1 17 Terminal 1 of the external 2.2 µh inductor connected to this pin. SMPS_LX2 18 Terminal 2 of the external 2.2 µh inductor connected to this pin. VDD_AUX 21 SMPS output for the auxiliary rail and AIO ports. VDD_DIG 22 SMPS output for the digital rail. VDD_MEM 23 SMPS output for the memory rail. VDD_RAD 19 SMPS output for the radio rail. VDD_RF_IN 20 SMPS output for the radio rail. VDD_RF 11 Decoupled supply for radio and XTAL pads. VSS_RF 8, 6 Ground connection for RF. 44, 28 Positive supply for digital I/O ports PIO[32:0] and SPI_PIO#. VSS 51, 29, 15 and the central pads 65, 64, 63, 62 and 61 Ground connections Device terminal functions (Unconnected terminals) Table 1-6 CSR1025 LGA device terminal functions (Unconnected terminals) Unconnected terminals Lead Description NC 27, 26, 25, 24, 12 Leave unconnected. Do not connect these pins doing so may have an adverse effect on the system. These pins must be left floating. Do not ground these pins (grounding these pins prevents the chip from functioning). 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 17

18 Package information 1.3 Package dimensions CSR1025 LGA is available in a 8 x 8 x 0.75 mm 60-lead LGA package. Package dimensions diagram A aaa C Top View E B A A3 A2 Pin1 Corner D aaa C 15 Bottom View E3 E2 30 See Note 1 bbb C C Seating Plane Side View SD D2 D3 D A1 Mark e L 60 e 45 SE b E1 ymt Figure 1-2 CSR1025 LGA package dimensions diagram 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 18

19 Package information Package dimensions table Table 1-7 CSR1025 LGA package dimensions table Dimension Min Typ Max Dimension Min Typ Max A E2-1 - A E A e b e D and E L D SD D2-1 - SE D bbb E Notes 1. Parallelism measurement excludes any effect of marks on the top surface of the package. 2. Dimensioning and tolerances conform to ASME Y14.5M Pin #1 identifier is placed on the top surface of the package. Exact shape and size of this feature is optional. Description 60-lead Land Grid Array Package Size 8 x 8 x 0.75 mm JEDEC N/A Pitch 0.5 Units mm 1.4 PCB design and assembly considerations This section lists recommendations to achieve maximum board-level reliability of the 8 x 8 x 0.75 mm LGA 60-lead package: NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation. QTIL recommends that the PCB land pattern is in accordance with IPC standard IPC Solder paste must be used during the assembly process. 1.5 Typical solder reflow profile For information, see Typical Solder Reflow Profile for Lead-free Devices Information Note. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 19

20 2 Bluetooth modem CSR1025 LGA's modem supports Bluetooth low energy technology and has four link controller blocks supporting up to four connections. 2.1 RF port CSR1025 LGA contains a single-ended 50 Ω RF Tx / Rx port pin. No external matching to 50 Ω is required. The antenna must be connected when CSR1025 LGA is powered up. Significant changes in VSWR after the chip has performed start of day calibrations might result in Tx modulation errors and reduced Rx sensitivity. 2.2 RF receiver The receiver features a near-zero IF architecture enabling the channel filters to be integrated onto the die. Sufficient out-of-band blocking provided on die at the LNA input enables the receiver to be used close to cellular phone transmitters without being significantly desensitized: Receive sensitivity is typically dbm Software selectable Boost mode can be enabled for extra sensitivity An AGC supports the device to meet Bluetooth v4.2 specification Receiver large input level saturation is typically -5 dbm CSR1025 LGA does not support control for an external LNA. The additional front-end gain from an LNA would compromise the Bluetooth maximum input signal level test RCV-LE/CA/BV-06-C RSSI Front-end LNA gain is changed according to measured RSSI, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference-limited environments. The level is reported to the firmware using an API with accuracy of ±6 dbm, and resolution of 1 dbm. This value is only available to an application after reception of a valid packet. 2.3 RF transmitter Power amplifier The internal PA can deliver a maximum of 4 dbm at the RF pin into a 50 Ω load. Configurable software enables delivery of lower output powers to reduce current consumption during transmit. For more information, see CSR102x A05 Limitations. 2.4 Bluetooth radio synthesizer The Bluetooth radio synthesizer is fully integrated onto the die with no requirement for external components and meets all lock-time requirements of the Bluetooth v4.2 specification. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 20

21 Bluetooth modem 2.5 Baseband Physical layer hardware engine Dedicated logic performs: Cyclic redundancy check Encryption Data whitening Access code correlation 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 21

22 3 Clock generation 3.1 Clock architecture Figure 3-1 shows CSR1025 LGA's three clocks: Fast Clock: Bluetooth system reference clock required for Tx and Rx Supplied by an external 16 MHz crystal Intermediate Clock: Internal clock source that can operate at various intermediate frequencies (62.5 khz to 8 MHz in approximate log spacing) Slow Clock: Suitable for peripherals that require a moderate clock frequency of low accuracy Lower power than Fast Clock and can work in Deep Sleep Internal clock source Lowest power and works in Deep Sleep A digital state machine uses temperature sampling to ensure clock drift for sleep timing stays within 500 ppm Internally generated, running at approximately 32 khz, without trim, only calibration 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 22

23 Clock generation Fast XTAL Clock for System PMU Controller Auxiliary ADC Bluetooth low energy technology Radio Intermediate Clock Microcontrollers PWM, I²C, and others Slow Clock for Sleep Memory fnj Figure 3-1 CSR1025 LGA clock architecture 3.2 Crystal oscillator: XTAL_IN and XTAL_OUT CSR1025 LGA has a crystal driver circuit. This operates with an external crystal to form a Pierce oscillator. Figure 3-2 shows how the external crystal is connected to pins XTAL_IN and XTAL_OUT. The crystal oscillator requires no external capacitors. - XTAL_IN XTAL_OUT spb Figure 3-2 Crystal driver circuit The PCB design must ensure that the total trace capacitance on XTAL_IN and XTAL_OUT are less than 2 pf each. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 23

24 Clock generation Crystal specification Table 3-1 lists the specification required for a CSR1025 LGA external crystal. Crystals with the specification in Table 3-1 are produced by a limited number of manufacturers. QTIL recommends only using crystals listed in CSR102x Recommended Crystals Specification. Table 3-1 Crystal specification Parameter Description Min Typ Max Unit F nom Nominal fundamental frequency MHz T stg Storage temperature C T op_industrial Operating temperature range C C P Package capacitance (16 MHz) pf C L Load capacitance pf F_tol_nom Frequency tolerance nominal at room temperature ppm F_tol_temp_ind Frequency stability over temperature (industrial) ppm F_tol_aging Frequency tolerance aging 1st 25 C -3-3 ppm/yr Sensitivity Frequency variation vs. load capacitance 25 C ppm/pf ESR Motional resistance (16 MHz) Ω 3.3 Sleep clock CSR1025 LGA uses the internal slow clock or crystal in low-power mode, eliminating the need for an externally supplied sleep clock. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 24

25 4 Operating modes CSR1025 LGA has six operating modes. Four are Deep Sleep modes: Active mode Radio-on mode Deep Sleep modes: Deep Sleep: 16 KB Data RAM and 64 KB RAM Retention mode Deep Sleep: 16 KB Data RAM Retention mode Deep Sleep: No RAM Retention and External Interrupts and Timer Enabled (Hibernate) mode Deep Sleep: No RAM Retention and External Interrupts Enabled (Dormant) mode 4.1 Active mode In Active mode, the processor runs: Code and/or performs activities with peripherals. With at least one link controller powered. 4.2 Radio-on mode In Radio-on mode, the Bluetooth radio is turned on. Radio-on mode can only be entered from Active mode. 4.3 Deep Sleep modes CSR1025 LGA has four Deep Sleep modes Deep Sleep: 16 KB Data RAM and 64 KB RAM Retention mode In Deep Sleep: 16 KB Data RAM and 64 KB RAM Retention mode: Normal operation uses only the slow clock or intermediate clock (running at a slow speed). CSR1025 LGA supports activity in peripherals to perform a particular operation (for example PWMs, keyboard scanner) or wake the chip on activity (for example UART, application SPI). Link controller state is maintained: This can be active (advertising, scanning or in a connection) and CSR1025 LGA can deep sleep between periods on or around radio activity. A PIO deep sleep timer time-out or optional temperature change or low battery can wake the chip by generating an interrupt. It is possible to keep the processor powered and its power-controlled using power gating. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 25

26 Operating modes Deep Sleep: 16 KB Data RAM Retention mode In Deep Sleep: 16 KB Data RAM Retention mode: Normal operation uses only the slow clock or intermediate clock (running at a slow speed). CSR1025 LGA supports activity in peripherals to perform a particular operation (for example PWMs, keyboard scanner) or wake the chip on activity (for example UART, application SPI). Link controller state is maintained: This can be active (advertising, scanning or in a connection) and CSR1025 LGA can deep sleep between periods on or around radio activity. A PIO deep sleep timer time-out or optional temperature change or low battery can wake the chip by generating an interrupt. It is possible to keep the processor powered and its power-controlled using power gating Deep Sleep: No RAM Retention and External Interrupts and Timer Enabled (Hibernate) mode In Deep Sleep: No RAM Retention and External Interrupts and Timer Enabled (Hibernate) mode: VDD_BAT must always be present. A PIO can wake the chip (programmable as in Deep Sleep: No RAM Retention and External Interrupts Enabled (Dormant) mode). The following can wake the chip: PIO hibernate timer time-out. Temperature change. Low battery Deep Sleep: No RAM Retention and External Interrupts Enabled (Dormant) mode In Deep Sleep: No RAM Retention and External Interrupts Enabled (Dormant) mode: An attached battery can be used as a wake-up. No timers run, therefore CSR1025 LGA can only be woken by a PIO or a rise on VDD_BAT. VDD_BAT can be removed if remains powered, because the pull states of pads are preserved. Ignore a rise on VDD_BAT until a PIO has latched an event (enabling two different Deep Sleep: No RAM Retention and External Interrupts Enabled submodes). The PIOs that CSR1025 LGA is sensitive to on wake-up are programmable; that is, it is possible to ignore events on some PIOs but not others. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 26

27 5 Microcontroller, memory, and baseband logic RAM Arbiter RAM 64 KB Code RAM 16 KB Data Code Data MCU Interrupt Timer Optional Cache ROM OTP Internal Flash Debug MTP enc Figure 5-1 Baseband digits block diagram 5.1 Microcontroller The MCU, interrupt controller, and event timer run the Bluetooth software stack and control the Bluetooth radio and external interfaces. A 16 bit RISC microcontroller is used for low power consumption and efficient use of memory. 5.2 Memory CSR1025 LGA memory includes: RAM code and data (Internal) ROM (Internal) OTP (Internal) MTP (Internal) Flash (Internal) 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 27

28 Microcontroller, memory, and baseband logic Memory spaces include: Application Store: A storage area for customer applications, located in OTP or SPI flash. Configuration Store: An area of memory used to store configuration settings (ROM, OTP, MTP, RAM, SPI flash). User Store: OTP (programmable once then read-only), MTP (multiple-time programmable), and SPI flash data storage available to user applications at runtime RAM code and data (Internal) CSR1025 LGA has RAM for code and data. Either RAM is available for code or data. Code RAM 64 KB: For code or data Primary use for developing applications for eventual storage in OTP memory Useable as a cache for applications stored in flash or OTP memory Useable as code or data RAM if not used as a code cache Software provides details of the area of shared RAM to the user application Part or all of the code RAM is powered down to save power when not in use Data RAM 16 KB: For code or data Primary use for firmware and applications The use of all data RAM for executing code is possible (although there are some restrictions on when this can be done) ROM (Internal) 192 KB of internal ROM is available for system firmware implementation. Code executes from ROM and RAM OTP (Internal) 60 KB of OTP is available for storage of user applications: One-time programmable Enables reading and writing of information to the configuration store Enables downloading of software Has a storage provider driver PMU supplies power Useable space to store a boot loader or fall-back image for deploying updateable applications in Flash MTP (Internal) 256 Bytes of MTP is an internal NVM where applications can store configuration data; for example, Bluetooth addresses and Link Keys: 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 28

29 Microcontroller, memory, and baseband logic 10,000 erase/write cycles Multiple-time programmable Flash (Internal) 256 KB of flash (internal) memory is available for user applications: More than 100,000 erase/write cycles Internal flash is accessed at a speed lower than the processor can run: This means that application code executing from flash executes slower than that in OTP (or RAM). To mitigate this use code RAM as a cache. For information about flash configuration, see CSR102x Initial Configuration for Devices (part of Qualcomm Bluetooth Low Energy SDK). Encrypted applications have a maximum size of 64 KB. This is because the image is copied to the code RAM and decrypted in place using the decryption key stored in OTP. For more information, see the SDK software release note. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 29

30 6 Peripheral interfaces I/O UART LED PWMs AIO PWM 3D Shutter PWM Driver Flexible PIO Mapping Keyboard Scanner Quadrature Decoders LCD Segment Display Driver IR Encoder I²S Audio DMA Digital Microphone G.722 Codec I²C / SPI Control State Machine MCU Interrupt Timer Debug Debug boz Figure 6-1 Peripheral interfaces block diagram 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 30

31 Peripheral interfaces 6.1 I²C interface CSR1025 LGA has 1 I²C interface for communication with external peripherals and sensors: Maximum clock speed 1 MHz Data transmiting/receiving of variable byte length 7 bit and 10 bit addressing modes Configurable: PIO pins for SCL and SDA I²C clock: 100 khz default (software-configurable) at 1:1 duty-cycle (asymmetric if necessary) Supports slave clock stretching CSR1025 LGA is Fast Mode and Fast Mode+ compatible. Strong pull-up is typically sufficient for I²C on all PIO pads. 6.2 SPI interface CSR1025 LGA has one SPI interface for communication with other devices. CSR1025 LGA supports: SPI master and slave All four modes supported Two methods of transferring data to memory: DMA to/from memory: 8 bit or 16 bit word size Big and little-endian Software reads and writes to FIFOs: variable from 1 bit to 16 bits Interrupt callbacks to processor enable SPI as a slave to indicate that it requires service Deep sleep mode (depending on clock) Figure 6-2 shows a simple SPI timing diagram. CS# CLK MISO MOSI MSB MSB LSB LSB fpt Figure 6-2 SPI timing diagram 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 31

32 Peripheral interfaces 6.3 SPI debug interface (QTIL proprietary) The CSR1025 LGA debug SPI interface is available in SPI slave mode to enable an external MCU to program and control the CSR1025 LGA, via libraries or tools supplied by QTIL. The protocol of this interface is proprietary. A 128 bit lock key is applicable to secure the application code. The four SPI debug lines directly support this function on PIO[3:0]. Debug SPI access is required for programming, configuring and debugging the CSR1025 LGA. It is required in production. Ensure the four SPI signals and SPI_PIO# are brought out to either test points or a header with SPI_PIO#. To enable the SPI debug feature on PIO[3:0], take SPI_PIO# high. CSR1025 LGA uses a 16 bit data and 16 bit address programming and debug interface. Transactions occur when the internal processor is running or is stopped. Data is written or read one word at a time, or the auto-increment feature is available for block access Instruction cycle The CSR1025 LGA is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table 6-1 lists the instruction cycle for an SPI transaction. Table 6-1 Instruction cycle for an SPI transaction Number Transaction Instruction 1 Reset the SPI interface Hold SPI_CS# high for 2 SPI_CLK cycles 2 Write the command word Take SPI_CS# low and clock in the 8 bit command 3 Write the address Clock in the 16 bit address word 4 Write or read data words Clock in or out 16 bit data word/s 5 Termination Take SPI_CS# high Except for reset, hold SPI_CS# low during the transaction. Data on SPI_MOSI is clocked into the CSR1025 LGA rising edge of the clock line SPI_CLK. When reading, CSR1025 LGA replies to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CS# high. The auto increment operation on the CSR1025 LGA cuts down on the overhead of sending a command word and the address of a register for each read or write. This is especially true when large amounts of data are to be transferred. The auto increment offers increased data transfer efficiency on the CSR1025 LGA. To invoke auto increment, SPI_CS# is kept low, which auto increments the address while providing an extra 16 clock cycles for each extra word written or read Multislave operation Do not connect the CSR1025 LGA in a multislave arrangement by simple parallel connection of slave MISO lines. When CSR1025 LGA is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead, CSR1025 LGA outputs 0 if the processor is running or 1 if it is stopped. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 32

33 Peripheral interfaces 6.4 UART (General) The CSR1025 LGA UART interface provides a simple mechanism to communicate with other serial devices using the RS232 protocol. Table 6-2 lists the four signals that implement the UART function in CSR1025 LGA. Hardware flow control using RTS/CTS lines is optional. Table 6-2 Signal UART signals Description UART_RX UART_TX UART_CTS UART_RTS Pin to receive UART data from another device Pin to transmit UART data to another device Pin for another device to indicate it is ready to receive data (active low input) Pin for another device to indicate that this other device is ready to receive data (active low input) UART configuration settings UART configuration parameters, for example baud rate and data format, are set using CSR1025 LGA firmware. Table 6-3 lists UART configuration settings for CSR1025 LGA. Table 6-3 UART configuration settings Parameter Possible values Baud rate Minimum 1200 baud ( 2 % Error) 9600 baud ( 1 % Error) Maximum (XTAL) a 1 Mbaud ( 1 % Error) Parity None, Odd or Even Number of stop bits 1 or 2 Bits per byte 8 a Refer to the applicable firmware documentation for details UART configuration while in Deep Sleep The maximum baud rate is 2400 baud during deep sleep. 6.5 PWMs CSR1025 LGA has five independently configurable PWM instances. A multipurpose PWM generator provides three modes: Normal PWM mode: For motor control and general-purpose PWM 3D Shutter mode: 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 33

34 Peripheral interfaces For 3D shutter control Cycle accurate 16 bit resolution for all the configuration registers to be specified in clock cycles New configuration applied on update register write or at a specific time (for example in response to radio traffic) Variable offset applicable after the reconfiguration Configurable width of the external sync pulses LED mode: For LED fading D shutter control PWM CSR1025 LGA has a 3D shutter control PWM that is cycle accurate and useable for driving 3D TV glasses. It has 16 bit resolution for all configuration registers to be specified in the clock cycles: Time On: For shutter on period Time Period: For shutter period Time Offset: Applied at a specific time (for example in response to radio traffic) A new configuration is applied on the TV sync pulse or controlled on the sync register write LED control PWM CSR1025 LGA has four LED mode PWM blocks (2 x fast / 2 x slow). Each LED mode PWM has an 8 bit resolution for all configuration registers and a: Minimum brightness duty cycle (grouped in a 16 bit wide register) Maximum brightness duty cycle (grouped in a 6 bit wide register) Hold Minimum and Maximum time (grouped in a 16 bit wide register) Step (ramp) time Brightness configuration specified in units of typically 30 μs assuming a 32 khz clock Hold times specified in units of typically 16 ms assuming a 32 khz clock Step time specified in units of typically 1 ms assuming a 32 khz clock CSR1025 LGA supports immediate reconfiguration on the sync register write. 6.6 LCD glass driver CSR1025 LGA's LCD driver has the following features: Drives simple static and multiplexed LCD glass with no requirement for external components Capable of controlling PIO pads to support bias modes: Normal: Switching between GND and VCC 1/2 bias: Switching between GND, 1/2 VCC and VCC 1/3 bias: Switching between GND, 1/3 VCC, 2/3 VCC and VCC Up to 28 segments and 4 common (backplane) driver outputs 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 34

35 Peripheral interfaces Configurable to support nonmultiplexed (static) and two, three, or four way multiplexed LCD glass Supports LCD glass with up to 112 display segments (4x the number of segment driver outputs) Unused segment outputs can be disabled. LCD blanking support: Enables flashing of all segments at slow (typically 2 Hz) frequency LCD segment blinking support: Up to two segments configurable to blink at slow frequency (typically 2 Hz) Flexible input clock prescaler to support required clock frequencies for different multiplexing modes and LCD glass characteristics Ultralow power operation to maintain LCD display with only low frequency clock LCD clock output for pad drivers to increase output pad drivers when LCD output changes Contrast control 6.7 Key scanner CSR1025 LGA has one key scanner for applications such as mouse and keyboard HID. Figure 6-3 shows an example keyboard matrix at a size of 3 x 2 (PIO drive lines x PIO sense lines respectively). Sense Lines PIO[IN 1] PIO[IN 0] PIO[OUT 0] B A Drive Lines PIO[OUT 1] PIO[OUT 2] D F C E tuv Figure 6-3 Example keyboard matrix 3 x 2 size Physical buttons are on line crossings A to F. If a button is pressed both lines become connected. Assuming sense lines are pulled-up by internal logic, a keypress, for example C is detectable by forcing PIO[OUT 1] low and reading 0 on PIO[IN 0]. It supports: Keypad matrix up to 12 PIO inputs (sense lines) and 18 PIO outputs (drive lines): Drives 1 to 18 drive lines consecutively 12 bit key registers updated every scan Press and release events reported to the host via callback Variable scan rate: By default drives consecutive drive lines every clock cycle Configurable number of clocks per drive line The key scanner does not support ghost key removal. The key scanner configuration and control includes: 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 35

36 Peripheral interfaces PIO pin numbers to be used for drive and sense lines Scan rate, Hz, and active/idle ratio Hardware starting and stopping Callback creation to receive keyboard map data. 6.8 Quadrature decoders CSR1025 LGA has four quadrature decoders with: Each having a configurable simple filter on inputs (for debouncing) Enabling and disabling of single or multiple decoders Data reading functionality Processor interrupt generation 6.9 Infrared output CSR1025 LGA has one infrared output for applications such as infrared remote control. It can run from Fast XTAL and Intermediate clocks Audio Figure 6-4 shows CSR1025 LGA audio. The clock for the Audio module is derived as an integer divided crystal source. Accuracy and drift track the underlying crystal specification. Digital Microphone (Mono) ADC 2 x 8-bit Samples 4 x 4-bit Samples 16-bit Input Sample or PIOs MUX 16-bit Sample Compander A-law / µ-law G.722 Codec Memory Interface To/From Memory Subsystem 16-bit Input Sample 2 x 8-bit Samples 4 x 4-bit Samples I²S Interface PCM 16-bit Output Sample jlr Figure 6-4 CSR1025 LGA audio Digital microphone and I²S input cannot be active at the same time. G.722 codec cannot encode and decode at the same time. 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 36

37 Peripheral interfaces Digital microphone CSR1025 LGA has one digital microphone input with: 1 Mbps or 2 Mbps sample rate Software selectable as left or right channel G.722 encoder or bypass option Audio routed to firmware only (not to I²S) Software supporting DMIC clock frequencies of 500 khz, 1 MHz, 2 MHz, and 4 MHz G.722 codec CSR1025 LGA has a G.722 codec, featuring: Output: 48 kbps (optional 56 kbps or 64 kbps) Input: 16 khz/16-bits (optional 8 khz/8-bits, 8 khz/16-bits, and 16 khz/8-bits) Output produces 20 Byte blocks for easy GATT streaming Analog audio is not provided bit auxiliary ADC CSR1025 LGA has a single 10 bit auxiliary ADC: A resistive SAR ADC Attached to two AIO pads The processor has access to its ADC result value after exit from Deep Sleep mode The ADC reference is VDD_AUX, see Figure 6-5. CSR102x VDD_AUX R1 AIO[0] V ref = 650mV R2 AIO[1] ADC 10 bits svq Figure bit auxiliary ADC reference 80-CE982-1 Rev. AA MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION 37