NT7532 V X132 RAM-Map LCD Controller/Driver. Preliminary

Transcription

1 65X132 RAM-Map LCD Controller/Driver V 0.1 Preliminary 1

2 1 REVISION HISTORY FEATURES GENERAL DESCRIPTION PADS CONFIGURATION BLOCK DIAGRAM PAD DESCRIPTIONS FUNCTIONAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS DC ELECTRICAL CHARA CTERISTICS AC CHARACTERISTICS BONDING DIAGRAM PACKAGE INFORMATION ORDERING INFORMATION V0. 1

3 Version History Version Content Date 0. 1 Original Jan

4 Features Direct RAM data display using the display RAM. When RAM data bit is 0, it is not displayed. When RAM data bit is 1, it is displayed. (At normal display) RAM capacity : 65 X 132 = 8580 bits Many command functions : Read/Write Display Data. Display ON/OFF. Normal/Reverse Display. Page Address Set. Set Display Start Line. Set LCD Bias. Electronic contrast Controls. V0 voltage regulation internal resistor ratio set. Read Modify Write. Select Segment Driver Direction. Power Save. High speed 8-bit microprocessor interface allowing direct connection to both the 8080 and 6800 Serial interface Maximum 12V LCD driving output voltage 2X / 3X / 4X on chip DC-DC converter Voltage regulator Voltage follower On-chip oscillator General Description The NT7502 is a single-chip LCD driver for dot-matrix liquid crystal displays, which is directly connectable to a microcomputer bus. It accepts 8-bit serial or parallel display data directly sent from a microcomputer and stores it in an on-chip display RAM. It generates a LCD drive signal independent of the microprocessor clock. The set of the on-chip display RAM of 65 X 132 bits and a one-to-one correspondence between LCD panel pixel dots and on-chip RAM bits permits implementation of displays with a high degree of freedom. The NT7502 contain 65 common output circuits and 132 segment output circuits, so that a single chip of NT7502 can make 65 X 132, 55 X 132, 49 X 132 and 33 X 132 dot displays with pad option (DUTY1, DUTY0). No external operation clock is required for RAM read/write operations. Accordingly, this driver can be operated with a minimum current consumption and its on-board low-current-consumption liquid crystal power supply can implement a high-performance handy display system with minimum current consumption and the smallest LSI configuration. 4 Ver. 0.1

5 Pad Configuration 5 Ver.0.1

6 Block Diagram VDD SEG0 SEG131 COM0 COM63 COMS V0 V1 V2 V3 V4 Vss Segment driver Common driver COM S TMPS Shift register CAP1+ CAP1- CAP2+ CAP2- CAP3+ VEXT VOUT Power Supply Circuit Display data latch VDD2 VR VRS IRS HPM Output status selector circuit I/O buffer circuit 132*65-dot display data RAM line address decoder Line counter Initial display line register Column address decoder Page address register 8-bit column address counter DUTY0 DUTY1 8-bit column address counter Display timing generator circuit FRS FR CL DOF M/S Bus holder Command decoder Bus holder Oscillator CLS Microprocessor interface I/O buffer CS1 CS2 A0 RD (E) WR C86 P/S RES (R / W) D7 (SI) D6 (SCL) D5 D4 D3 D2 D1 D0 6 Ver.0.1

7 Pad Descriptions Power Supply Pad No. Symbol I/O Descriptions VDD Supply 13,27,56,102,122,128, V power supply input. These pads must be connected each other VDD Supply V power supply output for pad option VDD2 Supply This is the reference power supply for the step-up voltage circuit for the LCD. These pads must be connected each other VSS Supply Ground. These pads must be connected each other VSS2 Supply Ground. These pads must be connected each other 6,20,58,99,1 20, 121,125,130, VSS Supply Ground output for pad option V0 V1 V2 V3 V4 Supply LCD driver supplies voltages. The voltage determined by LCD cell is impedance-converted by a resistive driver or an operation amplifier for application. Voltages should be according to the following relationship: V0 V1 V2 V3 V4 VSS When the on-chip operating power circuit is on, the following voltages are supplied to V1 to V4 by the on-chip power circuit. Voltage selection is performed by the Set LCD Bias command. LCD bias V1 V2 V3 V4 1/5 bias 4/5V0 3/5V0 2/5V0 1/5V0 1/6 bias 5/6V0 4/6V0 2/6V0 1/6V0 1/7 bias 6/7V0 5/7V0 2/7V0 1/7V0 1/8 bias 7/8V0 6/8V0 2/8V0 1/8V0 1/9 bias 8/9V0 7/9V0 2/9V0 1/9V0 7 Ver.0.1

8 LCD Driver Supplies Pad No. Symbol I/O Descriptions CAP1- O Capacitor 1- pad for internal DC/DC voltage converter CAP1+ O Capacitor 1+ pad for internal DC/DC voltage converter CAP2- O Capacitor 2- pad for internal DC/DC voltage converter CAP2+ O Capacitor 2+ pad for internal DC/DC voltage converter CAP3+ O Capacitor 3+ pad for internal DC/DC voltage converter VOUT O DC/DC voltage converter output VR I 100 VEXT I 133 TMPS I 101 VRS I Voltage adjustment pad. Applies voltage between V0 and VSS using a resistive divider This is the external input reference voltage (VREF) for the internal voltage regulator. It is valid only when external VREF is used. VEXT must be 2.4V and VDD2 When using internal VREF, this pad must be NC Selects temperature coefficient of the reference voltage TMPS = 0: -0.05% / C TMPS = 1: -0.2 % / C Select the internal voltage regulator or external voltage regulator, VRS = 0: using the external VREF VRS = 1: using the internal VREF 8 Ver.0.1

9 System Bus Connection Pads Pad No. Symbol I/O Descriptions D0 D1 D2 D3 D4 D5 D6(SCL) D7(SI) I/O A0 I RES I CS 1 CS2 RD (E) WR ( W R / ) 126 C86 I I I I This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus When the serial interface is selected (P/S = L ), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL) At this time, D0 to D5 are set to high impedance When the chip select is inactive, D0 to D7 are set to high impedance This is connected to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command A0 = H : Indicate that D0 to D7 are display data A0 = L : Indicates that D0 to D7 are control data When RES is set to L, the settings are initialized The reset operation is performed by the RES signal level This is the chip select signal. When CS 1 = L and CS2 = H, then the chip select becomes active, and data/command I/O is enabled When connected to an 8080 MPU, it is active LOW This pad is connected to the RD signal of the 8080MPU, and the NT7502 data bus is in an output status when this signal is L When connected to a 6800 Series MPU, this is active HIGH This is used as an enable clock input of the 6800 series MPU When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R / W = H : Read When R / W = L : Write This is the MPU interface switch terminal C86 = H : 6800 Series MPU interface C86 = L : 8080 MPU interface 9 Ver.0.1

10 127 P/S I 124 CLS I 123 M/S I 4 CL I/O 3 FR I/O 5 DOF I/O 2 FRS O This is the parallel data input/serial data input switch terminal P/S = H : Parallel data input P/S = L : Serial data input The following applies depending on the P/S status: P/S Data/Command Data Read/Write Serial Clock "H" A0 D0 to D7 RDWR "L" A0 SI (D7) Write only SCL (D6) When P/S = L, D0 to D5 are HZ. D0 to D5 may be H, L or Open. RD(E) and WR ( R / W ) are fixed to either H or L. With serial data input, RAM display data reading is not supported. Terminal to select whether enable or disable the display clock internal oscillator circuit CLS = H : Internal oscillator circuit is enabled CLS = L : Internal oscillator circuit is disabled (requires external input) When CLS = L, input the display clock through the CL pad This terminal selects the master/slave operation for the NT7502 chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system This is the display clock input terminal When the NT7502 chips are used in master/slave mode, the various CL terminals must be connected This is the liquid crystal alternating current signal I/O terminal M/S = H : Output M/S = L : Input When the NT7502 chip is used in master/slave mode, the various FR terminals must be connected This is the liquid crystal display blanking control terminal M/S = H : Output M/S = L : Input When the NT7502 chip is used in master/slave mode, the various DOF terminals must be connected This is the output terminal for the static drive This terminal is only enabled when the static indicator display is ON in master operation mode, and is used in conjunction with the FR terminal 10 Ver. 0.1

11 131 IRS I 129 HPM I This terminal selects the resistors for the V0 voltage level adjustment IRS = H, Use the internal resistors IRS = L, Do not use the internal resistors The V0 voltage level is regulated by an external resistive voltage divider attached to the VR terminal This pad is enabled only when the master operation mode is selected It is fixed to either H or L when the slave operation mode is selected This is the power control terminal for the power supply circuit for liquid crystal drive HPM = H, Normal mode HPM = L, High power mode This pad is enabled only when the master operation mode is selected It is fixed to either H or L when the slave operation mode is selected Liquid Crystal Drive Pads Pad No. Symbol I/O Description SEG0-131 O Segment signal output for LCD display COM31-0 COM32-63 O 167, 332 COMS O Common signal output for LCD display When in master/slave mode, the same signal is output by both master and slave These are the COM output terminals for the indicator. Both terminals output the same signal No connect these terminals if they are not used When in master/slave mode, the same signal is output by both master and slave Configuration Pads Pad No. Symbol I/O Description 57, 59 DUTY0, DUTY1 I Select the LCD driver duty DUTY1 DUTY0 LCD driver duty 0 0 1/ / / /65 11 Ver. 0.1

12 Test Pads Pad No. Symbol I/O Description 28 TEST0 I Test pads, and must be connected to VDD 1,31,34,37,4 0,43,,46,49, 52 55, NC NC pads, no connection for user 12 Ver. 0.1

13 Functional Description Microprocessor Interface Interface type selection The NT7532 can transfer data via 8-bit bi-directional data bus (D7 to D0) or via serial data input (SI). When high or low is selected for the parity of P/S pad either 8-bit parallel data input or serial data input can be selected as shown in Table 1. When serial data input is selected, the RAM data cannot be read out. Table. 1 P/S Type CS 1 CS2 A0 RD WR C86 D7 D6 D0 to D5 H Parallel Input CS 1 CS2 A0 RD WR C86 D7 D6 D0 to D5 L Serial Input CS 1 CS2 A SI SCL (HZ) Parallel Input - Must always be high or low When the NT7532 selects parallel input (P/S = high), the 8080 series microprocessor or 6800 series microprocessor can be selected by causing the C86 pad to go high or low as shown in Table 2. Table. 2 C86 Type CS 1 CS2 A0 RD WR D0 to D7 H L 6800 microprocessor bus 8080 microprocessor bus CS 1 CS2 A0 E R / W D0 to D7 CS 1 CS2 A0 RD WR D0 to D7 Data Bus Signals The NT7532 identifies the data bus signal according to A0, E, Table. 3 R/ W ( RD, WR ) signals. Common 6800 processor 8080 processor A0 ( R/ W ) RD WR Reads display data Writes display data Reads status Function Writes control data in internal register. (Command) Serial Interface (P/S is low) When the serial interface has been selected (P/S = L ), then when the chip is in active state ( 1 CS = L and CS2 = H ), the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits of parallel data in the rising edge of eighth serial clock 13 Ver. 0.1

14 for processing. The A0 input is used to determine whether or the serial data input is display data, and when A0 = L then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is the serial interface signal chart. CS1 CS2 SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 SCL A0 Figure. 1 When the chip is not active, the shift registers and the counter are reset to their initial states. Reading is not possible while in serial interface mode. Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend the operation be rechecked on the actual equipment. Chip Select Inputs The NT7532 has two chips select pads. CS 1 and CS2 can interface to a microprocessor whencs 1 is low and CS2 is high. When these pads are set to any other combination. D0 to D7 are high impedance and A0, E and R / W inputs are disabled. When serial input interface is selected. the shift register and counter are reset. Access to Display Data RAM and Internal Registers The NT7532 can perform a series of pipeline processing between LSI s using the bus holder of the internal data bus in order to match the operating frequency of display RAM and internal registers with the microprocessor. For example, the microprocessor reads data from display RAM in the first read (dummy) cycle, stores it in the bus holder, and outputs it onto system bus in the next data read cycle. Also, the microprocessor temporarily stores display data in the bus holder, and stores it in display RAM until the next data write cycle starts. When viewed from the microprocessor, the NT7532 access speed greatly depends on the cycle time rather than access time to the display RAM (t ACC). This view shows the data transfer speed to / from the microprocessor can increase. If the cycle time is inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the immediately following read instruction. The address data is output during the second data read. A single dummy read must be inserted after address setup and after the write cycle (refer to Figure2). 14 Ver. 0.1

15 A0 MPU E R/W DATA N N n n+1 Address preset Internal timing Read signal Column address Preset Incremented N N+1 N+2 BUS holder N n n+1 n+2 Set address n Dummy read Data Read address n Data Read address n+1 Busy Flag Figure. 2 When the busy flag is 1 it indicates that the NT7532 chip is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pad with the read instruction. If the cycle time (tcyc) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. Display Data RAM Display Data RAM The display data RAM is RAM that stores the dot data for the display. It has a 65(8 page * 8 bit+1)*132 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display common direction, and there are few constraints at the time of display data transfer when multiple NT7532 chips are used, thus display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). 15 Ver. 0.1

16 D0 D1 D2 D3 D COM0 COM1 COM2 COM3 COM4 Display data RAM Display on LCD The Page Address Circuit Figure. 3 As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address8 (D3, D2, D1, D0 = 1, 0, 0, 0,) is the page for the RAM region used; only display data D0 is used. The Column Address As shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read / write command. This allows the MPU display data to be accessed continuously. Moreover, the incrimination of column addresses stops with 83H, because the column address is independent of the page address. Thus, when moving, for example, from page0 column 83H to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. The Line Address Circuit Table. 4 SEG Output SEG0 SEG131 ADC 0 0 (H) Column Address 83 (H) (ADC) 1 83 (H) Column Address 0 (H) The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified. This is the COM0 output when the common output mode is normal and the COM63 output for NT7532, when the common output mode is reversed. The display area is a 65-line area for the NT7532 from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. 16 Ver. 0.1

17 Relationship between display data RAM and address. (if initial display line is 1DH) Page Address Data Line Address D0 00 D1 01 D2 02 D3, D2, D3 03 D1, D0 D4 Page0 04 0, 0, 0, 0 D5 05 D6 06 D7 07 D0 08 D1 09 D2 0A 0, 0, 0, 1 D3 0B Page1 D4 0C D5 0D D6 0E D7 0F D0 10 D1 11 D2 12 0, 0, 1, 0 D3 13 Page2 D4 14 D5 15 D6 16 D7 17 D0 18 D1 19 D2 1A 0, 0, 1, 1 D3 1B Page3 D4 1C D5 1D D6 1E D7 1F D0 20 D1 21 D2 22 0, 1, 0, 0 D3 23 Page4 D4 24 D5 25 D6 26 D7 27 D0 28 D1 29 D2 2A 0, 1, 0, 1 D3 2B Page5 D4 2C D5 2D D6 2E D7 2F D0 30 D1 31 D2 32 0, 1, 1, 0 D3 33 Page6 D4 34 D5 35 D6 36 D7 37 D0 38 D1 39 D2 3A 0, 1, 1, 1 D3 3B Page7 D4 3C D5 3D D6 3E D7 3F 1, 0, 0, 0 D0 Page8 Start COM output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS LCD OUT SEG0 SEG1 SEG2 SEG129 SEG130 SEG131 Column address D0= ADC D0= Figure Ver. 0.1

18 The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S = H and CLS = H. When CLS = L the oscillation stops, and the display clock is input through the CL terminal. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of access to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. CL FR COM0 V0 V1 V4 VSS V0 V1 COM1 V4 VSS RAM data SEGn V0 V2 V3 VSS Figure. 5 When multiple NT7532 chips are used, the slave chips must be supplied with the display timing signals (FR, CL, DOF ) from the master chip[s]. Table 5 shows the status of the FR, CL, and DOF signals. 18 Ver. 0.1

19 Table. 5 Operating Mode FR CL DOF Master (M/S = H ) The internal oscillator circuit is enabled (CLS = H ) Output Output The internal oscillator circuit is disabled (CLS Output Input = L ) Slave (M/S = L ) The internal oscillator circuit is disabled (CLS = H ) The internal oscillator circuit is disabled (CLS = L ) Input Input Table 6 shows the relationship between oscillation frequency and frame frequency Table. 6 Input Input Duty Item fcl ffr 1/65 On-chip oscillator is used fosc/6 fcl/(2 X 65) On-chip oscillator is not used External input fcl fcl/(2 X 65) 1/55 On-chip oscillator is used fosc/8 fcl/(2 X 55) On-chip oscillator is not used External input fcl fcl/(2 X 55) 1/49 On-chip oscillator is used fosc/8 fcl/(2 X 49) On-chip oscillator is not used External input fcl fcl/(2 X 49) 1/33 On-chip oscillator is used fosc/12 fcl/(2 X 33) On-chip oscillator is not used External input fcl fcl/(2 X 33) Common Output Control Circuit Output Output Input Input This circuit controls the relationship between the number of common output and specified duty ratio. Common output mode select instruction specifies the scanning direction of the common output pads. Table. 7 Common output pads Duty Status COM COM COM COM COM COM COM [0-15] [16-23] [24-26] [27-36] [37-39] [40-47] [48-63] COMS 1/33 COM[0-1 COM[16- Normal NC 5] 31] Reverse COM[31- COM[15-16] NC 0] COMS 1/49 Normal COM[0-23] NC COM[24-47] Reverse COM[47-24] NC COM[23-0] COMS 1/55 Normal COM[0-26] NC COM[27-53] Reverse COM[53-27] NC COM[26-0] COMS 1/65 Normal COM[0-63] Reverse COM[63-0] COMS This is 197-channel multiplexes that generate voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signals, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows example of the SEG and COM output waveform. 19 Ver. 0.1

20 Configuration Setting The NT7532 has two optional configurations, configured by DUTY0, DUTY1 DUTY1, DUTY0 Common Segment V1 V2 V3 V4 1, /9V0, 6/7V0 7/9V0, 5/7V0 2/9V0, 2/7 V0 1/9V0, 1/7V0 1, /8V0, 5/6V0 6/8V0, 4/6V0 2/8V0, 2/6 V0 1/8V0, 1/6V0 0, /8V0, 5/6V0 6/8V0, 4/6V0 2/8V0, 2/6 V0 1/8V0, 1/6V0 0, /6V0, 4/5V0 4/6V0, 3/5V0 2/6 V0, 2/5V0 1/6V0, 1/5V0 20 Ver. 0.1

21 21 Ver. 0.1 VDD FR COM0 COM1 COM2 SEG0 SEG1 COM0 - SEG0 COM0 - SEG1 VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG2 V1 V4 VSS V2 V0 V3 V1 V4 VSS V2 V0 V3 V1 V4 VSS V2 V0 V3 V1 V4 VSS V2 V0 V3 V1 V4 VSS V2 V0 V3 V1 V4 VSS V2 V0 V3 VSS V4 V3 V0 V2 V1 -V4 -V1 -V0 -V3 -V2 VSS V4 V3 V0 V2 V1 -V4 -V1 -V0 -V3 -V2 Figure. 6

22 The Power Supply Circuit The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control functions, and Table 8 shows reference combinations. Table. 8 The Control Details of Each Bit of the Power Control Set Command Item Status 1 0 D2 Booster circuit control bit ON OFF D1 Voltage regulator circuit (V regulator circuit) ON OFF control D0 Voltage bit follower circuit (V/F circuit) control bit ON OFF Use Settings D2 D 1 D0 Table. 9 St ep -u Voltage p regulato cir r circuit cu it V/F circuit External voltage input Step-up voltage system terminal Only the internal power supply is used O O O VDD2 Used Only the V regulator circuit and the V/F X O O VOUT, VDD2 Open circuit are used Only the V/F circuit is X X O V0, VDD2 Open Only the external power 0 supply is used 0 0 X X X V0 to V4 Open *The step-up system terminals refer CAP1+, CAP1-, CAP2+, CAP2-and CAP3+. *While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. The Step-up Voltage Circuits Using the step-up voltage circuits within the NT7532 chips it is possible to product 4X, 3X, 2X step-ups of the VDD2-VSS voltage levels 22 Ver. 0.1

23 C1 VSS VOUT C1 VSS VOUT C1 VSS VOUT C1 C1 CAP3+ CAP1- CAP1+ NT7502 C1 CAP3+ CAP1- CAP1+ NT7502 C1 CAP3+ CAP1- CAP1+ NT7502 C1 CAP2+ CAP2- C1 CAP2+ CAP2- CAP2+ CAP2-4x step-up voltage circuit 3x step-up voltage circuit 2x step-up voltage circuit VOUT = 4 X V DD2 = 12V VDD2 = 3V VSS = 0V VOUT = 3 X V DD2 = 9V VDD2 = 3V VSS = 0V VOUT = 2 X V DD2 = 6V VDD2 = 3V VSS = 0V 4x step-up voltage relationships 3x step-up voltage relationships 2x step-up voltage relationships The Voltage Regulator Circuit Figure. 7 The step-up voltage generated at VOUT outputs the liquid crystal driver voltage V0 through the voltage regulator circuit. Because the NT7532 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V0 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Moreover, in the NT7532, three types of thermal gradients have been prepared as VREG options: (1) approximately 0.05%/ (2) approximately 0.2%/, and (3) external input (supplied to the VEXT terminal). 23 Ver. 0.1

24 When the V0 Voltage Regulator Internal Resistors Are Used NT7532 Through the use of the V0 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V0 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V0 voltage can be calculated using equation A-1 over the range where V 0 < VOUT. V0 = ( 1+Rb/Ra)*VEV = ( 1+Rb/Ra)* (1-(63-α)/162)*VREG (Equation A-1) Rb Vout Vo Ra VEV Vss VEV (constant voltage supply + electronic volume) VREG is the IC internal fixed voltage supply, and its voltage at Ta = 25 is as shown in Table 10. Equipment Type TMPS VRS Table. 10 Thermal Gradient Units Internal power Supply %/ 2.1 Internal power Supply %/ 2.1 External input * VEXT α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for α depending on the electronic volume register settings. Ra/Rb is the V0 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V0 voltage regulator internal resistor ratio set command. The (1+Rb/Ra) ratio assumes the values shown in Table11 depending on the 3-bit data settings in the V0 voltage regulator internal resistor ratio register. VREG 24 Ver. 0.1

25 Table D4 D3 D2 D1 D0 α V Minimum : : : : : : (default) : : : : : : Maximum V0 voltage regulator internal resistance ratio register value and (1+ Rb/Ra) ratio (Reference value) Table. 12 Equipment Type by Thermal Gradient Register [Units:%/ ] D2 D1 D VREG External Input The V0 voltage as a function of the V0 voltage regulator internal resistor ratio register and the electronic volumn register. Setup example: When selecting Ta = 25 and V0 = 7V for an NT7532 model on which the temperature gradient = -0.05%, using the equation A-1, the following setup is enabled. Table. 13 Contents Register D5 D4D3 D2 D1D0 For V0 voltage regulator Electronic Volume When the V0 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF. The VR terminal is enabled only when the V0 voltage regulator internal resistors are not used (i.e. the IRS terminal = L ). When the V0 voltage regulator internal resistors are used (i.e. when the IRS ternimal = H ), then the VR terminal is left open. Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables,etc. to handle noise. 25 Ver. 0.1

26 The Liquid Crystal Voltage Generator Circuit NT7532 The V0 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2,V3, and V4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for NT7502 can be selected. High Power Mode The power supply circuit equipped in the NT7532 chips has very low power consumption (normal mode: HPM = H ). However for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to L (high power mode) can improve the quality of the display. We recommend that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a Command Sequence when Built-in Power Supply is turned OFF To turn off the built-in power supply, follow the command sequence as shown below to turn it off after making the system enter standby mode. 26 Ver. 0.1

27 Reference Power Supply Circuit for Driving LCD Panel -When using all LCD power circuits (Voltage converter regulator and follower) (In case of 3X boosting circuit) -When not using voltage booster circuits VDD VDD C1 M/S External Power Supply VOUT M/S C1 C1 Ra C2 C2 C2 C2 C2 Rb VOUT C3+ C2+ C2- C1+ C1- VR V0 V1 V2 V3 V4 Ra C2 C2 C2 C2 C2 Rb C3+ C2+ C2- C1+ C1- VR V0 V1 V2 V3 V4 VSS -When only using voltage follower VDD VSS -When not using internal LCD power supply circuits VDD M/S VSS External Power Supply C2 C2 C2 C2 C2 VOUT C3+ C2+ C2- C1+ C1- VR V0 V1 V2 V3 V4 *Value of External Capacitance Item C1 C2 Value µf External Power Supply VOUT C3+ C2+ C1+ C2- C1- VR V0 V1 V2 V3 V4 M/S VSS 27 Ver. 0.1

28 Reset Circuit When the RES input falls to L, these LSI reenter their default state. The default settings are shown below: 1. Display OFF 2. Normal display 3. ADC select: Normal display (ADC command D0 = L ) 4. Power control register (D2, D1, D0) = (0, 0, 0,) 5. Register data clear in serial interface 6. LCD power supply bias ratio 1/9 (1/65 duty), 1/8 (1/55, 1/49 duty), 1/6 (1/33 duty) 7. Read modify write OFF 8. Static indicator: OFF Static indicator register: (D1, D2) = (0, 0) 9. Display start line register set at first line 10. Column address counter set at address0 11. Page address register set at page Common output status normal 13. V0 voltage regulator internal power supply ratio set mode clear: V0 voltage regulator internal resistor ratio register: (D2, D1, D0) = (1, 0, 0) 14. Electronic volume register set mode clear Electronic volume register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0,) 15. Test mode clear 16. All-indicator-lamps-on OFF (All-indicator-lamps ON/OFF command D0 = L ) 17. Output condition of COM, SEG COM: V1 SEG: V2 On the other hand, when the reset command is used only default settings 7 to 15 above are put into effect. The MPU interface (Reference Example), the RES terminal is connected to the MPU reset terminal, making the chip reinitialize simultaneously with the MPU. At the time of power up, it is necessary to reinitialize using the RES terminal. Moreover, when the control signal from the MPU is in a high impedance state, there may be an overcurrent condition; therefore, take measures to prevent the input terminal from entering a high impedance state. In the NT7532, if the internal liquid crystal power supply circuit is not used, then it is necessary to apply an L signal to the RES terminal when the external liquid crystal power supply is applied. Even though the oscillator circuit operates while the RES terminal is L, the display timing generator circuit is stopped, and the FR, FRS, and DOF terminals are fixed to H, and the CL pin is fixed to H only when the intermal oscillator circuit is used. There is no influence on the D0 to D7 terminals. 28 Ver. 0.1

29 Commands The NT7532 uses a combination of A0, RD(E) and WR ( R/ W ) signals to identify data bus signals. As the chip analyzes and executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its busy check is usually not required. The 8080 series microprocessor interface enters a read status when a low pulse is input to the RD pad and a write status when a low pulse is input to the WR pad. The 6800 series microprocessor interface enters a read status when a high pulse is input to the R/ W pad and a write status when a low pulse is input to this pad. When a high pulse is input to the E pad, the command is activated. (For timing, see AC Characteristics.). Accordingly, in the command explanation and command table, RD (E) becomes 1(high) when the 6800 series microprocessor interface reads status of display data. This is the only different point from the 8080 series microprocessor interface. Taking the 8080 series microprocessor interface as an example, commands are explained below. When the serial interface is selected, input data starting from D7 in sequence. Command Set 1. Display ON/OFF Alternatively turns the display on and off. E R/ W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR Setting Display ON 0 Display OFF When the display OFF command is executed when in the display all points ON mode, power save mode is entered. See the section on the power saver for details. 2. Set Display Start Line Specifies line address (refer to Figure 4) to determine the initial display line, or COM0. The RAM display data becomes the top line of LCD screen. The higher number of lines in ascending order, corresponding to the duty cycle follows it. When this command changes the line address, smooth scrolling or a page change takes place. E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR A5 A4 A3 A2 A1 A0 High-order bit A5 A4 A3 A2 A1 A0 Line address : : Ver. 0.1

30 3. Set Page Address Specifies page address to load display RAM data to page address register. Any RAM data bit can be accessed when its page address and column address are specified. The display remains unchanged even when the page address is changed. Page address 8 is the display RAM area dedicates to the indicator, and only D0 is valid for data change. A0 E RD R / W WR D7 D6 D5 D4 D3 D2 D1 D A3 A2 A1 A0 A3 A2 A1 A0 Page address Set Column Address Specifies column address of display RAM. Divide the column address into 4 higher bits and 4 lower bits. Set each of them succession. When the microprocessor repeats to access the display RAM, the column address counter is incremental by during each access until address 132 is accessed. The page address is not changed during this time. A0 E RD R / W D7 D6 D5 D4 D3 D2 D1 D0 WR Higher bits A7 A6 A5 A4 Lower bits A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 Line address : : Ver. 0.1

31 5. Read Status E A0 RD R / W WR BUSY ADC D7 D6 D5 D4 D3 D2 D1 D0 ON/OFRESE F T NT7532 Busy: When high, the NT7532 is busy due to internal operation or reset. Any command is rejected until BUSY goes low. The busy check is not required if enough time is provided for each cycle. ADC: Indicates the relationship between RAM column address and segment drivers. When low, the display is reversed and column address 131-n corresponds to segment driver n. when high, the display is normal and column address corresponds to segment driver n. ON/OFF: Indicates whether the display is on or off. When low, the display turns on. When high, the display turns off. This is the opposite of Display ON/OFF command RESET: Indicates the initialization is in progress by RES signal or by reset command. When low, the display is on. When high, the chip is being reset. 6. Write Display Data Write 8-bit data in display RAM. As the column address automatically increments by 1 after each write, the microprocessor can continue to write data of multiple words. A0 E RD R/ W WR D7 D6 D5 D4 D3 D2 D1 D Write data 7. Read Display Data Reads 8-bit data from display RAM area specified by column address and page address. As the column address automatically increments by 1 after each write, the microprocessor can continue to read data of multiple words. A single dummy read is required immediately after column address setup. Refer to the display RAM section of FUNCTIONAL DESCRIPTION for details. Note that no display data can be read via the serial interface. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D Read data 8. ADC Select Changes the relationship between RAM column address and segment driver. The order of segment driver output pads could be reversed by software. This allows flexible IC layout during LCD module assembly. For details, refer to the column address section of Figure4. When display data is written or read, the column address is incremented by 1 as shown in Figure4. E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR D When D is low, rotation is to the right (normal direction) When D is high, rotation is to the left (reverse direction) 31 Ver. 0.1

32 9. Normal/ Reverse Display Reverses the Display ON/OFF status without rewriting the contents of the display data RAM. E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR D When D is low, the RAM data is high, being LCD ON potential (normal display) When D is high, the RAM data is low, being LCD ON potential (reverse display) NT Entire Display ON Forcibly turns the entire display on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This command has priority over the Normal/Reverse Display command. When D is low, the normal display status is provided. A0 E RD R/ W WR D7 D6 D5 D4 D3 D2 D1 D D When D is high, the entire display ON status is provided. If the Entire Display ON command is executed in the display OFF status, the LCD panel enters Power save mode. Refer to the Power Save section for details. 11. Set LCD Bias This command selects the voltage bias ratio required for the liquid crystal display. A0 E RD R / W Duty WR D7 D6 D5 D4 D3 D2 D1 D0 1/33 1/49 1/55 1/ /6 bias 1/8 bias 1/8 bias 1/9 bias 1 1/5 bias 1/6 bias 1/6 bias 1/7 bias 12. Read-Modify-Write A pair of Read-Modify-Write and End commands must always be used. Once Read-Modify-Write is issued, column address is not incremental by Read Display Data command but incremental by Write Display Data command only. It continues until End command is issued. When the End is issued, column address returns to the address when Read-Modify-Write is issued. This can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or other events. A0 E RD R/ W WR D7 D6 D5 D4 D3 D2 D1 D Note: Any command except Read/Write Display Data and Set Column Address can be issued during Read-Modify-Write mode. Cursor display sequence 32 Ver. 0.1

33 Set Page Address Set Column Address Read-Modify-Write Dummy Read No Read Data Write Data Data process Completed? Yes End 13. End Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write is issued) A0 E RD R/ W WR D7 D6 D5 D4 D3 D2 D1 D Return Column address N N+1 N+2 N+3 N+m N Read-Modify-Write mode is selected End 14. Reset This command resets the Display Start Line register, Column Address counter, Page Address register, and Common output mode register, the V0 voltage regulator internal resistor ratio register, the Electronic Volume register, the static indicator mode register, the read-modify-write mode register, and the test mode. The Reset command does not affect on the contents of display RAM. Refer to the Reset circuit section of Function Description. E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR Ver. 0.1

34 The Reset command cannot initialize LCD power supply. Only the Reset signal to the RES pad can initialize the supplies. 15. Output Status Select Register Applicable to the NT7532. When D is high or low, the scan direction of the COM output pad is selectable. Refer to Output Status Selector Circuit in Function Description for details. E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR D * * * D: Selects the scan direction of COM output pad D = 0: Normal (COM0 COM63/53/47/31) D = 1: Reverse (COM63/53/47/31 COM0) *: Invalid bit 16. Set Power Control Selects one of eight power circuit functions using 3-bit register. An external power supply and part of on-chip power circuit can be used simultaneously. Refer to Power Supply Circuit section of FUNCTIONAL DESCRIPTION for details. E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR A2 A1 A0 When A0 goes low, voltage follower turns off. When A0 goes high, it turns on. When A1 goes low, voltage regulator turns off. When A1 goes high, it turns on. When A2 goes low, voltage booster turns off. When A2 goes high, it turns on. 17. V0 Voltage Regulator Internal Resistor Ratio Set This command sets the V0 voltage regulator internal resistor ratio. For details, see explanation under The Power Supply Circuits. A0 E RD R / W WR D7 D6 D5 D4 D3 D2 D1 D0 Rb / Ra Ratio Small : : Large 18. The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V0 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. 34 Ver. 0.1

35 The Electronic Volume Mode Set When this command is input, the electronic volume register set command is enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. A0 E RD R/ W WR D7 D6 D5 D4 D3 D2 D1 D Electronic Volume Register Set By using this com mand to set six bits of data to the electronic volume register, the liquid crystal voltage V0 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. V0 A0 E R / W D7 D6 D5 D4 D3 D2 D1 D0 RD WR * * Small * * * * * * : : * * * * Large When the electronic volume function is not used, set D5 - D0 to Ver. 0.1

36 19. Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus command must be executed one after the other. (The static indicator OFF command is a single byte command.) Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. A0 E RD R/ W WR D7 D6 D5 D4 D3 D2 D1 D D D = 0: Static Indicator OFF D = 1: Static Indicator ON Static Indicator Register Set These command sets two bits of data into the static indicator register and are used to set the static indicator into a blinking mode. A0 E R / W D7 D6 D5 D4 D3 D2 D1 D0 RD WR Indicator Display State * * * * * * 0 0 OFF 0 1 ON (blinking at approximately 0.5 second intervals 1 0 ON (blinking at approximately 1 second intervals 1 1 ON (constantly on) * Disabled bit 20. Power Save (Compound Command) When all displays are turned on during display off, the Power Save command is issued to greatly reduce current consumption. If the static indicators are off, the Power Save command makes the system enter sleep mode. If on, this command makes the system enter standby mode. Release the Sleep mode using the both Power Save OFF command (Display ON command or Entire Display OFF command) and Set Indicator On command. 36 Ver. 0.1

37 Static Indicator OFF Static Indicator ON Power Save (Display OFF and Entire Display ON) (Sleep mode) (Standby mode) Power Save OFF (Display ON or Entire Displays OFF ) Static Indicator ON (Sleep mode released) (Standby mode released) Sleep Mode This mode stops every operation of the LCD display system, and can reduce current consumption nearly to a static current value if no access is made from the microprocessor. The internal status in the sleep mode is as follows: (1) Stops the oscillator circuit and LCD power supply circuit. (2) Stops the LCD drive and outputs the VSS level as the segment/common driver output. (3) Holds the display data and operation mode provided before the start of the sleep mode. (4) The MPU can access the built-in display RAM. Standby Mode Stops the operation of the duty LCD displays system and turns on only the static drive system to reduce current consumption to the minimum level required for static drive. The ON operation of the static drive system indicates that the NT7532 is in standby mode. The internal status in the standby mode is as follows: (1) Stops the LCD power supply circuit. (2) Stops the LCD drive and outputs the VSS level as the segment / common driver output. However, the static drive system still operates. (3) Holds the display data and operation mode provided before the start of the standby mode. (4) The MPU can access the built-in display RAM. When the RESET command is issued in the standby mode, the sleep mode is set. When the LCD drive voltage level is given by an external resistive driver, the current of this resistor must be cut so that it may be fixed to floating or VSS level, prior to or concurrently with causing the NT7532 to go to the sleep mode or standby mode. When an external power supply is used, likewise, the function of this external power supply must be stopped so that it may be fixed to floating or VSS level, prior to or concurrently with causing the NT7532 to go to the sleep mode or standby mode. 37 Ver. 0.1

38 21. NOP Non-Operation Command E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR Test Command This is the dedicated IC chip test command. It must not be used for normal operation. If the Test command is issued inadvertently set the RES input to low or issue the Reset command to release the test mode. E R / W A0 D7 D6 D5 D4 D3 D2 D1 D0 RD WR * * * * *: Invalid bit Cautions: The NT7532 maintains an operation status specified by each command. However, the internal operation status may be changed by a high level of ambient noise. Users must consider how to suppress noise on the package and system or to prevent ambient noise insertion. To prevent a spike in noise, built-in software for periodical status refreshment is recommended. The test command can be inserted in an unexpected place. Therefore it is recommended to enter the test mode reset command F0h during the refresh sequence. 38 Ver. 0.1