RW x32 Dot Matrix LCD Controller / Driver

Transcription

1 FEATURES Direct display of RAM data through the display data RAM. RAM capacity:64 x 64 = 4096 bits Display duty selectable by software /64 duty:64common x 28segment (RW065 x 2) 64common x 92segment (RW065 x 3) /32 duty:32common x 28segment (RW065 x 2) 32common x 92segment (RW065 x 3) High-speed 8-bit MPU interface (The chip can be connected directly to the 6800 series MPUs) Abundant command functions Display data Read/Write, display ON/OFF, Normal/Reverse display mode, page address set, display start line set, column address set, status read, display all point ON/OFF, read/modify/write, segment driver direction selects, power saver. Low-power liquid crystal display power supply circuit equipped internally. Bias set /5 /6 /8 /9 by pin. Booster circuit (with Boost ratios of 2X/3X/4X, where the step-up voltage reference power supply can be input externally). voltage regulator resistors equipped externally, V to V4 voltage divider resistors equipped internally, voltage follower. CR oscillator circuit equipped internally (external clock can also be input) Low power consumption. Logic power supply VSS = 2.7V to 5.5 V Boost reference voltage: 2 VSS = 2.7V to 5.5V Booster maximum voltage limited VOUT=7.0V Liquid crystal drive power supply: VSS = 4.0V to 5.0 V Wide range of operating temperatures: 40 to 85 C CMOS process. Shipping forms include bare chip and COB. Software compatible to KS008. GENERAL DESCRIPTION The RW065 is a single-chip dot matrix LCD driver that can be connected directly to a microprocessor bus. 8-bit parallel display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the RW065 contain 64x64 bits of display data RAM and there is a -to- correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The RW065 chips contain 32 common output circuits and 64 segment output circuits, so that two RW065 chips can drive a 64x28 dot display (capable of displaying 8 columnsx4 rows of a 6x6 dot kanji font). Moreover, the capacity of the display can be extended through the use of master/slave structures up to three RW065 chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power LCD driver power supply, and a display clock CR oscillator circuit, the RW065 can be used to create the lowest power display system with the fewest components for high-performance portable devices.

2 RW065 Serial Revision History Version Date Description. Modify set voltage circuit drawing 2006/05/ /07/05 Pad Configuration add Substrate connects to VSS /07/ /07/ /07/24 Modify Vout maximum voltage Add CHIP LAYOUT Modify Pad Center Coordinates Modify standard circuit SHL Pin Modify LCD Driver Circuit Signals Modify System Bus Connection Pin CS and CS2 change to CSBP and CS2P /08/ Modify Display Command Instruction /08/7 Add reference example for external multi-level power supply for lcd driving Add reference example for single chip solution for RW065 application Add reference example for an adjustable resistor on the main board to control the contrast of liquid crystal display change bypass capacitor value for v v4 Add PCB footprint style //3 Add the package information 2

3 BLOCK DIAGRAM 3 63 V4 SHL ADC /RST CS2P CSBP RS BS BS0 3

4 PAD ARRANGEMENT COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM20 COM2 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM SEG63 SEG62 SEG6 SEG60 SEG59 SEG58 SEG57 SEG SEG SEG54 24 SEG SEG SEG SEG SEG SEG SEG SEG SEG45 SEG SEG43 SEG42 SEG4 SEG40 SEG39 SEG Y SEG37 X SEG36 SEG SEG Chip size: 4897 um x902um SEG Pad size: 87.5um x 87.5um SEG SEG3 Pad pitch : 28um ~ 92um SEG30 Chip thickness: 470 um 0 54 SEG Substrate connects to VSS SEG SEG SEG26 97 SEG SEG SEG SEG SEG SEG SEG SEG8 65 SEG7 SEG6 SEG5 SEG C0503 COM2 COM COM0 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM0 V V4 V2 V3 VRAB VOUT CAP3P CAPN CAPP CAP2P CAP2N 2 SHLP BS0P BSP MSP FRR CLSP RSTP RWP RSP EP CS2P CSBP D7 D6 D5 D4 D3 D2 D D0 Vss SEG3 SEG2 SEG SEG0 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG0 ADCR CLL 4

5 CHIP LAYOUT PIN Digital Analog RAM 5

6 PAD CENTER COORDINATES RW065 DUTY=/64 duty, SHL=0 Pad Pin Name Pad Pad Pin Name X Y Pin Name X Y Master Slave No. No. Master Slave X Y COM3 COM SEG D COM4 COM SEG D COM5 COM SEG D COM6 COM SEG D COM7 COM SEG D COM8 COM SEG D COM9 COM SEG CSBP COM20 COM SEG CS2P COM2 COM SEG EP COM22 COM SEG RSP COM23 COM SEG RWP COM24 COM SEG COM25 COM SEG RSTP COM26 COM SEG CLSP COM27 COM SEG FRR COM28 COM SEG MSP COM29 COM SEG BSP COM30 COM SEG BS0P COM3 COM SEG SHLP SEG SEG SEG SEG CAP2N SEG SEG CAP2P SEG SEG CAPP SEG SEG CAPN SEG SEG CAP3P SEG SEG VOUT SEG SEG SEG SEG VRAB SEG SEG V SEG SEG V SEG SEG V SEG SEG V SEG SEG COM0 COM SEG SEG COM COM SEG SEG COM2 COM SEG SEG COM3 COM SEG SEG COM4 COM SEG SEG COM5 COM SEG SEG COM6 COM SEG ADCP COM7 COM SEG CLL COM8 COM SEG VSS COM9 COM SEG D COM0 COM SEG D COM COM COM2 COM

7 PAD CENTER COORDINATES RW065 DUTY=/64 duty, SHL= Pad Pin Name Pad Pad Pin Name X Y Pin Name X Y Master Slave No. No. Master Slave X Y COM50 COM SEG D COM49 COM SEG D COM48 COM SEG D COM47 COM SEG D COM46 COM SEG D COM45 COM SEG D COM44 COM SEG CSBP COM43 COM SEG CS2P COM42 COM SEG EP COM4 COM SEG RSP COM40 COM SEG RWP COM39 COM SEG COM38 COM SEG RSTP COM37 COM SEG CLSP COM36 COM SEG FRR COM35 COM SEG MSP COM34 COM SEG BSP COM33 COM SEG BS0P COM32 COM SEG SHLP SEG SEG SEG SEG CAP2N SEG SEG CAP2P SEG SEG CAPP SEG SEG CAPN SEG SEG CAP3P SEG SEG VOUT SEG SEG SEG SEG VRAB SEG SEG V SEG SEG V SEG SEG V SEG SEG V SEG SEG COM63 COM SEG SEG COM62 COM SEG SEG COM6 COM SEG SEG COM60 COM SEG SEG COM59 COM SEG SEG COM58 COM SEG SEG COM57 COM SEG ADCP COM56 COM SEG CLL COM55 COM SEG VSS COM54 COM SEG D COM53 COM SEG D COM52 COM COM5 COM

8 PAD CENTER COORDINATES RW065 DUTY=/32 duty, SHL=0 Pad Pin Name Pad Pad Pin Name X Y Pin Name X Y Master Slave No. No. Master Slave X Y COM3 COM SEG D COM4 COM SEG D COM5 COM SEG D NC NC SEG D NC NC SEG D NC NC SEG D NC NC SEG CSBP NC NC SEG CS2P NC NC SEG EP NC NC SEG RSP NC NC SEG RWP NC NC SEG NC NC SEG RSTP NC NC SEG CLSP NC NC SEG FRR NC NC SEG MSP NC NC SEG BSP NC NC SEG BS0P NC NC SEG SHLP SEG SEG SEG SEG CAP2N SEG SEG CAP2P SEG SEG CAPP SEG SEG CAPN SEG SEG CAP3P SEG SEG VOUT SEG SEG SEG SEG VRAB SEG SEG V SEG SEG V SEG SEG V SEG SEG V SEG SEG COM0 COM SEG SEG COM COM SEG SEG COM2 COM SEG SEG COM3 COM SEG SEG COM4 COM SEG SEG COM5 COM SEG SEG COM6 COM SEG ADCP COM7 COM SEG CLL COM8 COM SEG VSS COM9 COM SEG D COM0 COM SEG D COM COM COM2 COM

9 PAD CENTER COORDINATES RW065 DUTY=/32 duty, SHL= Pad Pin Name Pad Pad Pin Name X Y Pin Name X Y Master Slave No. No. Master Slave X Y COM8 COM SEG D COM7 COM SEG D COM6 COM SEG D NC NC SEG D NC NC SEG D NC NC SEG D NC NC SEG CSBP NC NC SEG CS2P NC NC SEG EP NC NC SEG RSP NC NC SEG RWP NC NC SEG NC NC SEG RSTP NC NC SEG CLSP NC NC SEG FRR NC NC SEG MSP NC NC SEG BSP NC NC SEG BS0P NC NC SEG SHLP SEG SEG SEG SEG CAP2N SEG SEG CAP2P SEG SEG CAPP SEG SEG CAPN SEG SEG CAP3P SEG SEG VOUT SEG SEG SEG SEG VRAB SEG SEG V SEG SEG V SEG SEG V SEG SEG V SEG SEG COM3 COM SEG SEG COM30 COM SEG SEG COM29 COM SEG SEG COM28 COM SEG SEG COM27 COM SEG SEG COM26 COM SEG SEG COM25 COM SEG ADCP COM24 COM SEG CLL COM23 COM SEG VSS COM22 COM SEG D COM2 COM SEG D COM20 COM COM9 COM

10 Pin Description ()Power Pins Name I/O Description - Connected to the +5V 0r +3V dc power. Common to the Vcc MPU power pin. 2 This is the retevence power supply for the Step-up voltage circuit. VSS - 0V dc pin connected to the system ground. CAPP~3P CAPN~2N ~V4 - - Capacitor connector pin for voltage booster. Multi-level power supplies for LCD driving. The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied. These voltages must satisfy the following: V V2 V3 V4 VSS (2)System Bus Connection Pins Name I/O Description The 8-bit bidirectional data buses to be connected to the 8- or 6- bit standard MCU D7 to D0 I/O Data busses. Usually connected to the low-order bit of the MPU address bus and used to identify the data or a command. RS I RS=0: D0 to D7 are display control data. RS=: D0 to D7 are display data. CLS I CLS= : internal oscillator enable CLS=0 : external clock operation mode ADCP SHLP BSP,BS0P RST I I I I The pin selects the relationship between display data RAM column addresses and segment drivers. ADCP=: SEG0 column address 3FH,..inverted ADCP=0: SEG0 column address 00H,..normal The pin selects the com output scan direction. SHL=: Reverse direction,com63 com0 SHL=0: Normal com0 com63 Both master and slave should set identical SHL value Select LCD Bias /5, /6, /8, /9 bias BSP=0, BS0P=0 : /5 bias BSP=0, BS0P= : /6 bias BSP=, BS0P=0 : /8 bias BSP=, BS0P= : /9 bias Input low active. System reset. CSBP, CS2P I Input. When CSBP = 0 and CS2P = the chip select become active E I For 68-series MPU : Input. Active high. Used as an enable clock input of the 68-series MPU. For 68-series MPU : Input. R/W I Used as an input pin of read control signals (if R/W is high) or write control signals signals (if low). 0

11 (3)LCD Driver Circuit Signals Name I/O Description CLL I/O Input/output. I/O selection M/S = H & CLS = H :Output M/S = L & CLS = H :Input M/S = X & CLS = L :Input This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. SEGn COMn FRR O O I/O Output. A single level of, V2, V3 and VSS is selected by the combination of display RAM contents and FR signal. Output. The output pin for LCD common (row) driving. A single level of, V, V4 and VSS is selected by the combination of common counter output and FR signal. The slave LSI has the reverse common output scan sequence than the master LSI. Input/output. This is the liquid crystal alternating current signal I/O terminal l/o selection M/S = H :Output M/S = L :Input VRAB I Provides the voltage between and VSS through a resistive voltage divider. Input. The master or slave LSI operation select pin for the RW065. M/S I M/S Operating Mode High Master Output FR CL ~V4 Power Internal Supply OSC See See On On CLS CLS Low Slave Input Input Off Off Off COMMON Output SEG output COM0-3 SEG0-63 COM32-63 SEG64-27

12 DESCRIPTION OF FUNCTIONS The Parallel Interface (6800 series MPU) RW065 Shared 6800 Series RS R/W Function Reads the display data 0 Writes the display data 0 Status read 0 0 Write control data (command) The Chip Select The RW065 Series chips have two chip select terminals: CS BP and CS2P. When the chip select is inactive, D0 to D7 enter a high impedance state, and the RS, E, and RW inputs are inactive. The Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the the first data read cycle (dummy) stores the read data MPU is required to satisfy the cycle time (tcyc) in the bus holder, and then the data is read from the requirement alone in accessing the RW065 Series. bus holder to the system bus at the next data read Wait time may not be considered. cycle. There is a certain restriction in the read And, in the RW065 Series chips, each time data is sequence of the display data RAM. Please be advised sent from the MPU, a type of pipeline process that data of the specified address is not generated by between LSIs is performed through the bus holder the read instruction issued immediately after the attached to the internal data bus. Internal data bus. address setup. This data is generated in data read of For example, when the MPU writes data to the display the second time. Thus, a dummy read is required data RAM, once the data is stored in the bus holder, whenever the address setup or write cycle operation then it is written to the display data RAM before the is conducted. next data write cycle. Moreover, when the MPU reads This relationship is shown in Figure 2. the display data RAM, 2

13 RS E Fig. 2.a write timing (RW= L ) RS RW E Fig. 2.b read timing 3

14 Display Data RAM The display data RAM is a RAM that stores the dot data for the display. It has a 64 (8 page x 8 bit) x 64 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display data transfer when multiple RW065 series chips are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). D0 0 0 COM0 D COM D COM2 D3 0 0 COM3 D COM4 - - Display data RAM Liquid crystal display Figure3 The Page Address Circuit As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. The Column Address As is shown in Table 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the increment of column addresses stops with 3FH. Because the column address is independent of the page address, when moving, for example, from page 0 column 3FH to page column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. Table 4 SEG Output ADC set SEG0 SEG 63 ADC(D0)=0 0 Column Address 63 ADC(D0)= 63 Column Address 0 4

15 Page Address D3 D2 D D0 Data SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG6 SEG62 SEG63 SEG COM D0 COM0 D COM D2 COM D3 D4 Page 0 COM3 COM4 D5 COM5 D6 COM6 D7 COM7 D0 COM8 D COM9 D2 COM D3 D4 Page COM COM2 D5 COM3 D6 COM4 D7 COM5 D0 COM6 D COM7 D2 COM D3 D4 Page 2 COM9 COM20 D5 COM2 D6 COM22 D7 COM23 D0 COM24 D COM25 D2 COM D3 D4 Page 3 COM27 COM28 D5 COM29 D6 COM30 D7 COM3 COLUMN ADC=0 ADC= Figure 4 5

16 Common Timing Generator Circuit Display Data Latch Circuit Generates common timing signals and FR frame This latch stores one line of display data for use by signals from the CL basic clock. The /32 or /64 duty the LCD driver interface circuitry. The output of this (for RW065) can be selected by the Duty Select latch is controlled by the Display ON/OFF. command. The /32 and /64 duties are provided by two chips consisting of the master and slave chips in the common multi-chip mode. /32 duty: SHL=0 SHL= /64 duty: SHL=0 SHL= 6

17 Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Two-frame alternating current drive waveform Figure 5 When multiple RW065 Series chips are used, the slave chip must be supplied the display timing signals (FR, CL) from the master chip. Table 5 shows the status of the FR and CL signals. Table 5 Operating Mode FR CL Master (M/S = H ) The internal oscillator circuit is enabled (CLS = H ) The internal oscillator circuit is disabled (CLS = L ) Output Output Output Input Slave (M/S = L ) The internal oscillator circuit is enabled (CLS = H ) The internal oscillator circuit is disabled (CLS = L ) Input Input Input Input 7

18 The Liquid Crystal Driver Circuits These are a 64-channel (RW065), that generate four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows examples of the SEG and COM output waveform. Figure 6 8

19 The Power Supply Circuit The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn on automatically after power on. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. The Liquid Crystal Voltage Generator Circuit The voltage is produced by a resistive voltage divider outside the IC through VRAB pin, and can be produced at the V, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V, V2, V3 and V4 to the liquid crystal drive circuit. /5 bias or /6 bias or /8 bias or /9 bias for RW065, can be selected by BS0 and BS pins. -Vss maximum voltage is 5V, Vout-Vss maximum voltage is 7V. If < 3.5V, it can use the Booster circuit 2x,3x,4x,The booster voltage can follow the spec. condition (Vout- Vss 7V max. voltage.) if >3.5V only use the 2X,3X, booster circuit, that can ensure the -Vss voltage 5V. If use the voltage 5V and 4X booster, it s over the spec. operation condition. To turn on built-in power (booster/follower) must waiting 200mS to display on for booster/follower stable. Therefore, power off must follower power off sequence too. Power on Display off Wait time >200mS Power off Display on Power on sequence Power off sequence 9

20 The Reset Circuit When the RTP input comes to the L level, these LSIs return to the default state. Their default states are as follows:. Display OFF 2. Display all point on is select to normal 3. Display normal/reverse is select to normal 4. /64 duty is selected 5. Read modify write OFF 6. Column address set to Address 0 7. Page address set to Page 0 8. Start line set to first line 9. Frame frequency set to default 0. Power save mode released. Ext set to 0 When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RSTP terminal. After the initialization, each input terminal should be controlled normally. While RSTP is L, the oscillator works but the display timing generator stops, and the CL, FR, terminals are fixed to H. The terminals D0 to D7 are not affected. 20

21 TABLE OF RW065 INSTRUCTIONS Instruction Instruction code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 Description EXT=0 or MODE SET EXT Set EXT mode Instruction EXT=0 Display ON/OFF Set page address Set column address Instruction code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB D Description D=0:Display OFF D=:Display ON P2 P P0 Set page address Y5 Y4 Y3 Y2 Y Y0 Read Status 0 BUSY 0 Write display data Read display data Set initial display line register ON /OFF 0 Write data Read data RESET S5 S4 S3 S2 S S0 Set column address MSB Read register status Write data into DDRAM Read data from DDRAM Specify the initial display line to realize vertical scrolling Instruction EXT= Instruction code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB0 Description NOP no operation Set modiyread END Set power save mode Display COMMAND (double command) PSAVE FRSEL REV ALL ON DUTY Set modiy-read mode release modiyread mode P=0: normal mode P=: sleep mode DUTY=: 64 duty DUTY=0: 32 duty ALLON=:display all on ALLON=0:display normal REV=:display reverse REV=0:display normal FRSEL=:FR frequency double default FRSEL=0:FR frequency default 2

22 Command Description See the Table of RW065 instructions. The RW065 series identifies a data bus using a combination of RS, E and RW signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed is very high. The busy check is usually not required. Display ON/OFF EXT RS RW D7 D6 D5 D4 D3 D2 D D D This command turns the display on and off. D=: Display ON D=0: Display OFF(default) Set page Address This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified. The display status is not changed even when the page address is changed. EXT RS RW D7 D6 D5 D4 D3 D2 D D A2 A A0 This command loads the page address register. A2 A A0 Page (default) Page mapping see Figure 4 22

23 Set Column Address This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU continuously, the column address is incremented by I each time it is accessed from the set address. Therefore, the MPU can access to data continuously. The column address stops to be incremented at address 63, and the page address is not changed continuously. EXT RS RW D7 D6 D5 D4 D3 D2 D D A5 A4 A3 A2 A A0 A5 A4 A3 A2 A A0 Column Address (default) Read Status EXT RS RW D7 D6 D5 D4 D3 D2 D D0 0 0 BUSY 0 ON/ OFF The BUSY Flag bit indicates that RW 065 is operating or no operating. BUSY=: Operation BUSY=0: Ready The ON/OFF bit indicates the current status of the display. It is the inverse of the polarity of the display ON/OFF command. ON/OFF=: Display OFF ON/OFF=0: Display ON RESET The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode. RESET=: Currently executing reset command RESET=0: Normal operation 23

24 Write Display Data RW065 EXT RS RW D7 D6 D5 D4 D3 D2 D D0 0 0 Write data Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page, address registers and then increments the column address register by one. Read Display Data EXT RS RW D7 D6 D5 D4 D3 D2 D D0 0 Read data Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data RAM location specified by the contents of the column address and page address registers and then increments the column address register. After loading a new address into the column address register one dummy read is required before valid data is obtained. Set initial display line register EXT RS RW D7 D6 D5 D4 D3 D2 D D S5 S4 S3 S2 S S0 Loads the RAM line address of the initial display line, COM 0, into the initial display line register. The RAM display data becomes the top line of the LCD screen. It is followed by the higher number lines in ascending order, corresponding to the duty cycle. The screen can be scrolled using this command by incrementing the line address.(default value= 00H ) 24

25 Read-Modify-Write RW065 EXT RS RW D7 D6 D5 D4 D3 D2 D D This command defeats column address register auto-increment after data reads. The current contents of the column Address register are saved. The mode remains active until an End command is received. When the End command is entered, the column address is returned to the one used during input of Read- Modify-Write Command. This function can reduce the load of MPU when data change is repeated as a specific display area. *Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column Address Set command cannot be used. Set page address Set column address Read-modify-write Dummy read Read data Write data No Completed? End Yes End EXT RS RW D7 D6 D5 D4 D3 D2 D D This command cancels read-modify-write mode and restores the contents of the column address register to their value prior to the receipt of the Read-Modify-Write command. Returm Column address N N+ N+2 N+3 N+m N Read -modify-write mode set End 25

26 Set power save mode RW065 EXT RS RW D7 D6 D5 D4 D3 D2 D D PSAVE When power save mode is entered, thus greatly reducing power consumption. In the power save mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. PSAVE=: Sleep mode PSAVE=0: Normal mode Sleep mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows:. The oscillator circuit and the LCD power supply circuit are halted. 2. All liquid crystal drive circuits are halted, and the segment and common drive outputs output a Vss level. Display command :double command EXT RS RW D7 D6 D5 D4 D3 D2 D D FRSEL REV ALLON DUTY Display Normal/Reverse set REV=: Reverse REV=0: Normal(default) Display All Point ON/OFF ALLON=: All display points ON ALLON=0: Normal(default) Select Duty Duty=: /64 duty cycle(default) Duty=0: /32 duty cycle FRAME FREQUENCY Select FRSEL=: Double FRSEL=0: (default) 26

27 Hardware Pin Set Select ADC by ADC Pin The pin selects the relationship between display data RAM column addresses and segment drivers. ADC=: SEG0 column address 3FH,..inverted ADC=0: SEG0 column address 00H,..normal(default) This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit Board design.see Figure 4 for a table of segments and column addresses for the two values of D. Select SHL by SHL Pin The pin selects the com output scan direction. SHL=: Reverse direction,com63 com0 SHL=0: Normal com0 com63 Both master and slave should set identical SHL value Select LCD Bias by BS0, BS Pin BS BS0 Bias 0 0 /5 bias 0 /6 bias 0 /8 bias /9 bias 27

28 When an External Resistance is Used The liquid crystal power supply voltage is set by adding resistors Ra and Rb between and VR, and between VR and, respectively. RW065 RW065 28

29 The set voltage circuits Using the step-up voltage circuits equipped within the RW065 chips, it is possible to produce a 2X, 3X, 4X, step-up voltage levels. 2X step-up To produce voltage level in the positive direction at the Vout terminal that is 2 times the voltage difference between VSS and 2. Please configure set voltage circuits like this. Place a uf~2.2uf capacitor between CAPN and CAPP. Place a uf~2.2uf capacitor between VSS and VOUT. Short CAP2P, CAP3P and VOUT. Leave CAP2N open. 3X step-up To produce voltage level in the positive direction at the Vout terminal that is 3 times the voltage difference between VSS and 2. Please configure set voltage circuits like this. Place a uf~2.2uf capacitor between CAPN and CAPP. Place a uf~2.2uf capacitor between VSS and VOUT. Place a uf~2.2uf capacitor and 00 ohms resistor between CAP2N and CAP2P. Short CAP3P and Vout. 4X step-up To produce voltage level in the positive direction at the Vout terminal that is 4 times the voltage difference between VSS and 2. Please configure set voltage circuits like this. Place a uf~2.2uf capacitor between CAPN and CAPP. Place a uf~2.2uf capacitor between VSS and VOUT. Place a uf~2.2uf capacitor and 00 ohms resistor between CAP2N and CAP2P. Place a uf~2.2uf capacitor and 00 ohms resistor between CAPN and CAP3P. 29

30 ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit Power supply voltage -0.3 to +7.0 V LCD driver voltage Vout 0 to +7 V Input voltage VIN -0.3 to +0.3 V Operating temperature TA -40 to +85 Storage temperature TSTO -55 to +25 DC CHARACTERISTICS Item Symbol Condition Unless otherwise specified, Vss=0V, =3.0V Rating Min. Typ. Max. Unit Applicable Pin Operating Voltage V * Step up output voltage Vout (Relative to ) 0-7 V Vout Voltage follower circuit operating Voltage (Relative to ) 0-5 V accuracy % High-level Input Voltage Low-level Input Voltage VIHC VILC Vss V *2 High-level Output Voltage Low-level Output Voltage VOHC VOLC IOH = 0.5 ma IOL = 0.5 ma 0.8 Vss V *3 Input leakage current ILI VIN = or VSS ua *4 Output leakage current ILO - - ua *5 Liquid Crystal Driver ON Resistance Oscillator Frequency Oscillator Frequency Internal Oscillator External Input RECOMMAND Internal Oscillator External Input RECOMMAND RON Ta= 25 C (Relative To ) =5 V KΩ fosc Ta = 25 C fcl /32Duty fosc Ta = 25 C fcl /64Duty Dynamic Consumption Current, During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used. 30 khz khz SEGn COMn *6 CL CL

31 Display Pattern OFF Item Symbol Condition Rating Min. Typ. Max. RW065 IDD =3.0 V, -Vss=8V =5.0 V, -Vss=8V Display Pattern Checker Item Symbol Condition Rating Min. Typ. Max. RW065 IDD =3.0 V, -Vss=8V =5.0 V, -Vss=8V Display Pattern OFF Item Symbol Condition Rating Min. Typ. Max. RW065 IDD =3.0 V, -Vss=8V =5.0 V, -Vss=8V Display pattern Checker Rating Item Symbol Condition Min. Typ. Max. =3.0 V, -Vss=8V RW065 IDD =5.0 V, -Vss=8V Ta = 25 C Vout=7V Unit Notes µa *7 Ta = 25 C Vout=7V Unit Notes µa *7 Ta = 25 C Vout=7V Unit Notes µa *7 Ta = 25 C Vout=7V Unit Notes µa *7 Consumption Current at Time of Power Saver Mode, VSS = 0 V, = 3.0 V ± 0% Rating Item Symbol Condition Unit Notes Min. Typ. Max. Sleep mode IDD µa - References for items market with * * While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The RS, D0 to D5, D6, D7, E, RW, CSBP, CS2P, CLS, CL, FR, M/S, and RST terminals. *3 The D0 to D7, FR and CL terminals. *4 The RS, E, RW, CSBP, CS2P, CLS, M/S, and RST terminals. *5 Applies when the D0 to D5, D6, D7, CL, and FR terminals are in a high impedance state. *6 These are the resistance values for when a 0. V voltage is applied between the output terminals SEGn or COMn and the various power supply terminals (V, V2, V3, and V4). These are specified for the operating voltage (3) range. RON = 0. V / I (Where I is the current that flows when 0. V is applied while the power supply is ON.) *7 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. 3

32 TIMING CHARACTERISTICS 68 Interface Item Signal Symbol Condition (Ta=-40 to 85 C) =2.7 to 4.5V Rating =4.5 to 5.5V Rating Units Min. Max. Min. Max. Address hold time RS tah6 0 0 Address setup time RS taw6 0 0 System cycle time RS tcyc ns Data setup time D0 to D7 tds Data hold time D0 to D7 tdh6 0 0 Access time D0 to D7 tacc CL = 00 pf Output disable time D0 to D7 toh Enable H pulse time Read tewhr E Write tewhw ns ns ns ns Enable L pulse time Read E tewlr Write tewlw * All timing is specified using 20% and 80% of as the reference. *2 tewlw and tewlr are specified as the overlap between CSBP being L (CS2P = H ) and E. ns 32

33 Reset Timing Item Signal Symbol Condition Rating Min. Typ. Max. Units Reset time tr - 2 µs Reset L pulse width RST trw 2 - µs * When double chip was be used, then the duty set command must be set between the tr 33

34 I/O PAD CONFIGURATION 34

35 THE MPU INTERFACE (REFERENCE EXAMPLES) The RW065 Series can be connected to 6800 Series MPUs. The display area can be enlarged by using multiple RW065 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access Series MPUs RW

36 When using external multi-level power supply for LCD driving (REFERENCE EXAMPLE) Using a resistor divider can provide RW065 external multi-level power supply for LCD driving. The circuit below shows a resistor divider network, which can bias, V, V2, V3, and V4 externally 36

37 Because pins can not set LCD bias when external power supplies are used for LCD driving, the bias can be set by an appropriate configuration for a resistor voltage divider networks. The example is shown below. R R N*R R R RV RV2 RV3 RV4 Bias Network Circuit Concept /5 Bias: N=, total = 5R /6 Bias: N=2, total =6R /8 Bias: N=4, total =8R /9 Bias: N=5, total = 9R VSS When, V, V2, V3, and V4 are biased by external power supply, analog section of RW065 should be turn off by software during LCD initialization. The example in below shows the sequence to turn off analog section when external bias is used. Begin of LCD initialization. Reset RW SET EXT= (mode instruction) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB SET Display Command (double command) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB SET EXT= (mode instruction) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB End of LCD initialization 37

38 Single chip solution for RW065 application (REFERENCE EXAMPLE) For a 64x32 application, the duty cycle of LCD panel is /64 and the display duty of RW065 should be set to /64. The display duty cycle can be selected by the DUTY bit in display command. The diagram for 64x32 application is shown below. 64 SEGx32COM LCD Panel /64 duty cycle COM~33 SEG~65 RW065 DUTY= 38

39 Using an adjustable resistor on the main board to adjust the contrast of liquid crystal display (REFERENCE EXAMPLE) The schematic shows an adjustable resistor on main board that can adjust voltage level of. 39

40 Package information: (Please pay close attention to the information in this section. Do not hesitate to consult with our sale representative, if you have any question or concern.) In order to make better bonding yield for RW065; please follow the tips and recommendations in this section. In this section, few tips about COB footprint style, PCB layout, and wire bonding will be discussed. The drawing in below shows the PCB footprint style, which we recommend for RW065. Pads array in curve shape is easier for Al wire bonding. Besides that, a real size COB footprint for RW065 is also shown in below. RW065 COB footprint is also available in powerpcb or protel format for design reference purpose. The ratio is : 40

41 During COB footprint design, there have some tips about footprint that the PCB designer should know. The angle between bonding wire and vertical line should less than 45. Otherwise, the wire shorts would become very easy to happen at fours corners of the chip. Bad! Wires are too close to each other. Wires are not too close to each other. The angle between bonding wire and vertical line is greater than 45 The angle between bonding wire and vertical line is less than 45 The angle between bonding wire and vertical line could be reduced by expanding the distance between pads array and the chip. In addition, reducing length in horizon direction of pads array could minimize the angle between bonding wire and vertical line. The picture in below will help to illustrate this concept. From the experiences, COB footprint style affects the bonding yield. The angle between bonding wire and vertical line could be reduced by expanding the distance between pads array and the chip. Reducing length in horizon direction of pads array could minimize the angle between bonding wire and vertical line. 4

42 If the gap between pads of COB footprint is filled with solder mask coating, it is difficult to bond Al wire to the pads. The top solder masks layer that overlap COB footprint area should be removed. Please use mils diameter Al wire for RW065 wire bonding. 42

43 D C B A C6 2.2uf OPTION R7 200K/0603 R8 300R/0603 R 0R/0603 CAP Value:UF~2.2UF R2 00R/0603 C7 CAP C8 CAP R3 0R/0603 R4 00R/0603 C9 CAP C0 2.2uf R20 00k/0603 C 2.2uf C2 2.2uf R2 00k/0603 C3 2.2uf RB RES VRAB RA RES C4 2.2uf R9 00R R5 0R R6 300R ADC R8 NC R9 00R/0603 SHL R0 R NC 00R/0603 BS0 BS0 BS Bias 0 0 /5 bias 0 0 /6 bias /8 bias /9 bias 2X:Put C6 C8, Short R R3,Open R2 R4 C7 C9 3X:Put C6 C8 C9 R4,Short R,Open R2 R3 C7 4X:Open R R3 R7 RES R2 00R/0603 R4 00R/0603 R3 NC R5 NC ADC=0: SEG0<~column address 00H,normal(default) ADC=: SEG0<~column address 3FH,inverted SHL=0: Normal COM0~>COM63(default) SHL=: Reverse direction COM63~>COM0 if use single chip for 32 command display,the display command must select /64 duty Display panel must select /64 duty type R6 C5 00R/ uf/0603 DB[0:7] C 0 0.uf COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM20 COM2 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM3 RW CLL CLL 84 ADC ADCP 83 SEG0 82 SEG 8 SEG2 80 SEG3 79 SEG4 78 SEG5 77 SEG6 76 SEG7 75 SEG8 74 SEG9 73 SEG0 72 SEG 7 SEG2 70 SEG3 Title Size C Number Revision Date: 29-Aug-2007 Sheet of File: D:\ 公司資料 \99se\MyDesign.ddb Drawn By: D C B A 20 SEG63 2 SEG62 22 SEG6 23 SEG60 24 SEG59 25 SEG58 26 SEG57 27 SEG56 28 SEG55 29 SEG54 30 SEG53 3 SEG52 32 SEG5 33 SEG50 34 SEG49 35 SEG48 36 SEG47 37 SEG46 38 SEG45 39 SEG44 40 SEG43 4 SEG42 42 SEG4 43 SEG40 44 SEG39 45 SEG38 46 SEG37 47 SEG36 48 SEG35 49 SEG34 50 SEG33 5 SEG32 52 SEG3 53 SEG30 54 SEG29 55 SEG28 56 SEG27 57 SEG26 58 SEG25 59 SEG24 60 SEG23 6 SEG22 62 SEG2 63 SEG20 64 SEG9 65 SEG8 66 SEG7 67 SEG6 68 SEG5 69 SEG4 COM2 COM COM0 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM0 V V4 V2 V3 VRAB VOUT CAP3P CAPN CAPP CAP2P CAP2N 2 SHLP BS0P BSP MSP FRR CLSP RSTP RWRP AOP(RS) ERDP CS2P CSBP D7 D6 D5 D4 D3 D2 D D0 VSS RW RS E CS2P CSB D0 D D2 D3 D4 D5 D6 D7 J CS VSS_IN _IN R28 0R R29 0R R30 0R R3 0R R32 0R 0 R33 0R R34 0R 2 R35 0R 3 R36 0R 4 R37 0R 5 R38 0R 6 VADJ 7 A 8 K 9 20 CON x902 um RW065 IC SHL=0 ADC=0 COM0-3 SEG0-63 SHL= COM3-0 ADC= SEG63-0 LCD PANEL 64X32 RockWorks RW065 64X32 B VOUT C3P CN CP C2P C2N 2 BS V V4 V2 V3 VRAB VOUT C3P CN CP C2P C2N 2 SHL BS0 BS FRR RSTP V V2 V3 V4 VADJ RA2 RES CS R22 0R CSBP R23 RES CS R24 CS2P R25 RES 0R 鐵框地 FGND R26 22R/0603 RS D C0 RW DIODE E 4.7uf D0 D R27 D2 22R/0603 D3 D4 D5 D6 R39 D7 5K/0603 RSTP C2 0.uf/0603 VSS

44 D C B A R 0R/0603 R2 00R/0603 C7 CAP C8 CAP R3 0R/0603 R4 00R/0603 C9 CAP C0 2.2uf C 2.2uf C2 2.2uf R23 00k/0603 C3 2.2uf RB RES RA RES C4 2.2uf R5 0R/0603 R6 300R/0603 R7 RES ADC R8 NC R9 00R/0603 ADC2 R0 R NC 00R/0603 SHL R2 R3 NC 00R/0603 R4 00R/0603 R6 00R/0603 R5 NC R7 NC DB[0:7] DB[0:7] IC COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM20 COM2 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM3 RW065 CLL ADCP SEG0 SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG0 SEG SEG2 SEG Title Size C Number Revision Date: 29-Aug-2007 Sheet of File: D:\ 公司資料 \99se\MyDesign.ddb Drawn By: D C B A COM2 COM COM0 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM0 V V4 V2 V3 VRAB VOUT CAP3P CAPN CAPP CAP2P CAP2N 2 SHLP BS0P BSP MSP FRR CLSP RSTP RWRP AOP(RS) ERDP CS2P CSBP D7 D6 D5 D4 D3 D2 D D0 VSS 4897x902 um COM2 0 Master COM22 RW065 Slave COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM20 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM3 85 CLL CLL 84 ADC2 ADCP 83 SEG0 82 SEG 8 SEG2 80 SEG3 79 SEG4 78 SEG5 77 SEG6 76 SEG7 75 SEG8 74 SEG9 73 SEG0 72 SEG 7 SEG2 70 SEG3 RW065 Master SEG63 SEG62 SEG6 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG5 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG4 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG3 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG2 SEG20 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG63 SEG62 SEG6 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG5 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG4 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG3 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG2 SEG20 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 COM2 COM COM0 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM0 V V4 V2 V3 VRAB VOUT CAP3P CAPN CAPP CAP2P CAP2N 2 SHLP BS0P BSP MSP FRR CLSP RSTP RWRP AOP(RS) ERDP CS2P CSBP D7 D6 D5 D4 D3 D2 D D0 VSS RW RS E IC_CS2P IC_CSBP RW RS E IC2_CS2P IC2_CSBP D0 D D2 D3 D4 D5 D6 D7 VSS VSS D0 D D2 D3 D4 D5 D6 D7 J CON20 OPTION R9 200K/0603 R20 C6 2.2uf 300R/0603 CAP Value:UF~2.2UF 2X:Put C6 C8, Short R R3,Open R2 R4 C7 C9 3X:Put C6 C8 C9 R4,Short R,Open R2 R3 C7 4X:Open R R3 R22 00k/0603 VRAB 2 BS0 BS BS0 BS Bias 0 0 /5 bias 0 0 /6 bias /8 bias /9 bias ADC=0: SEG0<~column address 00H,normal(default) ADC=: SEG0<~column address 3FH,inverted SHL=0: Normal COM0~>COM63(default) SHL=: Reverse direction COM63~>COM0 Both Master and Slave should set identical SHL value C 0.uf/0603 C0 R8 CS IC_CSBP CS2 IC2_CSBP 00R/0603 R24 0R R25 RES R28 0R R29 RES 0.uf/0603 IC2 4897x902 um RW065 Slave SHL=0 SHL=0 Master: COM0-3 Slave: COM32-63 SHL= SHL= Master: COM63-32 Slave: COM3-0 ADC=0 ADC=0 Master: SEG0-63 Slave: SEG64-27 ADC= ADC= Master: SEG63-0 Slave: SEG27-64 LCD PANEL 28X64 RockWorks RW065 28x VOUT C3P CN CP C2P C2N V V2 V3 V4 RA2 RES VADJ R2 00R CS IC_CS2P R26 RES R27 0R CS2 IC2_CS2P R30 RES R3 0R V V4 V2 V3 VRAB VOUT C3P CN CP C2P C2N 2 SHL BS0 BS FRR RSTP V V4 V2 V3 VRAB VOUT 2 SHL BS0 BS FRR RSTP CLL ADC 鐵框地 FGND CS R32 VSS CS2 VSS_IN 22R/0603 _IN D C0 C R34 0R RS DIODE RW 0.uf R35 0R 4.7uf R36 0R E R37 0R D0 R33 R38 0R D D2 22R/0603 R39 0R R40 0R D3 R4 0R D4 R42 0R D5 R45 R43 0R D6 5K/0603 R44 0R D7 VADJ A RSTP K C5 0.uF/0603 B