Design and Implementation of LED Display Screen Controller based on STM32 and FPGA Chi Zhang 1,a, Xiaoguang Wu 1,b and Chengjun Zhang 1,c

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1 Applied Mechanics and Materials Online: ISSN: , Vols , pp doi: / Trans Tech Publications, Switzerland Design and Implementation of LED Display Screen Controller based on STM32 and FPGA Chi Zhang 1,a, Xiaoguang Wu 1,b and Chengjun Zhang 1,c 1 School of Mechanical & Automation Engineering, Wuhan Textile University, Wuhan China a betazhang13@sina.com, b jdky@wtu.edu.cn, c @qq.com Keywords: LED display; FPGA; STM32; Ping-Pong operation; TM1809 Abstract. In order to realize point-light-source and hurdle lamp LED displays system, a kind of LED display screen controller design based on FPGA and STM32 is introduced by this paper. This design can quickly and easily receive display the data from USB, Ethernet and SD card interfaces through the STM32 processor, and use FPGA to realize data transmission throughput big operation of stable display by double RAM Ping-Pong operation This paper gives drive unit timing for TM1809 series LED drive chip as typical case. This design has applied to LED display controller with stability of reading data and excellent performance. Introduction The LED display is assembled with pixel modules. The input pulse current to pins of every pixel module is controlled by the computer to change the LED brightness. Change the duty cycle to generate brightness gray scale, then a pixel will changes into a variety of colors. A large quantity of such pixels can combine into image, such as that is displayed by televisions, monitors, showing texts and graphics. Common LED displays include: outdoor true color displays, indoor graphic displays, point-light-source displays, and hurdle lamp displays [1]. Point-light-source and hurdle lamp displays are commonly used in large-size advertising, building lighting, and can be in irregular shapes. The space between every two display modules is far, and the display resolution is slightly lower than the outdoor true color screen. The technical standards are not uniform currently, and there are a wide range of drives in different properties. The controller of point-light-source and hurdle lamp LED displays, commonly based on a single-chip microcontroller as the core, with extension of external mass storage such as CF card, SD card and U disk, often drives display units or sub-controllers [2-3] via SPI bus, RS232/485 bus. Using SCM is low in cost, but it can only drive one LED display unit due to the performance limitations of SCM, so the data throughput is low. This program, by using the STM32 processor [4], acquires display data by a convenient, quick and high-speed method via interfaces of USB, Ethernet and SD card, in order to achieve the hardware integration enabling various working ways. Through the Ping-Pong operation of the FPGA to double-ram, it realizes the stable display under data transmission of large throughput, which can read and write separately. The FPAG is designed to be built with multiple driving protocols to be compatible to all kinds of point-light-source and hurdle lamp drive units on the market. Hardware Architecture Design STM32 system processor, using Cortex-M3 kernel, the most advanced ARM architecture, with excellent real-time performance, outstanding power control and the largest extent of integration, is easy for development, making the product launch market quickly. The USB interface is the most convenient and fastest interface method for PC peripherals extension; 100M Ethernet interface is All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-09/05/16,01:30:34)

2 Applied Mechanics and Materials Vols for remote access of PC data transmission; SD card interface is an interface mode for traditional LED display control. Using STM32 processor can achieve the above three interfaces in a convenient and efficient way at a lower cost. After receiving the drive data (or reading from the SD card), CPU immediately write it to external RAM, and RAM read/write time is only 10-25ns, thus greatly improving the work efficiency of the CPU. FPGA's function is to receive the data from CPU and store it into RAM, in the meantime, to read out data from RAM and send as drive requirements. The Ping-Pong operation is characterized by switching the input data selection unit and output data selection unit with the beat coordinately, to transmit the data stream passing through the buffer to data stream computing and processing modules continuously for computing and processing. Regarding Ping-Pong operation module as a whole, through the observation the data at both ends of this module, it will be found that the input data stream and the output data stream are both continuous, making it ideal for pipelined processing of the data stream. Therefore, Ping-Pong operation is often used in the pipelined algorithm to implement continuous data buffering and processing. The Ping-Pong operation to RAM can read and write independently, and achieve the steady display under the transmission of a great data throughput. The controller hardware structure of this program is shown in Fig. 1. Fig.1. Electrical diagram of STM32 and FPAG controller It can be seen from Fig. 1 that STM32 obtains data via the USB, two SPI interfaces and serial interface, and is connected to FPAG by the 16-bit address bus and the 8-bit data bus. FPGA works under the system clock of 100MHz, implement the double RAMs Ping-Pong operation, and drive the 8-channel light board in a parallel way according to the timing requirements of drive light board. The data transmission speed of FPGA driving a single LED control unit is 1M bit/sec. A 32K-byte static RAM can store the RGB data for up to 10,920 point light source ( array), that is 1,365 RGB point per channel. FPGA transmission time is less than the refresh cycle of 40ms at the rate of 25 frames/second, therefore it meets the design requirements.

1580 Materials, Mechanical Engineering and Manufacture FPGA Modules Design and Simulation In this program, STM32 acquires control data via one of the three interfaces and then writes to the FPGA.

Fig.2. FPGA system function block diagram Design and simulation of transmission timing generation module.

3 1580 Materials, Mechanical Engineering and Manufacture FPGA Modules Design and Simulation In this program, STM32 acquires control data via one of the three interfaces and then writes to the FPGA. Double RAMs Ping-Pong operation and the lamp board driving timing are implemented by the FPGA. The basic functions of the FPGA to realize above features are shown in Fig. 2. Fig.2. FPGA system function block diagram Design and simulation of transmission timing generation module. FPGA have an advantage on the operation of parallel events, but as to implement the operations of complex loop, selection, waiting, the timing module should be designed according to the procedure steps or and circulation process. The work to be done by transmission timing generation module of this design is to generate the address signal (addr), address of reading RAM according to timing; latch the readout data into the specified port (BUFFER), and generate latch signal (latch) according to the timing. When the controller is driving 8 lamp boards in parallel, it is necessary to generate a start signal of serial output (wr_sig) after read out 8 bytes of data; wait according to the busy signal (busy) of serial transmission module; then determine the end according to the setting value of drive data length latch module at the transition of the Ping-Pong operation. At each transition of Ping-Pong operation control signal (wr_rd,), drive mode latch module and drive data length latch module are to latch the type of lamp board and length of data to be transmitted, and latch the data to the internal port. The timeline in the result of the complete timing simulation of the module is too long to show, so the timing diagram of the read timing sub-module simulated by Active-HDL V8.2 is as shown in Fig. 3. In this figure, this module reads out 8 bytes of data under the system clock (clk), sends 8 pulse signal (cntclkout) to the buffer decoder, and sends the data to 8 channel output buffer, and then gives a latch signal (latchclkout) to latch the data, and finally gives the serial output signal (wrclkout), which keeps high level during the serial output process. Fig. 3. Timing simulation of read timing sub-module Design and simulation of double RAMs module. The input of double RAMs Ping-Pong operation module includes: clk_sys (100MHz), system clock; wr_rd, read/write control bit to Ping-Pong operation; addr_write [14:0], address to be written; data_write [7:0], data to be written; addr_read [14:0], address to be read; data_read [7:0], the data to be read. The output includes: addr_a_ram [14:0], the 15-bit address of RAM-A; rd_a_ram and wr_a_ram, read/write control signal of

4 Applied Mechanics and Materials Vols RAM-A; addr_b_ram [14:0], the 15-bit address of RAM-B; addr_a_ram [14:0], the 8-bit address of RAM-B; rd_a_ram and wr_a_ram, read/write control signal of RAM-B. Input and output are IO signals for the two RAMs: data_a_ram [7:0] and data_b_ram [7:0]. When wr_rd is low, it means to write RAM-A and to read RAM-B; when wr_rd is high, it means to read RAM-A and to write RAM-B. The address and data of write operation are from the STM32 processor, and the address of read operation is from the timing generation module. The read out data is sent to the buffer of the transmission module to wait for the latch and output start signal. The internal module structure compiled by Diamond V1.3 (Lattice Semiconductor Corporation), the software developed by Lattice for FPGA design, is shown in Fig. 4. Fig.4. Logical structure of double-ram Ping-Pong operation module The timing diagram of Active-HDL V8.2 simulation is shown in Fig. 5. Fig. 5. Timing simulation of double-ram Ping-Pong operation module ZZ indicates the data not read out from RAM in the timing simulation process. It can be seen from the timing simulation results that the design requirements are satisfied. Design and simulation of 1809 timing transmission module. The 1809 ICs are chips designed by TM in 2010 especially for high-speed drive LED point light source. TM1809 is a 9-channel LED (light-emitting-diode display) drive control integrated circuit; integrating MCU digital interface, data latches, LED high-voltage drive circuit, and can control the luminance of sole brightness dot-matrix of outdoor cascade large-sized color screen via the external MCU. So it is popular when launched on the LED market, and has gained good results in the market application from 2011.

1582 Materials, Mechanical Engineering and Manufacture 1809 Series are 2-wire (DIN, GND) drive type. DIN represents the input of clock signal, and GND represents the ground with the controller.

5 1582 Materials, Mechanical Engineering and Manufacture 1809 Series are 2-wire (DIN, GND) drive type. DIN represents the input of clock signal, and GND represents the ground with the controller. The output gray scale of this series is 256. Since there is no clock signal line, the requirements for DIN timing is strict, as shown in Tabl1 1 [5]. Table low-speed drive time description Code Diagram Name Description Typical value Tolerance 0 1 T0H 0, High level 0.5us ±150ns T1H 0, Low level 2.0us ±150ns TOL 1, High level 2.0us ±150ns T1L 1, Low level 0.5us ±150ns reset Treset Reset, Low level >24us None The simulation of 1809 timing-driven module by Active-HDL V8.2 is shown in Fig. 6. Fig.6. Timing simulation of 1809 timing-driven module Conclusion The program, by using FPGA and STM32 hardware architecture, has promoted the speed of data access and transmission and enhanced the performance of hurdle LED display controller. The hardware interface for data acquisition is compatible with the interfaces of USB, Ethernet and SD card; in the data processing layer, the Ping-Pong operation implemented by FPGA on double RAMs has realized separate read and write, and steady display under data transmission of big throughput; in data-driven layer, the integration of point source and hurdle lamp-driven protocols has achieved the compatibility of the multiple LED display unit. After actual debugging and commissioning, the system works stable and reliable. It is suitable for the similar systems with control requirements, and can be used as reference for development systems with control requirements. Acknowledgements This project is supported by National Natural Science Foundation of China.( Number: ) Reference [1] [2]Xu Zhenfang, Meng Yanhua, Wang Yan. Research on Control System of LED Display Screen Based on AVR[J]. ZHAOMING GONGCHENG XUEBAO,2010,21(4): [3]Zhang Yujie, Ma Liyun, Zhang Heyan. Design of LED-screen Display Control System based on ARM and FPGA[J]. Computer Measurement & Control, 2009,17(12): [4]STM Corporation. STM32103RC product manual [5]TITAN MICRO Corporation. TM1809 product manual

6 Materials, Mechanical Engineering and Manufacture / Design and Implementation of LED Display Screen Controller Based on STM32 and FPGA /

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