Product Specification Industrial 1.8 /2.5 IDE Flash Disk (IDE Solid-State Disk) -MA Series-

Transcription

1 May 2008 Ver. 1.0 Product Specification Industrial 1.8 /2.5 IDE Flash Disk (IDE Solid-State Disk) -MA Series- Doc-No: 100-R8/2IFDMA-01V0

2 This document is for information use only and is subject to change without prior notice. APRO Co., Ltd. assumes no responsibility for any errors that may appear in this document, nor for incidental or consequential damages resulting from the furnishing, performance or use of this material. No part of this document may be reproduced, transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written consent of an officer of APRO Co., Ltd.. All parts of the APRO documentation are protected by copyright law and all rights are reserved. APRO and the APRO logo are registered trademarks of APRO Co., Ltd. Product names mentioned herein are for identification purposes only and may be trademarks and/or registered trademarks of their respective companies APRO Corporation. All rights reserved. Revision History Description Date Revisions before Rev. 1.0 initial release 2008/04/24 16GB C.H.S. value updated Power Requirement updated 2008/05/28

3 CONTENTS CONTENTS 1. INTRODUCTION SCOPE SYSTEM FEATURES ATA/ATAPI-4 STANDARD TECHNOLOGY INDEPENDENCE PRODUCT SPECIFICATIONS SYSTEM ENVIRONMENTAL SPECIFICATIONS SYSTEM POWER REQUIREMENTS SYSTEM PERFORMANCE SYSTEM RELIABILITY PHYSICAL SPECIFICATIONS CAPACITY SPECIFICATIONS INTERFACE DESCRIPTION INDUSTRIAL RUGGED 1.8 /2.5 IDE FLASH DISK INTERFACE PIN ASSIGNMENTS ELECTRICAL DESCRIPTION ELECTRICAL SPECIFICATION GENERAL DC CHARACTERISTICS INTERFACE I/O AT 5.0V INTERFACE I/O AT 3.3V AC CHARACTERISTICS i APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd.

4 CONTENTS ATTRIBUTE MEMORY READ TIMING CONFIGURATION REGISTER (ATTRIBUTE MEMORY) WRITE TIME COMMON MEMORY WRITE TIMING I/O READ TIMING I/O WRITE TIMING TRUE IDE PIO MODE READ/WRITE TIMING TRUE IDE MULTIWORD DMA MODE READ/WRITE TIMING ULTRA DMA SIGNAL IN EACH INTERFACE MODE ULTRA DMA DATA BURST TIMING REQUIREMENT ULTRA DMA DATA BURST TIMING DESCRIPTIONS ULTRA DMA SENDER AND RECIPIENT IC TIMING REQUIREMENTS ULTRA DMA AC SIGNAL REQUIREMENTS ULTRA DMA DATA-IN BURST INITIATION TIMING SUSTAINED ULTRA DMA DATA-IN BURST TIMING ULTRA DMA DATA-IN BURST HOST PAUSE TIMING ULTRA DMA DATA-IN BURST DEVICE TERMINATION TIMING ULTRA DMA DATA-IN BURST HOST TERMINATION TIMING ULTRA DMA DATA-OUT BURST HOST INITIATION TIMING SUSTAINED ULTRA DMA DATA-OUT BURST HOST INITIATION TIMING ULTRA DMA DATA-OUT BURST DEVICE PAUSE TIMING ULTRA DMA DATA-OUT BURST DEVICE TERMINATION TIMING ULTRA DMA DATA-OUT BURST HOST TERMINATION TIMING INTERFACE REGISTER DEFINITION DEVICE ADDRESS ii APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd.

5 CONTENTS 5.2. I/O REGISTER DESCRIPTIONS SOFTWARE SPECIFICATION ATA COMMAND SET ATA COMMAND DESCRIPTION S.M.A.R.T COMMAND SUPPORT SMART FEATURE REGISTER VALUES SMART DATA STRUCTURE ( READ DATA (DOH)) EXECUTION OF THE SMART FUNCTION ID TABLE INFORMATION INSTALLATION PROCEDURE BEFORE UNPACKING ESD PRECAUTIONS MASTER/SLAVE/CABLE SELECTING SETTING PIN IDE CABLE & CABLE INSERTION MOUNTING IDE DEVICE SETUP / AUTO-DETECTION PARTITION & FORMAT APPENDIX A. ORDERING INFORMATION APPENDIX B. LIMITED WARRANTY APPENDIX C. AFTER SERVICE iii APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd.

6 CONTENTS Preliminary Specification iv APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd.

7 1. Introduction APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series designed to follow ATAPI-4 (ATA-66) standard. The main used Flash memories are Samsung NAND Type SLC Flash memory chips. The available Disk capacities are 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB and 16GB. The operating temperature grade is optional for commercial level 0 C ~ 70 C and wide temperature level -40 C ~ +85 C. The APRO Industrial Rugged 1.8 /2.5 IDE Flash Disks are designed electrically complies with the conventional IDE hard Card and support True IDE Mode. The data transfer modes supports PIO mode 0, 1, 2, 3, and 4 or UDMA- 0, 1, 2, 3, and 4. The fastest reading speed is up to 45 MB/sec and writing speed is up to 34.0 MB/sec, The APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk products provide a high level interface to the host computer. This interface allows a host computer to issue commands to the Rugged 1.8 /2.5 IDE Flash Disk to read or write blocks of memory. Each sector is protected by a powerful 4 bits Error Correcting Code (ECC). APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA-Series intelligent controller manages interface protocols, data storage and retrieval as well as ECC, defect handling and diagnostics, power management and clock control. Figure 1 shows a block diagram of the used high tech Industrial Rugged 1.8 /2.5 IDE Flash Disk controller. Figure 1: Industrial Rugged 1.8 /2.5 IDE Flash Disk MA-Series Controller Block Diagram APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 1

8 1.1. Scope This document describes the features and specifications and installation guide of APRO s Industrial Rugged 1.8 /2.5 IDE Flash Disks MA Series. In the appendix, there provides order information, warranty policy, RMA/DOA procedure for the most convenient reference System Features Standard 2.5 HDD form-factor and 1.8 form-factor Compliant to ATA/ATAPI-4 specification Non-volatile memory and no moving parts NAND type SLC flash technology Support standard SMART function Card capacity from 128MB to 32GB ATA inter face 100% support True IDE mode Data transfer supports PIO- 4 and UDMA- 4 Performance up to 45 MB/sec Automatic 4 bits error correction (ECC ) and retry capabilities +5 V ±10% or +3.3 V ±5% operation MTBF > 1,000,000 hours. Shock : 1,500G, compliance to MIL-STD-810 Vibration : 15G, compliance to MIL-STD-810 Rugged environment is working well Very high performance, very low power consumption Low weight, Noiseless 1.3. ATA/ATAPI-4 Standard APRO Industrial Rugged 1.8 /2.5 IDE Flash Disks MA Series is compliant to ATA/ATAPI-4 and below version Technology Independence With the proprietary method to manage variable kinds of flash in terms of wear-leveling and ECC (Error Code Correction), it translate the ATA control, address and data bus signals into the management unit of NAND type flash devices and constitute the Rugged 1.8 /2.5 IDE Flash Disks more ideal than the conventional hard Card drives. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 2

9 2. Product Specifications For all the following specifications, values are defined at ambient temperature and nominal supply voltage unless otherwise stated System Environmental Specifications Table 1: Environmental Specification Commercial Grade APRO Industrial Rugged 1.8 /2.5 IDE SR8/2IFDxxxM-ACSC Flash Disk- MA Series Series Temperature Operating: 0ºC ~ +70ºC Non-operating: -20ºC ~ +80ºC Humidity Operating & Non-operating: 5% ~ 95% non-condensing Vibration Operating & Non-operating: 15 G peak-to-peak maximum Shock Operating & Non-operating: 1,500 G maximum Industrial Grade WR8/2IFDxxxM-AISI Series -40ºC ~ +85ºC -50ºC ~ +95ºC 2.2. System Power Requirements Table 2: Power Requirement APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk- MA Series DC Input Voltage (VCC) 100mV max. ripple(p-p) Reading Mode : +5V Current Writing Mode : (Maximum average value) Stand By Mode : Commercial Grade Industrial Grade SR8/2IFDxxxM-ACSC WR8/2IFDxxxM-AISI Series Series 5V±10% 56.5 ma (max.) ma (max.) 1.4 ma (max.) 2.3. System Performance Data Transfer Mode supporting Data Transfer Rate To/From Host Average Access Time Maximum Performance Table 3: System Performances - PIO mode : 0, 1, 2, 3, 4, (PIO 4 defaulted) - DMA SW Mode: Not supported - DMA MW Mode:0,1,2, 3 and 4 - UDMA Mode: 0,1,2,3, and Mybtes/sec burst under PIO Mode Mbytes/sec burst under UDMA-4 Mode 0.6 ms(estimated) Capacity 128MB 256MB 512MB 1GB 2GB 4GB 8GB 16GB Sequential PIO TBC Read (MB/s) UDMA TBC Sequential PIO TBC Write(MB/s) UDMA TBC The number of Channel Single Dual Single Single Dual Dual Dual TBC Note: (1). All values quoted are typically at 25 and nominal supply voltage. (2). Testing of the Industrial Rugged 1.8 /2.5 IDE Flash Disk maximum performance was performed under the following platform: - Computer with AMD 3.0GHz processor - Windows XP Professional operating system APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 3

10 2.4. System Reliability MTBF Data Reliability Wear-leveling Algorithms ECC Technology Endurance Data Retention Table 4: System Reliability >1000,000 hours <1 non-recoverable error in bits read <1 erroneous correction in bits read Supportive 4 bits Error Connection Code Greater than 2,000,000 cycles Logically contributed by Wear-leveling and advanced bad sector management 10 years APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 4

11 2.5. Physical Specifications Refer to Table 5 and see Figure 3 for Industrial Rugged 1.8 /2.5 IDE Flash Disk MA-Series physical specifications and dimensions. Table 5: Physical Specifications of Industrial Rugged 1.8 IDE Flash Disk-MA Series Length: 60.50±0.25mm(3.94±0.010 in) Width: 70.00±0.25mm(2.76± in) Thickness: 9.50±0.25mm(0.37±0.010 in) Weight: 70g (2.4oz) Figure 2: Rugged 1.8 IDE Flash Disk Dimension APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 5

12 Table 6: Physical Specifications of Industrial Rugged 2.5 IDE Flash Disk-MA Series Length: ±0.25mm(3.94±0.010 in) Width: 70.00±0.25mm(2.76± in) Thickness: 9.50mm±0.25mm(0.37±0.010 in) Weight: 110g (3.8oz) Figure 3: Rugged 2.5 IDE Flash Disk Dimension APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 6

13 2.6. Capacity Specifications APRO Industrial Rugged 1.8 /2.5 IDE Flash Disks are built-in mainly Samsung NAND Type SLC Flash memory chips. The Table 7 shows the equipollent part number of applied Samsung Flash memory chips for each card. Card Capacity 128MB 256MB 512MB 1GB 2GB 4GB 8GB 16GB 32GB Table 7: Card Configuration vs. Samsung NAND SLC part number Samsung SLC Flash Memory Part Number * Q TY Commercial Grade: K9F1G08U0A-PCB0(1Gb) or equipollent * 1 Industrial Grade: K9F1G08U0A-PIB0 (1Gb) or equipollent * 1 Commercial Grade: K9F2G08U0A-PCB0 (2Gb) or equipollent * 1 K9F1G08U0A-PCB0(1Gb) or equipollent * 2 Industrial Grade: K9F2G08U0A-PIB0 (2Gb) or equipollent * 1 K9F1G08U0A-PIB0 (1Gb) or equipollent * 2 Commercial Grade: K9F4G08U0M-PCB0 (4Gb) or equipollent * 1 K9F2G08U0A-PCB0 (2Gb) or equipollent * 2 K9F1G08U0A-PCB0(1Gb) or equipollent * 4 Industrial Grade: K9F4G08U0M-PIB0 (4Gb) or equipollent * 1 K9F2G08U0A-PIB0 (2Gb) or equipollent * 2 K9F1G08U0A-PIB0 (1Gb) or equipollent * 4 Commercial Grade: K9K8G08U0M-PCB0 (8Gb) or equipollent * 1 K9F4G08U0M-PCB0 (4Gb) or equipollent * 2 Industrial Grade: K9K8G08U0M-PIB0 (8Gb) or equipollent * 1 K9F4G08U0M-PIB0 (4Gb) or equipollent * 2 Commercial Grade: K9WAG08U1M-PCB0 (16Gb) or equipollent *1 K9K8G08U0M-PCB0 (8Gb) or equipollent *2 Industrial Grade: K9WAG08U1M-PIB0 (16Gb) or equipollent *1 K9K8G08U0M-PIB0 (8Gb) or equipollent *2 Commercial Grade: K9WAG08U1M-PCB0 (16Gb) or equipollent *2 K9K8G08U0M-PCB0 (8Gb) or equipollent *4 Industrial Grade: K9WAG08U1M-PIB0 (16Gb) or equipollent *2 K9K8G08U0M-PIB0 (8Gb) or equipollent *4 Commercial Grade: K9WAG08U1M-PCB0 (16Gb) or equipollent *4 Industrial Grade: K9WAG08U1M-PIB0 (16Gb) or equipollent *4 Commercial Grade: K9WBG08U1M-PCB0 or equipollent *4 Industrial Grade: NA Commercial Grade: K9WBG08U1M-PCB0 or equipollent *8 Industrial Grade: NA APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 7

14 The table 8 shows the specific capacity for the various models and the default number of heads, sectors/track and cylinders. Table 8: Model Capacity Unformatted Default Default Default CHS Default Sector Capacity Cylinder Head Capacity 128MB ,328, MB ,739, MB ,690,432 1,024MB 1, ,017,954, GB 3, ,037,219,328 4GB 7, ,075,061,248 8GB 15, ,150,712,320 16GB 33, ,302,768,128 APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 8

15 3. Interface Description 3.1. Industrial Rugged 1.8 /2.5 IDE Flash Disk interface The pin 1 ~ pin 44 are for IDE interface. The pin A ~ pin D are for option selection via physical jumpers. Figure 4: The front view of Rugged 1.8 & 2.5 IDE Flash Disk with 44-pin IDE Connector 3.2. Pin Assignments Signals whose source is the host is designated as inputs while signals that the Industrial R8/2IFD sources are outputs. The pin assignments are listed in below table 9. Pin No. Signal Name Table 9: Pin Assignments Pin Description Pin Name No. Description 1 RESET- Drive Reset 2 GND -- 3 DD7 Drive data bus bit 7 4 DD8 Drive data bus bit 8 5 DD6 Drive data bus bit 6 6 DD9 Drive data bus bit 9 7 DD5 Drive data bus bit 5 8 DD10 Drive data bus bit 10 9 DD4 Drive data bus bit 4 10 DD11 Drive data bus bit DD3 Drive data bus bit 3 12 DD12 Drive data bus bit DD2 Drive data bus bit 2 14 DD13 Drive data bus bit DD1 Drive data bus bit 1 16 DD14 Drive data bus bit DD0 Drive data bus bit 0 18 DD15 Drive data bus bit GND Ground 20 KEY No pin 21 DMARQ DMA request 22 GND Ground 23 DIOW- Drive I/O Write 24 GND Ground 25 DIOR- Drive I/O Read 26 GND Ground 27 IORDY I/O channel ready 28 CSEL Cable select 29 DMACK- DMA acknowledge 30 GND Ground 31 INTRQ Drive interrupt 32 IOCS16- Drive 16 bit I/O 33 DA1 Drive address bus bit 1 34 PDIAG- Passed diagnostics 35 DA0 Drive address bus bit 0 36 DA2 Drive address bus bit 2 37 CS0- Chip select 0 38 CS1- Chip select 1 39 DASP- Drive active/slave present 40 GND Ground 41 VCC +5V supply 42 VCC +5V supply 43 GND Ground 44 RESERVED Reserved for future definition A Option selection pins B Option selection pins C Option selection pins D Option selection pins APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 9

16 3.3. Electrical Description The Industrial Rugged 1.8 / 2.5 IDE Flash Disk- MA Series is optimized for operation with hosts. Table 10: describes the signals of 44-pin interface. Table 10: Signal Description Pin No. Signal Name Type Description CS(1:0) These signals are used to select the Command Block or 37, 38 (Chip Select) Control Block registers. When DMACK is asserted, CS0 I and CS1 shall be negated and transfers shall be 16 bits wide. 33, 35, 36 DA(2:0) This is the 3-bit binary coded address for host to access a I (Device Address) register or data port in this controller. 39 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 DASP (Device active, device 1 present) DD(15:00) (Device Data) DIOR : HDMARDY : HSTROBE I/O I/O During the reset protocol, DASP shall be asserted by Device 1 to indicate that the device is present. Bi-directional data bus. DD(7:0) are used for 8-bit register transfers. DIOR is the strobe signal used by the host to read device registers of the Data port. 25 (I/O Read: Ultra DMA Ready: Ultra DMA Data Strobe) I When Ultra DMA mode DMA Read is active, HDMARDY should be asserted by the host to indicate that the host is ready to receive Ultra DMA data-in bursts DIOW : STOP (I/O Write: Stop Ultra DMA Burst) DMACK (DMA acknowledge) DMARQ (DMA Request) INTRQ (Interrupt) IORDY:DDMARDY:DST ROBE (I/O channel ready: Ultra DMA ready: Ultra DMA data strobe) PDIAG :CBLID (Passed diagnostics: Cable assembly type identifier) RESET (Hardware RESET) CSEL (Cable select) I I O O O I/O I I HSTROBE receives the data-out strobe signal from the host for an UDMA burst. This pin is the strobe signal used by the host to write device registers or the Data port. This signal is used by the host in response to DMARQ to initiate DMA transfers. For DMA data transfers, this controller will assert DMARQ when the controller is ready to transfer data to or from the host. When this device is selected, this signal is the active high Interrupt Request to the host. The controller will assert this signal to indicate that the device is ready to receive Ultra DMA data-out bursts. When Ultra DMA mode DMA Read is active, this signal is the data-in strobe generated by the controller. PDIAG will be asserted by Device 1 to indicate to Device 0 that Device 1 has completed diagnostics. This is the hardware RESET pin from the host. This pin is used to configure this device as Device 0 or Device 1. When this pin is grounded, this device is configured as Device 0; When the pin is High, this device is configured as Device 1. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 10

17 IOCS16 During PIO transfer mode 0, 1 or 2, this pin indicates to the 32 O host that 16-bit data port has be addressed and that the device is prepared to send or receive a 16-bit data word. When transferring in PIO mode 3, 4 or above, this signal should not used by the host, and all transfers will be 16-bit.Whentransferring in DMA mode, the host must use a 16-bit DMA channel and this signal will not be asserted. 02, 19, 22, 24, 26, 30, GND Ground 40, 43 41,42 Vcc Vcc 5V Note: 1) NAME- : It means signal active low. 2) Pin type is Input/Output, Output or Input. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 11

18 4. Electrical Specification Table 11, Table 12, and Table 13 defines all D.C. Characteristics for the Industrial Rugged 1.8 /2.5 IDE Flash Disk. Unless otherwise stated, a condition is as below Table 11: Table 11: Electrical Condition Commercial Grade SR8/2IFDxxxM-ACSC Series Vcc = 5V ±10% Vcc = 3.3V ± 5% Ta = 0 C to 70 C Industrial Grade WR8/2IFDxxxM-AISI Series Vcc = 5V ±10% Vcc = 3.3V ± 5% Ta = -40 C to 85 C 4.1. General DC Characteristics Interface I/O at 5.0V Table 12: Interface I/O at 5.0V Symbol Parameter Min. Max. Units Remark V CC Power Supply V V OH Output Voltage High Level VCC-0.8 V V OL Output Voltage Low Level 0.8 V V IH Input Voltage High Level 2.92 V Schmitt trigger 1 V IL Input Voltage Low Level 1.70 V Schmitt trigger 1 T OPR-W Operating temperature for wide grade T OPR-S Operating temperature for standard grade T STG Storage temperature R PU Pull up resistance kohm R PD Pull down resistance kohm Interface I/O at 3.3V Table 13 Interface I/O at 3.3V Symbol Parameter Min. Max. Units Remark V OH Power Supply V V OL Output Voltage High Level VCC-0.8 V V IH Output Voltage Low Level 0.8 V V IL Input Voltage High Level 2.05 V Schmitt trigger 1 V CC Input Voltage Low Level 1.25 V Schmitt trigger 1 T OPR-W Operating Temperature For Wide Grade T OPR-S Operating Temperature For Standard Grade T STG Storage Temperature R PU Pull up resistance kohm R PD Pull down resistance kohm Notes: 1) Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW pins. 2) Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW, CSEL, PDIAG, DASP pins. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 12

19 Figure 5: Interface I/O Voltage Diagram 4.2. AC Characteristics Attribute Memory Read Timing Table 14: Attribute Memory Read Timing Speed Version 300 ns Symbol Item Min ns. Max ns. Read Cycle Time tc(r) 300 Address Access Time ta (HA) 300 Card Enable Access Time ta (CEx) 300 Output Enable Access Time ta (HOE) 150 Output Disable Time from CEx tdis (CEx) 100 Output Disable Time from HOE tdis (HOE) 100 Address Setup Time tsu (HA) 30 Output Enable Time from CEx ten (CEx) 5 Output Enable Time from HOE ten (HOE) 5 Data Valid from Address Change tv(ha) 0 Notes: All times are in nanoseconds. HD signifies data provided by the Rugged 1.8 /2.5 IDE Flash Disk to the system. The CEx signal or both the HOE signal and the HWE signal shall be de-asserted between consecutive cycle operations. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 13

20 Figure 6: Attribute Memory Read Timing Diagram Configuration Register (Attribute Memory) Write Time Table 15: Configuration Register (Attribute Memory) Write Time Speed Version Symbol Item Min ns. Write Cycle Time tc(w) 250 Write Pulse Width tw (HWE) 150 Address Setup Time tsu (HA) 30 Write Recovery Time trec (HWE) 30 Data Setup Time for HWE tsu (HD-HWEH) 80 Data Hold Time th (HD) ns Max ns. Notes: All times are in nanoseconds. HD signifies data provided by the system to the Rugged 1.8 /2.5 IDE Flash Disk. Figure 7: Configuration Register (Attribute Memory) Write Timing Diagram APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 14

21 Common Memory Write Timing Table 16: Common Memory Write Timing Cycle Time Mode 250 ns 120 ns 100 ns 80 ns Item Symbol Min Max Min Max Min Max Min Max ns. ns. ns. ns. ns. ns. ns. ns. Output Enable Access Time ta (HOE) Output Disable Time from tdis (HOE) Address Setup Time tsu (HA) Address Hold Time th (HA) CEx Setup before HOE tsu (CEx) CEx Hold following HOE th (CEx) Wait Delay Falling from HOE tv (IORDY-HOE) Na 1 Data Setup for Wait Release tv(iordy) Na 1 Wait Width Time 2 tw(iordy) Na 1 Notes: 1) IORDY is not supported in this mode 2) The Maximum load on IORDY is 1 LSTTL with 50pF (40pF below 120 nsec Cycle Time) total load. All times are in nanoseconds. HD signifies data provided by the Rugged 1.8 /2.5 IDE Flash Disk to the system. The IORDYsignal may be ignored if the HOE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. Figure 8: Common Memory Read Timing Diagram APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 15

22 I/O Read Timing Table 17: I/O Read Timing Cycle Time Mode 250 ns 120 ns 100 ns 80 ns Item Symbol Min Max Min Max Min Max Min Max ns. ns. ns. ns. ns. ns. ns. ns. Data Delay after HIOE td (HIOE) Data Hold following HIOE th (HIOE) HIOE Width Time tw (HIOE) Address Setup before HIOE tsuha (HIOE) Address Hold following HIOE tsuha (HIOE) CEx Setup before HIOE tsucex (HIOE) CEx Hold following HIOE thcex (HIOE) HREG Setup before HIOE tsuhreg(hioe) HREG Hold following HIOE thhreg (HIOE) Wait Delay Falling from HIOE 2 tdlordy(hioe) Na 1 Data Delay from Wait Rising 2 td(iordy) Na 1 Wait Width Time 2 tw(iordy) Na 1 Notes: 1) IORDY is not supported in this mode 2) Maximum load on IORDY is 1 LSTTL with 50pF (40pF below 120 nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from IORDY high to HIOE high is 0 nsec, but minimum HIOE width shall still be met. HD signifies data provided by the Rugged 1.8 /2.5 IDE Flash Disk to the system. Figure 9: I/O Read Timing Diagram APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 16

23 I/O Write Timing Table 18: I/O Write Timing Cycle Time Mode 250 ns 120 ns 100 ns 80 ns Item Symbol Min Max Min Max Min Max Min Max ns. ns. ns. ns. ns. ns. ns. ns. Data Setup before HIOW tsu (HIOW) Data Hold following HIOW th (HIOW) HIOW Width Time tw (HIOW) Address Setup before HIOW tsuha (HIOW) Address Hold following HIOW tsuha (HIOW) CEx Setup before HIOW tsucex (HIOW) CEx Hold following HIOW thcex (HIOW) HREG Setup before HIOW tsuhreg(hiow) HREG Hold following HIOW thhreg (HIOW) Wait Delay Falling from HIOW 2 tdlordy(hiow) Na 1 HIOW High from Wait High 2 tdrhiow(iordy) Na 1 Wait Width Time 2 tw(iordy) Na 1 Notes: 1) IORDY is not supported in this mode 2) The Maximum load on IORDY is 1 LSTTL with 50pF (40pF below 120 nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from IORDY high to HIOW high is 0 nsec, but minimum HIOW width shall still be met. HD signifies data provided by the system to the rugged 1.8 /2.5 IDE Flash Disk. Figure 10: I/O Write Timing Diagram APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 17

24 True IDE PIO Mode Read/Write Timing Table 19: True IDE PIO Mode Read/Write Timing Item Mode Mode Mode Mode Mode t0 Cycle time (min) t1 Address Valid to HIOE/HIOW setup (min) t2 HIOE/HIOW (min) t2 HIOE/HIOW (min) Register (8 bit) t2i HIOE/HIOW recovery time (min) t3 HIOW data setup (min) t4 HIOW data hold (min) t5 HIOE data setup (min) t6 HIOE data hold (min) t6z HIOE data tristate (max) t7 Address valid to IOCS16 assertion (max) n/a n/a t8 Address valid to IOCS16 released (max) n/a n/a t9 HIOE/HIOW to address valid hold trd Read Data Valid to IORDY active (min), if IORDY initially low after ta ta IORDY Setup time tb IORDY Pulse Width (max) tc IORDY assertion to release (max) Notes: All timings are in nanoseconds. The maximum load on IOCS16 is 1 LSTTL with a 50 pf (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from IORDY high to HIOE high is 0 nsec, but minimum HIOE width shall still be met. (1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device s identify device data. (2) This parameter specifies the time from the negation edge of HIOE to the time that the data bus is no longer driven by the device. (3)The delay from the activation of HIOE or HIOW until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device is not driving IORDY negated at ta after the activation of HIOE or HIOW, then t5 shall be met and trd is not applicable. If the device is driving IORDY negated at the time ta after the activation of HIOE or HIOW, then trd shall be met and t5 is not applicable. (4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid. (5) IORDY is not supported in this mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 18

25 Figure 11: True IDE PIO Mode Read/Write Timing Diagram Notes: 1) Device address consists of CE0, CE1, and HA [2:0] 2) Data consist of HD [15:00] ( 16-bit) or HD [7:0] ( 8-bit) 3) IOCS16 is shown for PIO modes 0, 1, and 2. For other modes, this signal is ignored. 4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is to be extended is made by the host after ta from the assertion of HIOE or HIOW. The assertion and negation of IORDY is described in the following three cases: 4-1) Device never negates IORDY: No wait is generated. 4-2) Device drives IORDY low before ta: wait generated. The cycle complete after IORDY is reasserted. For cycles where a wait is generated and HIOE is asserted, the device shall place read data on D15-D00 for trd before causing IORDY to be asserted. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 19

26 True IDE Multiword DMA Mode Read/Write Timing Table 20: True IDE Multiword DMA Mode Read/Write Timing Item Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Note to Cycle time (min) td HIOE / HIOW asserted width (min) te HIOE data access (max) tf HIOE data hold (min) tg HIOE/HIOW data setup (min) th HIOW data hold (min) ti DMACK(HREG) to HIOE/HIOW setup (min) tj HIOE / HIOW to -DMACK hold (min) tkr HIOE negated width (min) tkw HIOW negated width (min) tlr HIOE to DMARQ delay (max) tlw HIOW to DMARQ delay (max) tm CEx valid to HIOE / HIOW tn CEx hold Notes: t0 is the minimum total cycle time and td is the minimum command active time, while tkr and tkw are the minimum command recovery time or command inactive time for input and output cycles respectively. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, td, tkr, and tkw shall be met. The minimum total cycle time requirement is greater than the sum of td and tkr or tkw for input and output cycles respectively. This means a host implementation can lengthen either or both of td and either of tkr, and tkw as needed to ensure that t0 is equal to or greater than the value reported in the device s identify device data. A device implementation shall support any legal host implementation. Figure 12: True IDE Multiword DMA Mode Read/Write Timing Diagram Notes: 1) If the Rugged 1.8 /2.5 IDE Flash Disk cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the signal at a later time to continue the DMA operation. 2) This signal may be negated by the host to suspend the DMA transfer in progress. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 20

27 Ultra DMA Signal in Each Interface Mode Table 21: Ultra DMA Signal in True IDE Mode Signal Type (Non UDMA PC Card Memory PC Card IO Mode TRUE IDE MODE Memory Mode) Mode UDMA UDMA UDMA DMARQ Output (-INPACK) -DMARQ -DMARQ DMARQ HREG Input (-REG) - DMARQ DMARQ - DMARQ HIOW Input (-IOWR) STOP 1 STOP 1 STOP 1 HIOE Input (-IORD) IORDY Output (-WAIT) -HDMARDY(R) 1,2 HSTROBE(W) 1,3,4 -DDMARDY(W) 1,3 DSTROBE(R) 1,2,4 1,2 -HDMARDY(R) HSTROBE(W) 1,3,4 1,3 -DDMARDY(W) DSTROBE(R) 1,2,4 1,2 -HDMARDY(R) HSTROBE(W) 1,3,4 1,3 -DDMARDY(W) DSTROBE(R) 1,2,4 HD[15:00] Bidir (D[15:00]) D[15:00] D[15:00] D[15:00] HA[10:00] Input (A[10:00]) A[10:00] 5 A[10:00] 5 A[02:00] 5 CSEL Input (-CSEL) -CSEL -CSEL -CSEL HIRQ Output (READY) READY -INTRQ INTRQ CE1 (-CE1) -CE1 -CE1 -CS0 Input CE2 (-CE2) -CE2 -CE2 -CS1 Notes: 1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst. 2) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Read command. 3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command. 4) The HSTROBE signals are active on both the rising and the falling edge. 5) Address lines 03 through 10 are not used in True IDE mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 21

28 Ultra DMA Data Burst Timing Requirement Table 22: Ultra DMA Data Burst Timing Requirement Name UDMA Mode 0 UDMA Mode 1 UDMA Mode 2 UDMA Mode 3 UDMA Mode 4 Measure Location2 Min Max Min Max Min Max Min Max Min Max (See Note 2) t2cyctyp Sender tcyc Note3 t2cyc Sender tds Recipient tdh Recipient tdvs Sender tdvh Sender tcs Device tch Device tcvs Host tcvh Host tzfs Device tdzfs Sender tfs Device tli Note4 tmli Host tui Host taz Note5 tzah Host tzad Device tenv Host trfs Sender trp Recipient tiordyz Device tziordy Device tack Host tss Sender Notes: All Timings in ns 1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V. 2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column. For example, in the case of trfs, both STROBE and -DMARDY transitions are measured at the sender connector. 3) The parameter tcyc shall be measured at the recipient s connector farthest from the sender. 4) The parameter tli shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing response shall be measured at the same connector. 5) The parameter taz shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus to allow for a bus turnaround. 6) See the AC Timing requirements in Ultra DMA AC Signal Requirements. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 22

29 Ultra DMA Data Burst Timing Descriptions Table 23: Ultra DMA Data Burst Timing Descriptions Name Comment Notes T2CYCTYP Typical sustained average two cycle time tcyc Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) t2cyc Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge next falling edge of STROBE) tds Data setup time at recipient (from data valid until STROBE edge) 2,5 tdh Data hold time at recipient (from STROBE edge until data may become invalid) 2,5 tdvs Data valid setup time at sender (from data valid until STROBE edge) 3 tdvh Data valid hold time at sender (from STROBE edge until data may become invalid) 3 tcs CRC word setup time at device 2 tch CRC word hold time device 2 tcvs CRC word valid setup time at host (from CRC valid until -DMACK negation) 3 tcvh CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid) 3 tzfs Time from STROBE output released-to-driving until the first transition of critical timing. tdzfs Time from data output released-to-driving until the first transition of critical timing. tfs First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) tli Limited interlock time 1 tmli Interlock time with minimum 1 tui Unlimited interlock time 1 taz Maximum time allowed for output drivers to release (from asserted or negated) tzah Minimum delay time required for output tzad drivers to assert or negate (from released) tenv Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation) trfs Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of -DMARDY) trp Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY) tiordyz Maximum time before releasing IORDY tziordy Minimum time before driving IORDY 4 tack Setup and hold times for -DMACK (before assertion or negation) tss Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) Notes: (1) The parameters tui, tmli (in Figure16: Ultra DMA Data-In Burst Device Termination Timing and Figure 17: Ultra DMA Data-In Burst Host Termination Timing), and tli indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tui is an unlimited interlock that has no maximum time value. tmli is a limited time-out that has a defined minimum. tli is a limited time-out that has a defined maximum. (2) 80-conductor cablingshall be required in order to meet setup (tds, tcs) and hold (tdh, tch) times in modes greater than 2. (3) Timing for tdvs, tdvh, tcvs and tcvh shall be met for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system. (4) For all timing modes the parameter tziordy may be greater than tenv due to the fact that the host has a pull-up on IORDY- giving it a known state when released. (5) The parameters tds, and tdh for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable. This could result in the minimum values for tds and tdh for mode 5 at the middle connector being 3.0 and 3.9 ns respectively. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 23

30 Ultra DMA Sender and Recipient IC Timing Requirements Table 24: Ultra DMA Sender and Recipient IC Timing Requirements Name UDMA Mode 0 UDMA Mode 1 UDMA Mode 2 UDMA Mode 3 UDMA Mode 4 Min Max Min Max Min Max Min Max Min Max tdsic tdhic tdvsic tdvhic tdsic Recipient IC data setup time (from data valid until STROBE edge) (see note 2) tdhic Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2) tdvsic Sender IC data valid setup time (from data valid until STROBE edge) (see note 3) tdvhic Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3) Notes: (1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V. (2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tdsic and tdhic timing (as measured through 1.5 V). (3) The parameters tdvsic and tdvhic shall be met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values Ultra DMA AC Signal Requirements Table 25: Ultra DMA AC Signal Requirements Name Comment Min [V/ns] Max [V/ns] Notes SRISE Rising Edge Slew Rate for any signal SFALL Falling Edge Slew Rate for any signal Notes: (1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point. All other signals should remain connected through to the recipient. The test point may be located at any point between the sender s series termination resistor and one half inch or less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within one half inch of the connector. The test load and test points should then be soldered directly to the exposed source side connectors. The test loads consist of a 15 pf or a 40 pf, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the test point to ground. Slew rates shall be met for both capacitor values. Measurements shall be taken at the test point using a <1 pf, >100 Kohm, 1 Ghz or faster probe and a 500 MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output high level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent falling edge. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 24

31 Ultra DMA Data-In Burst Initiation Timing Figure 13: Ultra DMA Data-in Burst Initiation Timing Diagram ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the IORDY:-DDMARDY: DSTROBE,-IORD:-HDMARDY: HSTROBE, and IOWR:STOP signal lines are not in effect until DMARQ and DMACK are asserted. HA[02:00],-CS0 & -CS1 are True IDE mode signal definitions. HA[10:00],-CE1 and CE2 are PC Card mode signals. The Bus polarity of (-) DMACK and (-) DMARQ are dependent on interface mode active. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 25

32 Sustained Ultra DMA Data-In Burst Timing Figure 14: Sustained Ultra DMA Data-in Burst Initiation Timing Diagram Note: HD [15:00] and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Ultra DMA Data-In Burst Host Pause Timing Figure 15: Ultra DMA Data-In Burst Host Pause Timing Diagram APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 26

33 ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: (1) The host may assert STOP to request termination of the Ultra DMA data burst no sooner than trp after HDMARY is negated. (2) After negating HDMARDY, the host may receive zero, one, two, or three more data words from the device. (3) The bus polarity of the (-) DMARQ and (-) DMACK signals is dependent on the active interface mode Ultra DMA Data-In Burst Device Termination Timing Figure 16: Ultra DMA Data-In Burst Device Termination Timing Diagram ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. HA[02:00], -CS0& -CS1 are True IDE mode signal definitions. HA[10:00], -CE1 and -CE2 are PC Card mode signals. The bus polarity of DMARQ and DMACK are dependent on the active interface mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 27

34 Ultra DMA Data-In Burst Host Termination Timing Figure 17: Ultra DMA Data-In Burst Host Termination Timing Diagram ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. HA[02:00], -CS0& -CS1 are True IDE mode signal definitions. HA[10:00], -CE1 and CE2 are PC Card mode signals. The bus polarity of DMARQ and DMACK are dependent on the active interface mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 28

35 Ultra DMA Data-Out Burst Host Initiation Timing Figure 18: Ultra DMA Data-Out Burst Initiation Timing Diagram ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, DDMARD, and HSTROBE signal lines are no in effect after DMARQ and DMACK are asserted. HA[02:00], -CS0& -CS1 are True IDE mode signal definitions. HA[10:00], -CE1 and -CE2 are PC Card mode signals definitions. The bus polarity of DMARQ and DMACK dependent on the active interface mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 29

36 Sustained Ultra DMA Data-Out Burst Host Initiation Timing Figure 19: Sustained Ultra DMA Data-Out Burst Timing Diagram Notes: Data (HD[15:00]) and HSTROBE signals are shown at both the device and the host to emphasize that cable Setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 30

37 Ultra DMA Data-Out Burst Device Pause Timing Figure 20: Ultra DMA Data-out Burst Device Pause Timing Diagram ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: (1) The device may negate DMARQ to request termination of the Ultra DMA data burst no sooner than trp after DDMARDY, is negated. (2) After negating DDMARDY, the device may receive zero, one, two, or three more data words from the host. (3) The bus polarity of DMARQ and DMACK depend on the active interface mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 31

38 Ultra DMA Data-Out Burst Device Termination Timing Figure 21: Ultra DMA Data-Out Burst Device Termination Timing Diagram ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. HA[00:02], -CS0& -CS1 are True IDE mode signal definitions. HA[00:10], -CE1 and -CE2 are PC Card mode signals. The bus polarity of DMARQ and DMACK are dependent on the active interface mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 32

39 Ultra DMA Data-Out Burst Host Termination Timing Figure 22: Ultra DMA Data-Out Burst Host Termination Timing Diagram ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. HA[02:00], -CS0& -CS1 are True IDE mode signal definitions. HA[10:00], -CE1 and -CE2 are PC Card mode signal definitions. The bus polarity of DMARQ and DMACK are dependent on the active interface mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 33

40 5. Interface Register Definition 5.1. Device Address This controller receives commands from the host only when it is the selected device by checking the DEV bit in the Device Register. This interface is for the host to program and perform commands and return status. Table 26: Device Address Commands 5.2. I/O Register Descriptions The Command Block registers are used for the host to send commands to this controller or for this controller to post status. These registers include the LBA High, LBA Mid, LBA Low, Device, Sector Count, Command, Status, Features, Error and Data Registers. The Control Block register is used for device control and to post alternate status. These registers include Device Control and Alternate Status registers. For the detail field/bit description of every register, please refer to the ATAPI-5 specification. (4) Alternate Status Register This register contains the same information as the Status register in the Command Block. (5) Command Register This register contains the command code being sent. This controller begins immediately to execute the command after receipt of the command (6) DMA Data Port This port is only accessed for the host DMA data transfers when DMACK and DMARQ are asserted. The data is 16-bits in width. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 34

41 (7) Data Register This register is accessed for the host PIO data transfer only when DRQ is set to one and DMACK is not asserted. The contents of this register are not valid while it is in the Sleep mode. This register is 16 bits wide. (8) Device Register This register is for the host to set bit 4, DEV, of this register to selects the device. Other bis in this register are command dependent. (9) Device Control Register This register allows the host to software reset attached devices and to enable or disable the assertion of the INTRQ signal by a selected device. When this register is written, the controller will respond to the write no matter the device is selected or not. And this controller will respond to the SRST bit when in the SLEEP mode. (10) Error Register At command completion of any command, the contents of this register are valid when the ERR bit is set to one in the Status register. (11) Feature Register This register is writing only, If this address is reading by the host, the content read by the host will be the Error register. The content of this register is command dependent. (12) LBA High Register This register contains the high order bits of logic block address and becomes a command parameter when Command register is written. (13) LBA Low Register This register contains the low order bits of logic block address and becomes a command parameter when Command register is written. (14) LBA Mid Register This register contains bit 15-8 of logic block address and becomes a command parameter when Command register is written. (15) Sector Count Register This register contains the numbers of sectors of data requested to be transferred on a read or write operation. (16) Status Register This register contains the device status. The contents of this register are updated to reflect the current state of the device. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 35

42 6. Software Specification 6.1. ATA Command Set The following table summarizes the commands supported by the controller. Table 27: ATA Command Set Command Code FR SC SN CY DH LBA Controller Status Note 1 Check Power Mode E5 or 98h Y Support 2 Execute Drive Diagnostic 90h Y Support 3 Erase Sector C0h Y Y Y Y Y Support 4 Flush Cache E7h Y NOT Support #4 5 Format Track 50h Y Y Y Y Support 6 Identify Device Ech Y Support 7 Idle E3h or 97h Y Y Support 8 Idle Immediate E1h or 95h Y Support 9 Initialize Drive Parameters 91h Y Y Support 10 Key Management Structure B9 (Feature Y Y Y Y Y NOT Support #1 Read 0-127) 11 Key Management Read B9 (Feature Y Y Y Y Y NOT Support #1 Keying Material 80) 12 Key Management Change B9 (Feature Y Y Y Y Y NOT Support #1 Key Management Value 81) 13 NOP 00h Y Support 14 Read Buffer E4h Y Support 15 Read DMA C8h Y Y Y Y Y Support 16 Read Long Sector 22h or 23h Y Y Y Y NOT Support #3 17 Read Multiple C4h Y Y Y Y Y Support 18 Read Sector(s) 20h or 21h Y Y Y Y Y Support 19 Read Verify Sector(s) 40h or 41h Y Y Y Y Y Support 20 Recalibrate 1Xh Y Support 21 Request Sense 03h Y Support 22 Security Disable Password F6h Y NOT Support #2, #5 23 Security Erase Prepare F3h Y NOT Support #2, #5 24 Security Erase Unit F4h Y NOT Support #2, #5 25 Security Freeze Lock F5h Y NOT Support #2, #5 26 Security Set Password F1h Y NOT Support #2, #5 27 Security Unlock F2h Y NOT Support #2, #5 28 Seek 7Xh Y Y Y Y Support 29 Set Feature EFh Y Y Support 30 Set Multiple Mode C6h Y Y Support 31 Set Sleep Mode E6h or 99h Y Support 32 Standby E2 or 96h Y Support APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 36

43 Command Code FR SC SN CY DH LBA Controller Status Note 33 Standby Immediate E0 or 94h Y Support 34 Translate Sector 87h Y Y Y Y Y Support 35 Wear Level F5h Y Support 36 Write Buffer E8h Y Support 37 Write DMA CAh Y Y Y Y Y Support 38 Write Long Sector 32h or 33h Y Y Y Y Not Support #3 39 Write Multiple C5h Y Y Y Y Y Support 40 Write Multiple w/o Erase CDh Y Y Y Y Y Support 41 Write Sector(s) 30h or 31h Y Y Y Y Y Support 42 Write Sector(s) w/o Erase 38h Y Y Y Y Y Support 43 Write Verify 3Ch Y Y Y Y Y Support Notes: 1) These commands are optional, depending on the key Management scheme in use. 2) Use of this command is not recommended by Rugged 1.8 /2.5 IDE Flash Disk. 3) Use of this command is not recommended. 4) SM223 don't have cache. 5) Will support by firmware update, it will be available by September, ) Definitions FR = Features Register SC =Sector Count register (00H to FFH, 00H means 256 sectors) S N = Sector Number register CY = Cylinder Low/High register DH = Head No. (0 to 15) of Drive/Head register LBA = Logic Block Address Mode Support = Not used for the command Y = Used for the command APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 37

44 6.2. ATA Command Description (1) CFA Erase Sector(s) C0h This command pre-erases and conditions from 1 to 256 sectors in the Sector Count register. This command must be issued in advance of CFA Write without Erase or CFA Write Multiple without Erase command to increase the execution speed of the write operation. (2) CFA Request Extended Error Code 03h This command requests extended error information for the previous command. The extended error code is returned to the host in the Error Register. (3) CFA Translate Sector 87h This command allows the host a method of determining the exact times a user sector has been erased and programmed. This controller will respond with a 512-byte buffer of information containing the desired cylinder, head and sector, including its Logical Address. (4) CFA Write Multiple w/o Erase CDh This command is similar to Write Multiple command with the exception that an implied erase before write operation is not performed. (5) Write Sector(s) w/o Erase 38h This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. (6) Check Power Mode E5h This command allows the host to determine the current power mode of the device. This command will not cause this controller to change power mode. (7) Execute Device Diagnostic 90h This command causes the controller to perform the internal diagnostic tests. (8) Identify Device ECh This command enables the host to receive parameter information from the device. The following table specifies each field in the data returned by Identify Device command. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 38

45 Table 28: Identify Device Commands APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 39

46 APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 40

47 APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 41

48 Notes: (1) F/V = Fixed/Variable content F = the content of the word is fixed and does not change. V = the content of the word is variable and may be changed depending on the state of the device, commands executed. X = the content of the word may be fixed or variable. C = vendor specific data which can be customized before device shipping. (2) aaaa indicates an ASCII vendor string; x indicates a numeric nibble value. (9) Idle E3h This command allows the host to place the device in the Idle mode and also set the Standby timer. (10) Idle Immediate E1h This command allows the host to immediately place the device in the Idle mode. (11) Initialize Device Parameters 91h This command enables the host to set the number of sectors per track and number of heads per cylinder. (12) NOP 00h This controller will respond with command abort upon receipt of the NOP command. (13) Read Buffer E4h This command enables the host to read the current contents of the device s sector buffer. (14) Read DMA C8h This command allows the host to read data using the DMA data transfer protocol. (15) Read Multiple C4h APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 42

49 This command reads the number of sectors specified in the Sector Count register. The number of sectors per block is defined by the content of word 59 in the Identify Device response. A successful Set Multiple Mode command has to precede this command. (16) Read Sector(s) 20h This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 will be treated as 256 sectors. The transfer begins at the sector specified in the LBA Low, LBA Mid, LBA High and Device registers. (17) Read Verify Sector(s) 40h This command is identical to Read Sector(s) command, except that DRQ is never set and no data is transferred to the host. (18) Seek 70h This command allows the host to provide advanced notification that particular data may be requested by the host in a subsequent command. (19) Set Features EFh This command is used by the host to establish parameters that affect the execution of certain features. The following table defines all features that are supported by this controller. If any subcommand input value is not supported or is invalid, this controller will return command aborted. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 43

50 Table 29: Set Feature Commands (20) Set Multiple Mode C6h Upon receipt of this command, the controller will perform Read and Write Multiple operations and establishes the block count for these commands. This controller will set BSY to 1 and checks the Sector Register for the number of sectors per block. (21) Sleep E6h Upon receipt of this command, the controller will set BSY and enter Sleep mode, clear BSY and generate an interrupt. (22) Standby E2h This command will cause the device to enter Standby mode. The value in the Sector Count register is used to determine the time programmed into the Standby timer. (23) Standby Immediate E0h or 94h This command will cause the device to immediately enter Standby mode. APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 44

51 (24) Write Buffer E8h This command allows the host to overwrite contents of a sector buffer with any data pattern desired. (25) Write DMA CAh This command allows the host to write data using the DMA data transfer protocol. (26) Write Multiple C5h This command is similar to the Write Sector(s) command. Interrupts are not presented on each sector but on the transfer of a block that contains the number of sectors defined by Set Multiple. (27) Write Sector(s) 30h This command writes from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 will be treated as 256 sectors. This controller will interrupt for each DRQ block transferred S.M.A.R.T Command Support APRO Rugged 1.8 /2.5 IDE Flash Disk - MA Series supports SMART command set and defines some vendor specific data to report spare/bad block number in each memory management unit. Users can get the data by Read Data command SMART Feature Register Values Table 30: SMART Feature Register Values D0h Read Data D4h Execute OFF-LINE Immediate D1h Read Attribute Threshold D8h Enable SMART Operations D2h Enable/Disable Autosave D9h Disable SMART Operations D3h Save Attribute Values DAh Return Status Notes: If reserved size below the Threshold, the status can be read from Cylinder register by Return Status command (DAh). APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 45

52 SMART Data Structure ( Read Data (Doh)) Table 31: SMART Data Structure BYTE F / V Description 0-1 X Revision code X Vendor specific 362 V Off line data collection status 363 X Self-test execution status byte V Total time in seconds to complete off-line data collection activity 366 X Vendor specific 367 F Off-line data collection capability F SMART capability 370 F Error logging capability 7-1 Reserved 0 1=Device error logging supported 371 X Vendor specific 372 F Short self-test routine recommended polling time (in minutes) 373 F Extended self-test routine recommended polling time (in minutes) 374 F Conveyance self-test routine recommended polling time (in minutes) R Reserved F Firmware Version/Date Code 396 V Number of MU in device (0~n) 397+(n*6) V MU number 398+(n*6) V MU data block 400+(n*6) V MU spare block 401+(n*6) V Init. Bad block 402+(n*6) V Run time Bad block information 511 V Data structure checksum Notes: F = the content of the byte is fixed and does not change. V = the content of the byte is variable and may change depending on the state of the device or the commands executed by the device. X = the content of the byte is vendor specific and may be fixed or variable. R = the content of the byte is reserved and shall be zero. N = Nth Management Unit * 4 Byte value : [MSB] [2] [1] [LSB] APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 46

53 Execution of the SMART Function APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk- MA Series support SMART (Self-Monitoring Analysis and Reporting Technology) function, which is compliance with ATAPI-4. User can execute SMART function on APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk-MA Series by HD Turn 2.55 (Free) / Pro 3.0 or Active SMART 2.6. Below Figure23 / 24/ 25 are the testing results per HD Turn2.55(Free). ( Figure 23: HD Tune 2.5 -Hard Disk Utility for Benchmark Information on Rugged 1.8 / MB IDE Flash Disk APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 47

54 Figure 24: HD Tune 2.55-Hard Disk Utility for Card Information on Rugged 1.8 / MB IDE Flash Disk Figure 25: HD Tune 2.55-Hard Disk Utility for Health Information on Rugged 1.8 /2.5 IDE 128MB IDE Flash Disk APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 48

55 Below Figures 26/27/28 are testing results by HD Turn Pro 3.00 ( Figure 26: HD Tune Pro Disk Utility for Benchmark Information on Rugged 1.8 / MB IDE Flash Disk Figure 27: HD Tune Pro Disk Utility for Card Information on Rugged 1.8 / MB IDE Flash Disk APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 49

56 Figure 28: HD Tune Pro Disk Utility for Health Information on Rugged 1.8 / MB IDE Flash Disk Below Figures 29/30/31 are testing results by Active SMART 2.6 Trial version ( Figure 29: Active SMART 2.6 (Trial version) for General Information on Rugged 1.8 / MB IDE Flash Disk APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 50

57 Figure 30: Active SMART 2.6 (Trial version) for Disk Information on Rugged 1.8 / MB IDE Flash Disk APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 51

58 Figure 31: Active SMART 2.6 (Trial version) for SMART Information on Rugged 1.8 / MB IDE Flash Disk APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 52

59 6.4. ID Table Information Word Address Default value Total Bytes Table 32: Identify Data Information 0 044Ah 2 General configuration 1 XXXXh 2 Default number of cylinders h 2 Reserved 3 00XXh 2 Default number of heads h 2 Obsolete h 2 Obsolete 6 XXXXh 2 Default number of sectors per track Data Field Type information 7-8 XXXXh 4 Number of sectors per card (Word 7 = MSW, Word 8 = LSW) h 2 Obsolete XXXXh 20 Serial number in ASCII (Right Justified) h 2 Obsolete h 2 Obsolete h 2 Number of ECC bytes passed on Read/Write Long Commands XXXXh 8 Firmware revision in ASCII. Big Endean Byte Order in Word XXXXh 40 Model number in ASCII (Left Justified) Big Endean Byte Order in Word h 2 Maximum number of sectors on Read/Write Multiple command h 2 Reserved h 2 Capabilities h 2 Reserved h 2 PIO data transfer cycle timing mode h 2 Obsolete h 2 Field validity 54 XXXXh 2 Current numbers of cylinders 55 XXXXh 2 Current numbers of heads 56 XXXXh 2 Current sectors per track XXXXh 4 Current capacity in sectors (LBAs)(Word57=LSW, Word58=MSW) h 2 Multiple sector setting XXXXh 4 Total number of sectors addressable in LBA Mode h 2 Reserved h 2 Multiword DMA transfer. In PCMCIA mode this value shall be oh h 2 Advanced PIO modes supported h 2 Minimum Multiword DMA transfer cycle time per word h 2 Recommended Multiword DMA transfer cycle time h 2 Minimum PIO transfer cycle time without flow control h 2 Minimum PIO transfer cycle time with lordy flow control h 20 Reserved h 2 Major version number h 2 Minor version number h 2 Command sets supported Ch 2 Command sets supported h 2 Command sets supported h 2 Command sets Enable h 2 Command sets Enable h 2 Command sets Enable 2 APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 53

60 88 001Fh 2 True IDE Ultra DMA Mode Supported and Selected (UDMA0~4) h 2 Time required for Security erase unit completion h 2 Time required for Enhanced security erase unit completion h 2 Current Advanced power manage mentvalue h 72 Reserved h 2 Security status h 64 vendor unique bytes F4h 2 Power requirement description h 2 Reserved for assignment by the CFA h 2 Key management schemes supported h Bh 2 RUGGED 1.8 /2.5 IDE FLASH DISK Advanced True lde Timing Mode Capability and Setting h 22 80ns cycle in memory and IO mode RUGGED 1.8 /2.5 IDE FLASH DISK Advanced PCMCIA I/O and Memory Timing Mode Capability and set h 140 Reserved for assignment by the CFA Notes: Word 1: Default number of cylinders. Word 3: Default number of heads. Word 6: Default number of sectors per track. Word 10~19: Serial number in ASCII. Word 23~26: Firmware revision in ASCII. Word 27~26: Model number in ASCII APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 54

61 7. Installation Procedure 7.1. Before unpacking Before unpacking or handling a drive, take all proper electrostatic discharge (ESD) precautions, including personal and equipment grounding. Before you start to install the industrial R8/2IFD into your system please check the following. If the shipping container appears to be damaged or water stained, notify your dealer. Remove the disk from its shipping enclosure and inspect it for any damage that may have occurred during shipment. If any damage is observed, notify your dealer. Record the disk serial number and shipment date. Retain the original shipping enclosure and all packing material for re-shipment ESD Precautions You can prolong the life of your Flash disk as well as increase its reliability and prevent unnecessary damage by following the instructions listed below. Failure to follow any of these instructions may void your warranty. (1) Always take all proper electrostatic discharge (ESD) precautions, including personnel and equipment grounding. (2) Always operate the Flash disk within the environmental specifications. (3) Always use a grounded wrist strap when handling the Flash disk. Drives that are not installed in the system are sensitive to ESD damage Master/Slave/Cable Selecting Setting Before mounting in the system s drive bay, the R8/2IFD must be configured. The master/slave jumper is located on the IDE header of the R8/2IFD. Please refer to Figure 4 shows the front view of the 44-pin connector and the location of the jumpers. Figure 5 shows the valid jumper configurations for master, slave, and cable selecting. Grayed pins indicate jumpers on. Figure 32: Configuration of Master/Slave/Cable Selecting Setting APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 55

62 pin IDE Cable & Cable Insertion A 44-pin flat cable is used for 2.5" internal hard drives. The 4 extra pins are used for supplying power and GROUND to the drive. The hard drive ribbon cable will have a red stripe down the side with Pin 1. Also, the cable is likely to have a notch that will match up with a cut-out notch in the drive and a similar cut-out notch in the main board socket for the IDE connector. Often, there is a missing pin ( Pin 20) at the bottom center of the connector. 44-pin Cable line specification: (1) Standard 44-pin IDE flat cable (2) Pitch: 2.0mm (3) Length: Do not over 18 (457.2 mm max.) (4) Standard power connector to power supply (5) Pin 41(+5V logic); Pin 42 (+5V motor) (6) Pin 43(Ground); Pin44 (Reserved, no connection) Figure 33: 44-pin IDE Flat Cable 7.5. Mounting The APRO s R8/2IFD mounts into a standard 2.5" hard disk drive bay and may be mounted from the side or the bottom. There are 8 mounting holes on sides and 8 mounting holes on the bottom. Consider the length of screw used and thickness of the mounting surface. A common screw length of 4mm is provided but may not be correct in all applications. Refer to Figure 3 for mounting hole s locations. Double check all connections, also make sure you haven't loosened any connections while you have been installing IDE Device Setup / Auto-Detection Most BIOSes have an entry in the Standard Setup menu for each of the four IDE/ATA devices supported in a system (primary master, primary slave, secondary master, and secondary slave). For each one, you can enter a value for each setting in this section (type, size, cylinders, etc.). Virtually all BIOSes now come with IDE device Auto-Detection. This comes in two forms: Dynamic IDE Auto-Detection: This is the fully automatic mode. You set one or more of the IDE devices (primary master, primary slave, etc.) on "Auto" and the BIOS will automatically re-detect and set the correct options for the drive each time you boot the PC. The BIOS will usually display on the screen what device it finds each time it auto-detects. For most people, this is the best way to go; it ensures that your APRO Industrial Rugged 1.8 /2.5 IDE Flash Disk MA Series 2008 APRO Co., Ltd. 56