Customer: Customer. Part Number: InnoDisk. Part Number: InnoDisk. Model Name: Date: InnoDisk. Customer. Approver. Approver

Transcription

1 Customer: Customer Part Number: InnoDisk Part Number: InnoDisk Model Name: Date: InnoDisk Approver Customer Approver

2 Table of contents 1. INTRODUCTION FEATURES PIN ASSIGNMENT PIN DESCRIPTION SPECIFICATIONS CE AND FCC COMPATIBILITY ROHS COMPLIANCE ENVIRONMENTAL SPECIFICATIONS Temperature Ranges Humidity Shock and Vibration Mean Time between Failures (MTBF) MECHANICAL DIMENSIONS ELECTRICAL SPECIFICATIONS DC Characteristic Timing Specifications TRANSFER FUNCTION I/O Transfer function Common Memory Transfer Function True IDE Mode I/O Transfer Function CONFIGURATION REGISTER Configuration Option Register (200h in Attribute Memory) Card Configuration and Status Register (202h in Attribute Memory) Pin Replacement register (204h in Attribute Memory) Socket and Copy Register (206h in Attribute Memory) SOFTWARE INTERFACE CF-ATA Drive Register Set Definition and Protocol I/O Primary and Secondary Address Configurations Contiguous I/O Mapped Addressing Memory Mapped Addressing True IDE Mode Addressing CF-ATA Register HARDWARE RESET(ONLY FOR MEMORY CARD MODE AND I/O CARD MODE) POWER ON RESET SUPPORTED IDE COMMANDS Check power mode E5h or 98H Rev. 1.2 Datasheet, Oct. 2011

3 Execute Device Diagnostic 90h Flush Cache- E7h Identify Device ECh Idle E3h or 97h Idle immediate E1h or 95h Read Buffer E4h Read DMA C8h Read Sector(s) 20h or 21h Read Verify Sector(s) 40h or 41h Set Features EFh Set Multiple Mode C6h Set Sleep Mode E6h or 99h Standby E2h or 96h Standby Immediate E0h or 94h Write Buffer E8h Write DMA CAh Write Multiple- C5h Write Sector(s) 30h or 31h SMART DEVICE PARAMETERS Rev. 1.2 Datasheet, Oct. 2011

4 REVISION HISTORY Revision Description Date Preliminary Release Preliminary Version Mar Rev. 1.0 First Release Apr Rev. 1.1 Modify capacity and CHS table Jan Rev. 1.2 Update capacity Modify part number rule Add new ME Oct Rev. 1.3 Modify performance May Rev. 1.2 Datasheet, Oct. 2011

5 List of Tables TABLE 1: INNOLITE EDC PIN ASSIGNMENTS TABLE 2: INNOLITE EDC PIN DESCRIPTION TABLE 3: SHOCK/VIBRATION TEST FOR INNOLITE EDC TABLE 4: INNOLITE EDC MTBF TABLE 5: ATTRIBUTE MEMORY READ TIMING TABLE 6: CONFIGURATION REGISTER (ATTRIBUTE MEMORY) WRITE TIMING TABLE 7: COMMON MEMORY READ TIMING TABLE 8: COMMON MEMORY WRITE TIMING TABLE 9: I/O READ TIMING TABLE 10: I/O WRITE TIMING TABLE 11: READ/WRITE TIMING SPECIFICATIONS, PIO MODE TABLE 12: READ/WRITE TIMING SPECIFICATIONS, MULTIWORD DMA MODE TABLE 13: TIMING DIAGRAM, ULTRA DMA MODE TABLE 14: PCMCIA MODE I/O FUNCTION TABLE 15: COMMON MEMORY FUNCTION TABLE 16: TRUE IDE MODE I/O FUNCTION TABLE 17: CONFIGURATION OPTION REGISTER TABLE 18: INFORMATION FOR CONFIGURATION OPTION REGISTER TABLE 19:INNOLITE EDC CONFIGURATION TABLE 20: CARD CONFIGURATION AND STATUS REGISTER TABLE 21: INFORMATION FOR CARD CONFIGURATION AND STATUS REGISTER TABLE 22: PIN REPLACEMENT REGISTER TABLE 23: INFORMATION FOR PIN REPLACEMENT REGISTER TABLE 24: SOCKET AND COPY REGISTER TABLE 25: INFORMATION FOR SOCKET AND COPY REGISTER TABLE 26: I/O CONFIGURATION TABLE 27: PRIMARY AND SECONDARY I/O DECODING TABLE 28: CONTIGUOUS I/O DECODING TABLE 29: MEMORY MAPPED DECODING TABLE 30: TRUE IDE MODE I/O DECODING TABLE 31: DATA REGISTER TABLE 32: ERROR REGISTER TABLE 33: FEATURE REGISTER TABLE 34: SECTOR COUNT REGISTER TABLE 35: SECTOR NUMBER REGISTER TABLE 36: CYLINDER LOW REGISTER TABLE 37: CYLINDER HIGH REGISTER TABLE 38: DEVICE/HEAD REGISTER Rev. 1.2 Datasheet, Oct. 2011

6 TABLE 39: STATUS REGISTER TABLE 40: DEVICE CONTROL REGISTER TABLE 41: DRIVE ADDRESS REGISTER TABLE 42: TIMING DIAGRAM, HARDWARE RESET TABLE 43: TIMING DIAGRAM, POWER ON RESET TABLE 44: IDE COMMANDS TABLE 45: CHECK POWER MODE INFORMATION TABLE 46: EXECUTE DEVICE DIAGNOSTIC INFORMATION TABLE 47: DIAGNOSTIC TABLE 48: FLUSH CACHE COMMAND FOR INPUTS INFORMATION TABLE 49: FLUSH CACHE COMMAND FOR NORMAL OUTPUT INFORMATION TABLE 50: FLUSH CACHE COMMAND FOR ERROR OUTPUT INFORMATION TABLE 51: IDENTIFY DEVICE INFORMATION TABLE 52: IDENTIFY DEVICE INFORMATION TABLE 53: IDLE INFORMATION TABLE 54: IDLE IMMEDIATE INFORMATION TABLE 55: READ BUFFER INFORMATION TABLE 56: READ DMA INFORMATION TABLE 57: READ SECTOR INFORMATION TABLE 58: READ VERIFY SECTOR INFORMATION TABLE 59: SET FEATURE INFORMATION TABLE 60: FEATURE SUPPORTED TABLE 61: SET MULTIPLE MODE INFORMATION TABLE 62: SET SLEEP MODE INFORMATION TABLE 63: STANDBY INFORMATION TABLE 64: STANDBY IMMEDIATE INFORMATION TABLE 65: WRITE BUFFER INFORMATION TABLE 66: WRITE DMA INFORMATION TABLE 67: WRITE MULTIPLE COMMAND FOR INPUTS INFORMATION TABLE 68: WRITE MULTIPLE COMMAND FOR NORMAL OUTPUT INFORMATION TABLE 69: WRITE MULTIPLE COMMAND FOR NORMAL OUTPUT INFORMATION TABLE 70: WRITE SECTOR INFORMATION TABLE 71: SMART FEATURE REGISTER VALUES TABLE 72: SMART COMMAND FOR INPUTS INFORMATION TABLE 73: SMART COMMAND FOR NORMAL OUTPUTS INFORMATION TABLE 74: SMART DATA STRUCTURE TABLE 75: SMART ENABLE COMMAND FOR INPUTS INFORMATION TABLE 76: SMART COMMAND FOR NORMAL OUTPUTS INFORMATION TABLE 77: SMART DISABLE COMMAND FOR INPUTS INFORMATION Rev. 1.2 Datasheet, Oct. 2011

7 TABLE 78: SMART COMMAND FOR NORMAL OUTPUTS INFORMATION TABLE 79: DEVICE PARAMETERS Rev. 1.2 Datasheet, Oct. 2011

8 List of Figures FIGURE 1 MECHANICAL DIMENSION OF INNOLITE EDC FIGURE 2: ATTRIBUTE MEMORY READ TIMING DIAGRAM FIGURE 3 CONFIGURATION REGISTER (ATTRIBUTE MEMORY) WRITE TIMING DIAGRAM FIGURE 4 COMMON MEMORY READ TIMING DIAGRAM FIGURE 5 COMMON MEMORY WRITE TIMING DIAGRAM FIGURE 6 I/O READ TIMING DIAGRAM FIGURE 7 I/O WRITE TIMING DIAGRAM FIGURE 8 READ/WRITE TIMING DIAGRAM, PIO MODE FIGURE 9 READ/WRITE TIMING DIAGRAM, MULTIWORD DMA MODE FIGURE 10 ULTRA DMA MODE DATA-IN BURST INITIATION TIMING DIAGRAM FIGURE 11 ULTRA DMA MODE DATA-OUT BURST INITIATION TIMING DIAGRAM FIGURE 12 SUSTAINED ULTRA DMA MODE DATA-IN BURST TIMING DIAGRAM FIGURE 13 SUSTAINED ULTRA DMA MODE DATA-OUT BURST TIMING DIAGRAM FIGURE 14 TIMING DIAGRAM, HARDWARE RESET FIGURE 15 TIMING DIAGRAM, POWER ON RESET Rev. 1.2 Datasheet, Oct. 2011

9 1. Introduction Embedded DISK CARD Lite (InnoLite EDC) products provide high capacity solid-state flash memory that electrically complies with the Personal Computer Memory Card International Association ATA standard. Embedded DISK CARD Lite (InnoLite EDC) is embedded solid-state data storage systems for industrial work place. Embedded DISK CARD Lite (InnoLite EDC) features an extremely light weight, reliable, low-profile form factor. Embedded DISK CARD Lite (InnoLite EDC) supports advanced PIO (0-4), Multi Word DMA (0-2), Ultra DMA (0-4) transfer modes, multi-sector transfers, and LBA addressing. 2. Features The Industrial ATA products provide the following system features: Capacities: 4GB to 32GB Fully compatible with the IDE standard interface, ATA Standard Access modes: True IDE Mode ECC (Error Correction Code) function: 24 bits/ per 1024 byte +3.3V/+5V power supply operation Support Auto Stand-by and Sleep Mode. Power Consumption Active mode Read operation: 86mA(Typ.) Write operation: 140mA(Typ.) Power Down mode: 1mA(Typ./max.) Support transfer modes: PIO(0-4), Multiword DMA (0-2) and Ultra DMA(0-4) MTBF 3,000,000 hours 9 Rev. 1.2 Datasheet, Oct. 2011

10 R/W performance: -Single: Read: 20Mbytes/s. (MAX) Write: 10Mbytes/s (MAX) -Dual: Read: 40Mbytes/s. (MAX) Write: 15Mbytes/s (MAX) Operating temperature range: 0 C ~ +70 C (Standard Temp.) -40 C ~ +85 C (Industrial Temp.) Storage temperature range: -55 C ~ +95 C 10 Rev. 1.2 Datasheet, Oct. 2011

11 3.Pin Assignment See Table 1 for InnoLite EDC pin assignments. Table 1: InnoLite EDC Pin Assignments Pin No. Name Function Pin No. Name Function 1 HRESET Host Reset 2 GND Ground 3 HDB[7] Host Data Bit 7 4 HDB[8] Host Data Bit 8 5 HDB[6] Host Data Bit 6 6 HDB[9] Host Data Bit 9 7 HDB[5] Host Data Bit 5 8 HDB[10] Host Data Bit 10 9 HDB[4] Host Data Bit 4 10 HDB[11] Host Data Bit HDB[3] Host Data Bit 3 12 HDB[12] Host Data Bit HDB[2] Host Data Bit 2 14 HDB[13] Host Data Bit HDB[1] Host Data Bit 1 16 HDB[14] Host Data Bit HDB[0] Host Data Bit 0 18 HDB[15] Host Data Bit GND Ground pin VCC 1 Supply Voltage 44pin KEY 1 Key-pin 21 DMARQ DMA Request 22 GND Ground 23 HIOW 3 STOP 4 Host I/O Write Stop Ultra DMA burst 24 GND Ground HIOR 3 Host I/O Read 25 HDMARDY 4 Ultra DMA ready 26 GND Ground HSTROBE 4 Ultra DMA data strobe 27 IORDY 3 DDMARDY 4 DSTROBE 4 I/O Ready Ultra DMA ready Ultra DMA data strobe 28 CSEL Master/Slave Select (Switch used) 29 DMACK DMA Acknowledge 30 GND Ground 31 INTRQ Interrupt Request 32 IOCS16 CS I/O 16-Bit 33 HAB[1] Host Address Bit 1 34 PDIAG Passed Diagnostic Pin No. Name Function Pin No. Name Function 35 HAB[0] Host Address Bit 0 36 HAB[2] Host Address Bit 2 11 Rev. 1.2 Datasheet, Oct. 2011

12 37 CS0 Chip Select 0 38 CS1 Chip Select 1 39 DASP Drive Active 40 GND Ground 41 2 VCC Supply Voltage 42 2 VCC Supply Voltage 43 2 GND Ground 44 2 NC Not Connected 1. In the 40-pin version, this pin is defined as VCC to reduce the need for an external power connector. In the 44-pin version, this pin is defined as KEY, according to the ATA standard. 2. The 40-pin version does not contain pins NC = These pins are not connected internally. 3. Signal usage in PIO & Multiword DMA mode. 4. Signal usage in Ultra DMA mode. 4. Pin Description Table 2 describes the pin descriptions for InnoLite EDC Table 2: InnoLite EDC Pin Description Pin Name Pin No. Description I/O Host side pins HRESET- 1 Host reset signal, High: Reset. I CS0-37 Chip select CS0 I CS1-38 Chip select CS1 I INTRQ 31 Host interrupt signal. O HIOR- 3 I/O read strobe signal. HDMARDY DMA ready during Ultra DMA data in burst I HSTROBE 4 Data strobe during Ultra DMA data out burst HIOW STOP 4 I/O write strobe signal. Stop during Ultra DMA data bursts I IOCS16-32 Asserted in 16-bit access. O IORDY 3 27 DDMARDY- 4 I/O Ready Signal DMA ready during Ultra DMA data out burst O 12 Rev. 1.2 Datasheet, Oct. 2011

13 DSTROBE 4 Data strobe during Ultra DMA data in burst HDB[15:0] 18, 16, 14, 12, 10, 8, 6, 4, 3, 5, 7, 9, 11, 13, 15, 17 Host data bus I/O HAB[2:0] 33, 35, 36 Host Address bus I/O Master/Slave select signal (cable select signal). CSEL- 28 DASP- 39 PDIAG- 34 Low: Device operates as a master, High: Device operates as a slave. Switch used. Used as an input port to check in the master mode to see if the slave is present or not, and as an output port to check in the slave mode to see if the slave for the master is present or not. Used as an input port to evaluate the result of slave diagnosis in the master mode, and as an output port to return the result of diagnosis to the master. I I/O I/O DMARQ 21 DMA Request. O DMACK- 29 DMA Acknowledge. I Power and Ground VCC 20 1, 41 2, 42 2 Connect to VCC VCC GND 2, 19, 22, 24, 26, 30, 40, 43 2 Connect to GND. GND Other pins NC 44 2 Not used. Please do not connect. N/A 1. In the 40-pin version, this pin is defined as VCC to reduce the need for an external power connector. In the 44-pin version, this pin is defined as KEY, according to the ATA standard. 2. The 40-pin version does not contain pins NC = These pins are not connected internally. 3. Signal usage in PIO & Multiword DMA mode. 4. Signal usage in Ultra DMA mode. 13 Rev. 1.2 Datasheet, Oct. 2011

14 5. Specifications 5.1 CE and FCC Compatibility InnoLite EDC conforms to CE and FCC requirements. 5.2 RoHS Compliance InnoLite EDC is fully compliant with RoHS directive. 5.3 Environmental Specifications Temperature Ranges Operating Temperature Range: 0 C to +70 C (Stanard) -40 C to +85 C (Industrial) Storage Temperature Range: -55 C to +95 C Humidity Relative Humidity: 10-95%, non-condensing Shock and Vibration Table 3: Shock/Vibration Test for InnoLite EDC Reliability Test Conditions Reference Standards Vibration 7 Hz to 2 KHz, 20 g, 3 axes IEC Mechanical Shock Duration: 0.5ms, 1500 g, 3 axes IEC Mean Time between Failures (MTBF) Table 4 summarizes the MTBF prediction results for various InnoLite EDC configurations. The analysis was performed using a RAM Commander failure rate prediction. Failure Rate: The total number of failures within an item population, divided by the total number of life units expended by that population, during a particular measurement interval under stated condition. Mean Time between Failures (MTBF): A basic measure of reliability for repairable items: The mean number of life units during which all parts of the item perform within their specified limits, during a particular measurement interval under stated conditions. 14 Rev. 1.2 Datasheet, Oct. 2011

15 Table 4: InnoLite EDC MTBF Product Condition MTBF (Hours) InnoLite EDC Telcordia SR-332 GB, 25 C 3,000, Mechanical Dimensions 40pin Vertical (DE0H-XXXD5XXX) Mechanical Dimension: 60.2/6.4/27.8 mm±0.1(w/t/h) Figure 1 Mechanical Dimension of InnoLite EDC 40pin 44pin Vertical (DE4H-XXXD5XXX) Mechanical Dimension: 50.3/5.8/27.3 mm ± 0.1mm(W/T/H) Figure 2 Mechanical Dimension of InnoLite EDC 44pin 15 Rev. 1.2 Datasheet, Oct. 2011

16 5.5 Electrical Specifications DC Characteristic Item Symbol Rating Unit Input voltage V IN +5 DC ± 5% +3.3 DC ± 0.3 V Timing Specifications Attribute Memory Read Timing Specification Attribute Memory access time is defined as 300ns. Detailed timing specs are shown in Table 5. Speed Version Table 5: Attribute Memory Read Timing 300ns Item Symbol Min (ns) Max (ns) Read cycle time tc(r) 300 Address access time ta(ha) 300 Card enable access time ta(cex) 300 Output enable access time ta(hoe) 150 Output disable time from CE tdis(cex) 100 Output disable time from OE tdis(hoe) 100 Address setup time tsu(ha) 30 Output enable time from CE ten(cex) 5 Output enable time from OE ten(hoe) 5 Data valid from address change tv(ha) 0 Note: All times intervals are recorded in nanoseconds. HD refers to data provided by the CompactFlash Card to the system. The CEx# signal or both the HOE# signal and the HWE# signal are deasserted between consecutive cycle operations. 16 Rev. 1.2 Datasheet, Oct. 2011

17 Figure 3: Attribute Memory Read Timing Diagram Configuration Register (Attribute Memory) Write Timing Specification The Card Configuration write access time is defined as 250ns. Defined timing specifications are shown in Table 6. Table 6: Configuration Register (Attribute Memory) Write Timing Speed Version 250ns Item Symbol Min (ns) Max (ns) Write cycle time tc(w) 250 Write pulse width tw(hwe) 150 Address setup time tsu(ha) 30 Write recovery time trec(hwe) 30 Data setup time for WE tsu(hd-weh) 80 Data hold time th(hd) 30 Note: All times intervals are recorded in nanoseconds. HD refers to data provided by the system to the CompactFlash Card. 17 Rev. 1.2 Datasheet, Oct. 2011

18 Figure 4 Configuration Register (Attribute Memory) Write Timing Diagram Common Memory Read Timing Specification Table 7: Common Memory Read Timing Cycle Time Mode: 250ns 120ns 100ns 80ns Item Symbol Min Max Min Max Min Max Min Max ns. ns. ns. ns. ns. ns. ns. ns. Output enable access time ta(hoe) Output disable time from HOE# tdis(hoe) Address setup time tsu(ha) Address hold time th(ha) CEx# setup before HOE# tsu(cex) CEx# hold following HOE# th(cex) Wait delay falling from HOE# tv(iordy-hoe) Na 1 Data setup for wait release tv(iordy) Na 1 Wait width time 2 tw(iordy) Na 1 Note: 1) IORDY is not supported in this mode. 2) The maximum load on IORDY is 1 LSTTL with a 50 pf (40 pf below 120 nsec cycle time) total load. All times intervals are recorded in nanoseconds. HD refers to data provided by the CompactFlash Card to the system. The IORDY signal can be ignored when the HOE# cycle-to-cycle time is greater than the Wait Width time. The Max Wait 18 Rev. 1.2 Datasheet, Oct. 2011

19 Width time can be determined from the Card Information Structure (CIS). Although adhering to the PCMCIA specification of 12 µs, the Wait Width time is intentionally lower in this specification. Figure 5 Common Memory Read Timing Diagram Common Memory Write Timing Specification Table 8: Common Memory Write Timing Cycle Time Mode: 250ns 120ns 100ns 80ns Item Symbol Min Max Min Max Min Max Min Max ns. ns. ns. ns. ns. ns. ns. ns. Data Setup before HWE# tsu(hd-weh) Data Hold following HWE# th(hd) HWE# Pulse Width tw(hwe) Address Setup Time tsu(ha) CEx# Setup before HWE# tsu(cex) Write Recovery Time trec(hwe) Address Hold Time th(ha) CE Hold following HWE# th(cex) Wait Delay Falling from HWE# tv(iordy-we) Na 1 HWE# High from Wait Release tv(iordy) Na 1 Wait width time 2 tw(iordy) Na 1 Note: 1) IORDY is not supported in this mode. 19 Rev. 1.2 Datasheet, Oct. 2011

20 2) The maximum load on IORDY is 1 LSTTL with a 50 pf (40 pf below 120 nsec Cycle Time) total load. All times intervals are recorded in nanoseconds. HD refers to data provided by the CompactFlash Card to the system. The IORDY signal can be ignored when the HWE# cycle-to-cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure (CIS). Although adhering to the PCMCIA specification of 12 µs, the Wait Width time is intentionally lower in this specification. Figure 6 Common Memory Write Timing Diagram I/O Input (Read) Timing Specification Table 9: I/O Read Timing Cycle Time Mode: 250 ns 120 ns 100 ns 80 ns Item Symbol Min ns. Max ns. Min ns. Max ns. Min ns. Max ns. Min ns. Max ns. Data Delay after HIOE# td(hioe) Data Hold following HIOE# th(hioe) HIOE# Width Time tw(hioe) Address Setup before HIOE# tsua(hioe) Address Hold following HIOE# tha(hioe) Rev. 1.2 Datasheet, Oct. 2011

21 CEx# Setup before HIOE# CEx# Hold following HIOE# HREG# Setup before HIOE# HREG# Hold following HIOE# Wait Delay Falling from HIOE# 2 tsucex (HIOE) thcex (HIOE) tsuhreg (HIOE) thhreg (HIOE) tdiordy (HIOE) Na 1 Data Delay from Wait Rising 2 td(iordy) Na 1 Wait Width Time 2 tw(iordy) Na 1 Note: 1) IORDY is not supported in this mode. 2) Maximum load on IORDY is 1 LSTTL with a 50 pf (40 pf below 120 nsec cycle time) total load. All time intervals are recorded in nanoseconds. Although minimum time from IORDY high to HIOE# high is 0 nsec, the minimum HIOE# width is still met. HD refers to data provided by the CompactFlash Card to the system. Although adhering to the PCMCIA specification of 12 µs, the Wait Width time is intentionally lower in this specification. Timing Specification Figure 7 I/O Read Timing Diagram Table 10: I/O Write Timing 21 Rev. 1.2 Datasheet, Oct. 2011

22 Cycle Time Mode: 250ns 120ns 100ns 80ns Item Symbol Min ns. Max ns. Min ns. Max ns. Min ns. Max ns. Min ns. Max ns. Data Setup before HIOW# tsu(hiow) Data Hold following HIOW# th(hiow) HIOW# Width Time tw(hiow) Address Setup before HIOW# tsuha(hiow) Address Hold following HIOW# thha(hiow) CEx# Setup before HIOW# tsucex(hiow) CEx# Hold following HIOW# thcex(hiow) HREG# Setup before HIOW# tsuhreg(hiow) HREG# Hold following HIOW# thhreg(hiow) Wait Delay Falling from HIOW# 2 tdiordy(hiow) Na 1 HIOW# high from Wait high 2 tdrhiow(iordy) Na 1 Wait Width Time 2 tw(iordy) Na 1 Note: 1) IORDY is not supported in this mode. 2) The maximum load on IORDY is 1 LSTTL with a 50 pf (40 pf below 120 nsec cycle time) total load. All time intervals are recorded in nanoseconds. Although minimum time from IORDY high to HIOW# high is 0 nsec, the minimum HIOW# width is still met. HD refers to data provided by the CompactFlash Card to the system. Although adhering to the PCMCIA specification of 12 µs, the Wait Width time is intentionally lower in this specification. Figure 8 I/O Write Timing Diagram 22 Rev. 1.2 Datasheet, Oct. 2011

23 True IDE PIO Mode Read/Write Timing Specification Figure 9 Read/Write Timing Diagram, PIO Mode Note: 1) Device address comprises CE1#, CE2#, and HA[2:0]. 2) Data comprises HD[15:0] (16-bit) or HD[7:0] (8-bit). 3) IOCS16# is shown for PIO modes 0, 1, and 2. For other modes, this signal is ignored. 4) The negation of IORDY by the device is used to lengthen the PIO cycle. Whether the cycle is to be extended is determined by the host after ta from the assertion of HIOE# or HIOW#. The assertion and negation of IORDY is described in the following three cases. (a) The device never negates IORDY: No wait is generated. (b) Device drives IORDY low before ta: a wait is generated. The cycle is completed after IORDY is reasserted. For cycles in which a wait is generated and HIOE# is asserted, the device places read data on D15-D00 for trd before IORDY is asserted. Table 11: Read/Write Timing Specifications, PIO Mode 0-4 PIO timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 t0 Cycle time (min.) t1 Address valid to HIOE# / Rev. 1.2 Datasheet, Oct. 2011

24 HIOW# setup (min.) t2 HIOE# / HIOW# (min.) t2 t2i HIOE# / HIOW# (min.) Register (8-bit) HIOE# / HIOW# recovery time (min.) t3 HIOW# data setup (min.) t4 HIOW# data hold (min.) t5 HIOE# data setup (min.) t6 HIOE# data hold (min.) t6z HIOE# data tristate (max.) t7 t8 t9 trd Address valid to IOCS16# assertion (max.) n/a n/a Address valid to IOCS16# released (max.) n/a n/a HIOE# / HIOW# to address valid hold Read data valid to IORDY active (min.), if IORDY initially low after ta ta IORDY setup time tb IORDY pulse width (max.) tc IORDY assertion to release (max.) Note: All timings are in nanoseconds. The maximum load on IOCS16# is 1 LSTTL with a 50 pf (40 pf below 120 nsec cycle time) total load. All time intervals are recorded in nanoseconds. Although minimum time from IORDY high to HIOE# high is 0 nsec, the minimum HIOE# width is still met. 1) Where t0 denotes the minimum total cycle time; t2 represents the minimum command active time; t2i is the minimum command recovery time or command inactive time. Actual cycle time equals the sum of actual command active time and actual command inactive time. The three timing requirements for t0, t2, and t2i are met. The minimum total cycle time requirement is greater than the sum of t2 and t2i, implying that a host implementation can extend either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device s identity data. A CompactFlash Card implementation supports any legal host implementation. 2) This parameter specifies the time from the negation edge of the HIOE# to 24 Rev. 1.2 Datasheet, Oct. 2011

25 the time that the CompactFlash Card (tri-state) no longer drives the data bus. 3) The delay originates from HIOE# or HIOW# activation until the state of IORDY is first sampled. If IORDY is inactive, the host waits until IORDY is active before the PIO cycle is completed. When the CompactFlash Storage Card is not driving IORDY, which is negated at ta after HIOE# or HIOW# activation, then t5 is met and trd is inapplicable. When the CompactFlash Card is driving IORDY, which is negated at the time ta after HIOE# or HIOW# activation, then trd is met and t5 is inapplicable. 4) Both t7 and t8 apply to modes 0, 1, and 2 only. For other modes, this signal is invalid. 5) IORDY is not supported in this mode. True IDE Multiword DMA Mode Read/Write Timing Specification Figure 10 Read/Write Timing Diagram, Multiword DMA Mode Note: 1) If a card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ during the time from the start of a DMA transfer cycle (to suspend DMA transfers in progress) and reassertion of the signal at a relatively later time to continue DMA transfer operations. 2. The host may negate this signal to suspend the DMA transfer in progress. 25 Rev. 1.2 Datasheet, Oct. 2011

26 Table 12: Read/Write Timing Specifications, Multiword DMA Mode 0-2 Multiword DMA timing parameters Mode 0 Mode 1 Mode 2 t0 Cycle time (min.) td HIOE# / HIOW# assertion width (min.) te HIOE# data access (max.) tf HIOE# data hold (min.) tg HIOE# / HIOW# data setup (min.) th HIOW# data hold (min.) ti HREG# to HIOE# / HIOW# setup (min.) tj HIOE# / HIOW# to HREG# hold (min.) tkr HIOE# negated width (min.) tkw HIOW# negated width (min.) tlr HIOE# to DMARQ delay (max.) tlw HIOW# to DMARQ delay (max.) tm CEx# valid to HIOE# / HIOW# tn CEx# hold Note: Where t0 is the minimum total cycle time and td is minimum command active time, whereas tkr and tkw are minimum command recovery time or command inactive time for input and output cycles, respectively. Actual cycle time equals the sum of actual command active time and actual command inactive time. The three timing requirements of t0, i.e. td, tkr, and tkw, must be met. The minimum total cycle time requirement exceeds the sum of td and tkr or tkw for input and output cycles, respectively, implying that a host implementation can extend either or both td and tkr or tkw as deemed necessary to ensure that t0 equals or exceeds the value reported in the device's identity data. A CompactFlash Card implementation supports any legal host implementation. 26 Rev. 1.2 Datasheet, Oct. 2011

27 True IDE Ultra DMA Mode Read/Write Timing Specification Figure 11 Ultra DMA Mode Data-in Burst Initiation Timing Diagram Note: 1) All waveforms in this diagram are shown with the asserted state high. Negative true signals are inverted on the bus relative to the diagram. 2) The definitions for the IORDY:DDMARDY#:DSTROBE, HIOE#: HDMARDY#: HSTROBE and HIOW#: STOP signal lines are not in effect until DMARQ(#) and DMACK(#) are asserted. Notably, HA[2:0], CS0# and CS1# are True IDE mode signal definitions, and HA[10:0], CE1# and CE2# are PC Card mode signals. The Bus polarity of DMACK(#) and DMARQ(#) is based on the active interface mode. 27 Rev. 1.2 Datasheet, Oct. 2011

28 Figure 12 Ultra DMA Mode Data-out Burst Initiation Timing Diagram Note: 1) All waveforms in this diagram are shown with the asserted state high. Negative true signals are inverted on the bus relative to the diagram. 2) Definitions for STOP, DDMARDY#, and HSTROBE signal lines are not in effect until DMARQ(#) and DMACK(#) are asserted. The HA[2:0], CS0# and CS1# are True IDE mode signal definitions. The HA[10:0], CE1# and CE2# are PC Card mode signal definitions. Bus polarities of DMARQ(#) and DMACK(#) are dependent on the active interface mode. 28 Rev. 1.2 Datasheet, Oct. 2011

29 Figure 13 Sustained Ultra DMA Mode Data-in Burst Timing Diagram Note: HD[15:0] and IORDY signals are shown at both the host and device to emphasize that neither cable settling time nor cable propagation delay allow data signals to be considered stable at the host until after they are driven by the device. Figure 14 Sustained Ultra DMA Mode Data-out Burst Timing Diagram Note: Data (HD[15:0]) and HSTROBE signals are shown at both the device and host to emphasize that neither cable settling time nor cable propagation delay allow for data signals to be considered stable at the device until after they are driven by a host. 29 Rev. 1.2 Datasheet, Oct. 2011

30 Ultra DMA timing parameters t 2CYCTYP t CYC t 2CYC Table 13: Timing Diagram, Ultra DMA Mode 0-4 Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max t DS Data setup time (at recipient) t DH Data hold time (at recipient) Data valid setup time at sender (from t DVS t DVH t FS data bus being valid until STROBE edge) Data valid hold time at sender (from STROBE edge until data may become invalid) First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) t LI Limited interlock time t MLI Interlock time with minimum t UI Unlimited interlock time Maximum time allowed for output t AZ t ZAH drivers to release (from being asserted or negated) Minimum delay time required for output drivers to assert or negate (from released state) t ZAD t ENV t RFS Envelope time (from DMACK- to STOP and HDMARDY- during data out burst initiation) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY-) Rev. 1.2 Datasheet, Oct. 2011

31 t RP t IORDYZ t ZIORDY t ACK t SS Ready-to-pause time (time that recipient shall wait to initiate pause after negating DMARDY-) Pull-up time before allowing IORDY to be released Minimum time device shall wait before driving IORDY Setup and hold times for DMACK- (before assertion or negation) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) 5.6 Transfer Function I/O Transfer function The I/O transfer to or from the InnoLite EDC can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the signal IOIS16 is asserted by the InnoLite EDC. Otherwise, the IOIS16 signal is de-asserted. When a 16 bit transfer is attempted and the IOIS16 signal is not asserted by the InnoLite EDC, the system shall generate a pair of 8 bit references to access the word s even byte and odd byte. The InnoLite EDC permits both 8 and 16 bit accesses to all of its I/O addresses, so IOIS 16 is asserted for add address to which the InnoLite EDC responds. The InnoLite EDC may request the host to extend the length of an input cycle until data ready by asserting the WAIT signal at the start of the cycle. Table 14: PCMCIA Mode I/O Function Function Code -REG -CE2 -CE1 A0 -IORD -IOWR D15~D8 D7~D0 Standby Mode X H H X X X High Z High Z Byte Input Access (8 bits) Byte Output Access (8 bits) Word Input Access (16bits) Word Output Access (16bits) L L H H L L L H L L L H L L H L H L H H H H High Z High Z Even-Byte Odd-Byte L Don t Care Even-Byte L Don t Care Odd-Byte L L L L L H Odd-Byte Even-Byte L L L L H L Odd-Byte Even-Byte 31 Rev. 1.2 Datasheet, Oct. 2011

32 I/O Read Inhibit H X X X L H Don t Care Don t Care I/O Write Inhibit H X X X H L High Z High Z High Byte Input L L H X L H Odd-Byte High Z Only (8 bits) High Byte Output Only (8bits) L L H X H L Odd-Byte Don t Care Common Memory Transfer Function The Common Memory transfer to or from InnoLite EDC can be either 8 or 16 bits. The InnoLite EDC permits both 8 and 16 bit access to all of its Common Memory addresses. The InnoLite EDC request the host to extend the length of a memory write cycle or extend the length of a memory read cycle until data is ready by asserting the WAIT signal at the start of the cycle. Table 15: Common Memory Function Function Code -REG -CE2 -CE1 A0 -OE -WE D15~D8 D7~D0 Standby Mode X H H X X X High Z High Z Byte Read Access (8 bits) H H H H L L L H L L H H High Z High Z Even-Byte Odd-Byte Byte Write Access (8 bits) H H H H L L L H H H L L Don t Care Don t Care Even-Byte Odd-Byte Word Input Access H L L X L H Odd-Byte Even-Byte (16bits) Word Output Access H L L X H L Odd-Byte Even-Byte (16bits) Odd Byte Read Only H L H X L H Odd-Byte High Z (8 bits) Odd Byte Write Only (8bits) H L H X H L Odd-Byte Don t Care 32 Rev. 1.2 Datasheet, Oct. 2011

33 5.6.3 True IDE Mode I/O Transfer Function The InnoLite EDC can be configured in a True IDE Mode of operation. The InnoLite EDC is configured in this mode only when OE input signal is grounded by the host during the power off to power on cycle. Table 16: True IDE Mode I/O Function Function Code -CS1 -CS0 -A0~A2 -DMACK -IORD -IOWR D15~D8 D7~D0 L L X X X X Undefined Undefined In/Out In/Out Invalid Mode L X X L L X Undefined Out L X X L X L Undefined In X L X L L X Undefined Out X L X L X L Undefined In Undefined Out Undefined In Undefined Out Undefined In Standby Mode H H X H X X High Z High Z Task File Write H L 1-7h H H L Don t Care Data In Task File Read H L 1-7h H L H High Z Data In PIO Data Register Write H L 0 H H L Odd-Byte In Even-Byte In DMA Data Register Write H H X L H L Odd-Byte In Even-Byte In Ultra DMA Data Register Write H H X L See Note 1 Odd-Byte In Even-Byte In PIO Data Register Read H L 0 H L H Odd-Byte Out Even-Byte Out DMA Data Register Read H H X L L H Odd-Byte Out Even-Byte Out Ultra DMA Data Register Read H H X L See Note 2 Odd-Byte Out Even-Byte Out Control L H 6h H H L Don t Care Control In Register Write Alt Status Read L H 6h H L H High Z Status Out Drive Address L H 7h H L H High Z Data Out Note1: In Ultra DMA Data Register Write mode the signals IORD, -IOWR and IORDY are redefined 33 Rev. 1.2 Datasheet, Oct. 2011

34 and used as follows: -IORD as HSTROBE, -IOWR as STOP and IORDY as DDMARDY. Data transfers with each edge of HSTROBE. Note2: In Ultra DMA Data Register Read mode the signals IORD, -IOWR and IORDY are redefined and used as follows: -IORD as HDMARDY H, -IOWR as STOP and IORDY as DSTROBE. Data transfer with each edge of DSTROBE. 5.7 Configuration Register Configuration Option Register (200h in Attribute Memory) The Configuration Option Register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the InnoLite EDC. Table 17: Configuration Option Register Operation D7 D6 D5 D4 D3 D2 D1 D0 R/W SRESET LevelREQ Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 Table 18: Information for Configuration Option Register Name Description SRSET Soft Reset: Setting this bit to one (1), waiting the minimum reset time and returning to zero(0) places the InnoLite EDC in the reset state. Setting this bit to one (1) is equivalent to assertion of the +RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the InnoLite EDC in the same un-configured, Reset state as following power-up and hardware reset. This bit is PCMCIA Soft Reset is considered a hard Reset by the ATA Commands. Contrast with Soft Reset in the Device Control Register. LevelREQ This bit is set to one (1) then Level Mode Interrupt is selected, and zero (0) then Pulse Mode is selected. Set to zero (0) by Reset. Conf5-0 Configuration Index: Set to zero (0) by reset. It is used to select operation mode of the InnoLite EDC as shown below Note: Conf5 and Conf4 are reserved for CompactFlash Storage cards and shall be written as zero(0). Table 19:InnoLite EDC Configuration Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 Disk Card Mode Memory Mapped I/O Mapped, Any 16 byte system decoded boundary 34 Rev. 1.2 Datasheet, Oct. 2011

35 Primary I/O Mapped, 1F0h~1F7h/3F6h ~ 3F7h Secondary I/O Mapped, 170h~177h/376h ~ 377h Card Configuration and Status Register (202h in Attribute Memory) The Card configuration and Status Register contains information about the Card s condition. Table 20: Card Configuration and Status Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Changed SigChg IOis8 0 0 PwrDwn Int 0 Write 0 SigChg IOis8 0 0 PweDwn 0 0 Table 21: Information for Card Configuration and Status Register Name Description Changed Indicates that one or both of the Pin Replacement register CReady. Or CWProt bits are set to one(1). When the changed bit is set. STSCHG Pin 46 us held low if the SigChg bit is a One(1) and the InnoLite EDC is configured for I/O interface. SigChg This bit is set and reset by the host to enable and disable a state-change single from the Status Register, the Changed bit controls pin 46, the Changed Status single. If no state change single is descried, this bit is set to zero(0) and pin46 (-STSCHG) single is then held high while the InnoLite EDC is configured for I/O. IOis8 The host sets this bit to one (1) if the InnoLite EDC is to be configured in an 8 bit I/O Mode. The InnoLite EDC is always configured for both 8 and 16 bit I/O, so this bit is ignored. PwrDwn This bit indicates whether the host requests InnoLite EDC to be in the power saving or active mode. When the bit is one (1), the InnoLite EDC enter a power down mode. The PwrDwn is zero (0), the host is requesting the InnoLite EDC to enter the active mode. The PCMCIA READY value becomes false (busy) when this bit is changed. READY shall not become true (ready) until the power state requested has been entered. The InnoLite EDC automatically powers down when it is idle and powers back up when it receives a command. 35 Rev. 1.2 Datasheet, Oct. 2011

36 Int This bit represents the internal state of the interrupt request. This value is available whether or not the I/O interface has been configured. This signal remains true until the condition that caused the interrupt request has been serviced. If interrupts are disabled by the IEN bit in the Device Control Register, this bit is a zero (0) Pin Replacement register (204h in Attribute Memory) Table 22: Pin Replacement Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read 0 0 CReady RReady 0 Write 0 0 CReady MReady 0 Name CReady RReady MReady Table 23: Information for Pin Replacement Register Description This bit is set to one (1) when the bit RReady changes state. This bit can also be written by the host. This bit is used to determine the internal state of the READY signal. This bit may be used to determine the state of the READY signal as this pin has been reallocated for use as Interrupt Request on an I/O card. When written, this bit acts as a mask(mready) for writing the corresponding bit CReady. This bit acts as a mask for writing corresponding bit CReady Socket and Copy Register (206h in Attribute Memory) This register contains additional configuration information. This register is always written by the system before writing the card s Configuration Index Register. This register is used for identification of the card from the other card. Table 24: Socket and Copy Register Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Obsolete (Drive #) Write Obsolete (Drive #) X X X X 36 Rev. 1.2 Datasheet, Oct. 2011

37 Table 25: Information for Socket and Copy Register Name Description Obsolete(Drive #) This bit is obsolete and should be written as Software Interface CF-ATA Drive Register Set Definition and Protocol The InnoLite EDC can be configured as a high performance I/O device through: a) The standard PC-AT disk I/O address 1F0h-1F7h, 3F6h-3F7h (primary) or 170h-177h, 376h-377h (secondary) with IRQ14 (or other available IRQ). b) Any system decode 16 byte I/O block using any available IRQ. c) Memory space The communication to or from the card is done using the Task File register, which provide all the necessary register for control and status information related to the storage medium. The PCMCIA interface connects peripherals to the host using four register mapping methods. Table 26: I/O Configuration Standard Configurations Config Index I/O or Memory Address Description 0 Memory 0h-Fh, 400h-7FFh Memory Mapped 1 I/O XX0h-XXFh I/O Mapped 16 Contiguous Registers 2 I/O 1F0h-1F7h, Primary I/O 3F6h-3F7h Mapped 3 I/O 170h-177h, Secondary I/O 376h-377h Mapped I/O Primary and Secondary Address Configurations Table 27: Primary and Secondary I/O Decoding -REG A9-A4 A3 A2 A1 A0 -IORD=0 -IOWR=0 Note 0 1F(17)h Even RD Data Even WR Data 1,2 0 1F(17)h Error Register Features 1,2 0 1F(17)h Sector Count Sector Count 0 1F(17)h Sector No. Sector No. 0 1F(17)h Cylinder Low Cylinder Low 0 1F(17)h Cylinder High Cylinder High 37 Rev. 1.2 Datasheet, Oct. 2011

38 0 1F(17)h Select Card/Head Select Card/Head 0 1F(17)h Status Command 0 3F(37)h Alt Status Device Control 0 3F(37)h Drive Address Reserved Note 1) Register 0 is accessed with CE1 low and CE2 low ( and A0=Don t care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte access to the offset 0 with CE1 low and CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers, which lie at offset 1. When accessed twice as byte register with CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. Note2) A byte access to register 0 with CE1 high and CE2 low access the error (read) or feature (write) register Contiguous I/O Mapped Addressing When the system decodes a contiguous block of I/O registers to select the card, the registers are accessed in the block of I/O space decoded by the system as follows: Table 28: Contiguous I/O Decoding -REG A3 A2 A1 A0 Offset -IORD=0 -IOWR=0 Note Even RD Data Even WR Data Error Features Sector Count Sector Count Sector No. Sector No Cylinder Low Cylinder Low Cylinder High Cylinder High Select Card/Head Select Card/Head Status Command Dup Even RD Data Dup. Even WR 2 Data Dup. Odd RD Data Dup. Odd WR 2 Data D Dup. Error Dup. Feature E Alt Status Device Ctl F Drive Address Reserved Note 1) Register 0 is accessed with CE1 low and CE2 low (and A0=Don t care) as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte access to the offset 0 with CE1 low and CE2 high. Note that the address space of this 38 Rev. 1.2 Datasheet, Oct. 2011

39 word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. Note 2) A byte access to register 0 with CE1 high and CE2 low access the error (read) or feature (write) register. Note 3) Address lines that are not indicated are ignored by the card for accessing all the registers in this table Memory Mapped Addressing When the card registers are accessed via memory references, the register appears in the common memory space window: 0-2K bytes as follows: Table 29: Memory Mapped Decoding -REG A10 A9-A4 A3 A2 A1 A0 Offset -OE=0 -WE=0 Note 1 0 X Even RD Even WR 1,2 Data Data 1 0 X Error Features 1,2 1 0 X Sector Count Sector Count 1 0 X Sector No. Sector No. 1 0 X Cylinder Low Cylinder Low 1 0 X Cylinder High Cylinder High 1 0 X Select Card/Head Select Card/Head 1 0 X Status Command 1 0 X Dup Even Dup. Even 2 RD Data WR Data 1 0 X Dup. Odd Dup. Odd 2 RD Data WR Data 1 0 X D Dup. Error Dup. 2 Feature 1 0 X E Alt Status Device Ctl 1 0 X F Drive Address Reserved 1 1 X X X X 0 8 Even RD Even WR 3 Data Data 1 1 X X X X 1 9 Odd Rd Data Odd WR 3 39 Rev. 1.2 Datasheet, Oct. 2011

40 Data Note 1) Register 0 is accessed with CE1 low and CE2 low as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte access to the offset 0 with CE1 low and CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte accesses to register 0 with CE1 high and CE2 low access the error (read) or feature (write) register. Note 2) Register at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the register is byte accessed in the order 9 then 8 the data shall be transferred odd byte then even byte. Repeated byte accessed to register 8 or 0 shall access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 shall access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to register 8 then 9 shall access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. Note 3) Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1 K byte memory window to the data register is provide so that hosts can perform memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to memory block move instruction, Some PCMCIA socket adapters also have auto incrementing address logic embedded within them. This address window allows these hosts and adapters to function efficiently. Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the card. A word access to address at offset 8 shall provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high-order byte of the bus True IDE Mode Addressing When the InnoLite EDC is configured in the True IDE mode, the I/O decoding is as follows: 40 Rev. 1.2 Datasheet, Oct. 2011

41 Table 30: True IDE Mode I/O Decoding -CS1 -CS0 A2 A1 A0 -DMACK -IORD=0 -IOWR=0 Note PIO RD Data PIO WR Data 8 or 16 bit 1 1 X X X 0 DMA RD Data DMA WR Data 16 bit Error Register Features 8 bit Sector Count Sector Count 8 bit Sector No. Sector No. 8 bit Cylinder Low Cylinder Low 8 bit Cylinder High Cylinder High 8 bit Select Select 8 bit Card/Head Card/Head Status Command 8 bit Alt Status Device Control 8 bit CF-ATA Register The following section describes the hardware registers used by the host software to issue commands to the InnoLite EDC. Note: In accordance with the PCMCIA specification: each of the registers below that is located at an odd offset address may be accessed in the PC Card Memory or PC Card I/O modes at its normal address and also the corresponding even address (normal address -1) using data bus lines (D15-D8) when CE1 is high and CE2 is low unless IOIS16 is high (not asserted by the card) and an I/O cycle us being performed. In True IDE Mode of operation, the size of the transfer is based solely on the register being addressed. All registers are 8 bit only except for the Data Register, which is normally 16 bits, but can be programmed to use 8 bit transfers for Non-DMA operations through the use of the Set Features command. The data register is also 8 bits during a portion of the Read Long and Write Long commands, which exist solely for historical reasons and should not be used. Data Register The Data Register is a 16 bit register, and it is used to transfer data blocks between the card and the host. This register overlaps the Error Register. This register can be accessed in word and byte mode. 41 Rev. 1.2 Datasheet, Oct. 2011

42 Data Register Table 31: Data Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Error Register This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined as follows: Table 32: Error Register BBK UNC 0 IDNF 0 ABRT 0 AMNF D7 D6 D5 D4 D3 D2 D1 D0 Feature Register This register provides information regarding features of the card that the host can utilize. This register is also accessed in PC Card modes on data D15-D8 during a write operation to Offset 0 with CE2 low and CE1 high. Feature Register Table 33: Feature Register D7 D6 D5 D4 D3 D2 D1 D0 Sector Count Register This registers the number of sectors of data requested to be transferred on a read or write operation between the host and the card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. Sector Count Register Table 34: Sector Count Register D7 D6 D5 D4 D3 D2 D1 D0 Sector Number Register This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for InnoLite EDC data access for the subsequent command. Sector Number Register Table 35: Sector Number Register D7 D6 D5 D4 D3 D2 D1 D0 42 Rev. 1.2 Datasheet, Oct. 2011