Virtual Memory. Stefanos Kaxiras. Credits: Some material and/or diagrams adapted from Hennessy & Patterson, Hill, online sources.

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1 Virtual Memory Stefanos Kaxiras Credits: Some material and/or diagrams adapted from Hennessy & Patterson, Hill, online sources.

2 Caches Review & Intro Intended to make the slow main memory look fast by automatically copying useful data in fast memory Fundamental Principle: Locality of reference (temporal & spatial) Programs tend to spend their time on small subsets of the memory What is Virtual Memory? BUT: VM is much more than this! Intended to expand main memory, using the disk as Offers a much each process larger its albeit slower storage medium own ADDRESS SPACE Speed differential cache-to-mem & Protection! mem-to-disk changes many of the tradeoffs! FAST VAST CPU Cache (fast) Memory (DRAM-slow) DISK Virtual memory x-x 5 x

3 History & Motivation Historical need Main memory & addresses started small... Need to run programs bigger than main memory Overlays: programmer orchestrates the movement of code and data in and out of main memory (from secondary storage) in the same address space Ouch! Need to expand memory automatically BUT: Physical Memory The solution!= Address (ATLAS, Space 96): Virtual Physical Memory Memory is what Illusion you have that (buy) each program has Address space There the is whole what is only address your one mistake program space that available is can allowed be made to it in to on computer have by design the ISA that its own is difficult to recover from not having enough address Corollary: bits start for memory with a huge addressing address and memory space management. or else you ll need a new Gordon ISA Bell fast and Bill Strecker PDP 8, speaking,, about Intel the 886, PDP- 886, in 886, etc Map multiple address spaces on: (a much 976 Programs live in the smaller) address physical space, memory can + be (a big, much expand, contract (stack, heap), larger) but disk, typically automatically use only a small part at any time (locality) highly dynamic behavior How to map address spaces on to memory & manage it?

4 Virtual memory: map DRAM (Virtual) Pages Virtual ADDRESS SPACE Page Frames or Physical Pages How to do it: Divide Virtual address space & mem into fixedsized blocks (e.g., KB, MB): Pages & Page frames (e.g., KB) Alternatively: variable-sized blocks called Segments DISK Swap file

5 Virtual memory: map DRAM Virtual ADDRESS SPACE (H&P Q) Where Can a Page (Block) Be Placed in Main Memory? How to do it: In VM: anywhere FULLY Divide Virtual address space ASSOCIATIVE & mem into fixedsized blocks (e.g., KB, MB): Pages & Page frames Contrast (e.g., KB) w/ Caches: Fixed place for Keep the hot pages of a block the program (Direct-Mapped) in memory within a The rest on disk set (Set-Assoc.) Transparency: program does not differentiate RAM or DISK Hot (active) pages go to memory (H&P Q) How is a Page (Block) Found IF It Is in Main Memory? Cold (rarely used) pages go In Caches: Matched TAGS to DISK BUT VM is FA! (would need to search ALL tags) DISK Instead: Use an INDIRECTION TABLE!

6 Virtual memory: map One-to-One DRAM Virtual ADDRESS SPACE Page Table DISK Loc: DISK Loc: 5 DISK Loc: 6 7 R D Page Frame or Disk loc. How to do it: All we need to make it work is an Indirection Table called a Page Table Foreach virtual page shows its location: In RAM page frame (physical page number) On disk location on disk Additional bits in page table entries: Resident, Dirty, Valid (not shown), protection bits (not shown) DISK Hot (active) pages go to memory Cold (rarely used) pages go to DISK

7 Virtual memory: map multiple Another Virtual ADDRESS SPACE Another Page Table Page Table DISK Loc: DISK Loc: DISK Loc: DISK Loc: Protection: different programs occupy different address spaces VM keeps the page mappings separate! DRAM DISK Hot (active) pages go to memory Cold (rarely used) pages go to DISK More on protection later

8 Virtual memory: automatically CPU issues Virtual Addresses (VA): V Page Offset Virtual ADDRESS SPACE Page Table DISK Loc: DISK Loc: DRAM Hot (active) pages go to memory Page Frame or Disk loc. Programs live in the Virtual address space CPU issues virtual addresses Composed of a virtual page number (highorder address bits) Offset within the page (low order bits) But really want to go to main memory R D DISK Loc: DISK Cold (rarely used) pages go to Disk

9 Virtual memory: automatically CPU issues Virtual Addresses (VA): V Page Offset P Page Offset Page Table DISK Loc: DISK Loc: Physical Address (PA) DRAM Hot (active) pages go to memory Page Frame or Disk loc. ADDRESS TRANSLATION: VA PA Index the Page Table with the virtual page # If resident PT gives page frame # Access the physical page at that frame and use the same offset to get what you want Common case that needs to happen FAST! R D DISK Loc: DISK Cold (rarely used) pages go to DISK

10 Virtual memory: automatically CPU issues Virtual Addresses (VA): V Page Offset Page Table DISK Loc: PAGE FAULT Index the Page Table with the (H&P virtual Q) Which page Block # Should R DBe If not resident PT gives DISK Replaced loc. on a Virtual Memory Miss? Need to bring in the page from the disk! Page Frame or UNCOMMON case that is delegated to SW OS Disk loc. Important to get it right! manages this:. Make an empty frame Latency (LRU, is Clock, not an WS, issue, done by SW see your OS course!) (OS). Replace old page with requested page. Patch the PT with the Contrast new location w/ Caches: of the do it fast use page. Restart the access pseudo-lru or simpler in SA DISK Loc: DISK Loc: DRAM Bring in the new page Patch the PT (H&P Q) What Happens on a Write? VM is strictly write-back Writing through to disk on every store to memory is simply too much! Dirty pages (D-bit set) selected for DISK replacement need to be written back to disk.

11 Sanity check # Address translation via the page table needs to happen fast How big is this page table? Example IA: bit Addr space, GB/KByte pages = M entries bit bits for offset = bits page# Need ~bytes per entry (bit frame number & control bits) MB needed for page table Fit in SRAM? Put in main memory! IA Example: bit addresses KB Pages ( bits) bit V Page (M pages, GB) Up to bit P Page (M pages, GB) bits bits

12 Fast Address Translation: the TLB Even Worse when we have caches! But we know how to solve this: Cache the page table entries! Could be done in the cache but same problem accesses A better solution: Translation Lookaside Buffer (TLB) Small: 6-8entry, fully associative (low miss rate), strong locality Tagged with virtual page numbers Hit returns the physical page number Miss loads the PPN from the page table and associates with VPN. Advantages: address translation separate from cache access all entries in one place (TLB shootdown, flush, purge, invalidate) protection & control bits handy Address Translation Address in Translation the TLB via PT in Memory TLB Address Translation via cached PT CPU Cache (fast) Memory (DRAM-slow) V Page P Page P bits Tag Result

13 Hiding address translation Physical Cache Virtual Cache Virtually indexed, Physically Tagged VA PA PA CPU TLB Cache (L) Memory VA VA PA CPU Cache (L) TLB Memory CPU Cache blk bits V Page Offset TLB Cache (L) hit P Page =? P TAG VA PA miss Memory Tags are Virtual addr. Tags are Physical addr. Penalize only cache misses All programs use same VAs: Penalize all cache Same VAs referring to different PAs Accesses! Synonym problem: Different VAs referring to Same PA Deleting page mappings, Coherence (TBD in the next course)! Tags are Physical but cache is indexed w/ Virtual: Best of both worlds But: limits index to un-translated Offset can expand cache size via Assoc or exceed this limit and handle synonyms (AMD does this )

14 Interim Summary VM Exploiting locality on a large scale and offering protection at the same time Programmers want a large, flat address space but they ll use it sparsely, unpredictably! Key fetures: Offer each program is own virtual address space Demand Page sparse working set into RAM from DISK Key implementation issues: Mapping is Fully Associative need an indirection table, the Page Table Address translation needs to happen fast cache the page table into a specialized buffer, the TLB Can be further hidden behind the L cache access Page faults are slow and best handled by the OS VM essential in modern computers

15 Protection Basic tenet for protection: Separation of user space and supervisor (superuser, OS) space Programs can play in their sandbox but are not allowed to touch others OS: unrestricted privileges VM offers protection: by separating the address spaces of programs each program is given its own page table (mapping) which is wholly controlled by the OS by differentiating among User/Super pages & RO/RW pages How is it done?

16 Protection: How it is done (in Linux, Windows, ): GB address space (-bit IA) DRAM User pages USER GB Page table u s OS pages User program cannot touch these! Supervisor OS GB U/S bit

17 Protection: How it is done (in Linux, Windows, ): GB address space (-bit IA) DRAM User pages USER USER GB GB u Page table u s s OS pages Supervisor OS GB U/S bit Page Tables differ only in their upper part (user space) The OS part is identical

18 Protection: How it is done (in Linux, Windows, ): GB address space (-bit IA) DRAM User pages USER USER GB GB OS pages Sanity Check # How big Supervisor are these page table? A: MB for OS bit A.S. We need many GB(one per process) Another example: 6bit AS Alpha 6 maps ^8 pages GB page table! Still need multiple of those But they are mostly empty PAGE THE PAGE TABLES TOO!!! u u s s Another Reason Why This Is Not Simply Just a Good Idea But a Must! OS is only-one that can touch the page tables The Page Table Maps and Pages Itself! But the OS is also a program living in a Virtual Address Space Page Tables Need to APPEAR in OS s VM! and as such are also subject to PAGING

19 Paging the Page Table: -level hierarchical page tables VA V Page Offset bits Page Table Physical Address Space (DRAM) P. Page VPage ( bits) index IA Example: bit addresses KB Pages ( bits) bit V Page (M pages, GB) Up to bit P Page (M pages, GB) M entries x Bytes/entry MB (bit P.Page + protection/control bits = Bytes)

20 Paging the Page Table: -level hierarchical page tables (cont.) V Page VA Offset Page Table PT PAGE entries: KB Physical Address Space (DRAM) Divide the Page table Into KB Pages PT PAGE entries: KB PT PAGE entries: KB M entries x Bytes/entry MB (bit P.Page + protection/control bits = Bytes) KB tables MB

21 Paging the Page Table: -level hierarchical page tables (cont.) V Page VA Offset Page Table Physical Address Space (DRAM) Map the pages on Physical Mem

22 Paging the Page Table: -level hierarchical page tables (cont.) V Page VA Offset Page Table Physical Address Space (DRAM) There is a special Page Table Page Page Table Directory or Root Page Table: entries, KB, page Directory Just changing the CR (pointing to another directory in physical memory) changes the whole page table! Tells us where the pages of the PAGE TABLE are (The TLB is flushed and reload anew) CR PA Looks Familiar? It sure does, it s the same as the mapping of a virtual address space only just MB (instead of GB) are mapped Itself mapped (always resident) in Physical memory It s Location in Physical Memory is known, and held in a special register (let s call it CR) The only Physical Address inside the processor!!

23 Address Translation in -level hierarchical page tables (cont.) VA V Page bits bits bits Dir entry PT entry Offset Page Table + Physical Address Space (DRAM) Offset Directory bits + bits PT entry CR + + Dir entry + + CR Can be generalized to more levels (e.g., ALPHA cah have or levels) TLB operation remains unaffected! Still pairs VPage (bits) to (the final) PPage

24 Paging in Windows Page Table (MB) USER KERNEL VIRTUAL x x x x x x5 x6 x7 x8 WinNT x9 xa xb xc xd xe xf MB 6 x MB Pages (56MB) Mapped - xc xcfffff (MB) KB xc Physical x x x x x x5 x6 x7 x8 x9 xa xb xc xd xe xf The Directory is the PT Page that maps the MB of where the PT resides in VM

25 Summary VM Exploiting locality on a large scale and offering protection at the same time Programmers want a large, flat address space but they ll use it sparsely, unpredictably! Key fetures: Offer each program is own virtual address space Demand Page sparse working set into RAM from DISK Key implementation issues: Mapping is Fully Associative need an indirection table, the Page Table Address translation needs to happen fast cache the page table into a specialized buffer, the TLB Can be further hidden behind the L cache access Page faults are slow and best handled by the OS Protection from multiple address spaces, protected OS pages, individual access rights per page Protection comes from the fact that only the OS can touch page tables Page tables need to be paged too! For size and OS virtual access multi-level page tables, with page tables for the page table, called directories VM essential in modern computers

Virtual Memory Fall /19/0. L21 Virtual Memory 1

Virtual Memory Fall /19/0. L21 Virtual Memory 1 Virtual Memory L21 Virtual Memory 1 Lessons from History There is only one mistake that can be made in computer design that is difficult to recover from not having enough address bits for memory addressing