Virtual Memory, Address Translation
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1 Memory Hierarchy Virtual Memory, Address Translation Slides contents from: Hennessy & Patterson, 5ed Appendix B and Chapter 2 David Wentzlaff, ELE 475 Computer Architecture MJT, High Performance Computing, NPTEL
2 Process/Program Address Space Byte Address 0 CODE DATA HEAP Compiler assumes a linear address space Byte 0 to Byte Virtual Address space The entire process data structure is may not be present in MM at all times STACK
3 MAIN MEMORY MAIN MEMORY HARD DISK HARD DISK Paged Virtual Memory Page Number 0 Byte Virtual Address Space 0 Virtual Page Number 0 Virtual Page Number 1 Physical Address Space Page Number 13 Page Number 1 Page Number Virtual Page Number N-1 Page Number N-1
4 The Memory Hierarchy Virtual Virtual Addresses Addresses Physical Physical Addresses Addresses Main memory Virtual memory Registers Cache Words (transferred explicitly via load/store) Lines (transferred automatically upon cache miss) Pages (transferred automatically upon page fault) Virtual Virtual Addresses Addresses
5 Address Translation Table Virtual Address VPN PO VPN 0 VPN 1 Physical Page Numbers PPN 0 PPN PPN PO Physical Address VPN N-1
6 Paged Virtual Memory 48 bit Virtual Addresses, 40 bit Physical Addresses Page size = 16KB How many entries in a process's Page Translation Table? What is the size of the Page Translation Table?
7 Virtual Memory
8 Address Translation Table MAIN MAIN MEMORY HARD DISK DISK Virtual Address VPN PO VPN 0 VPN 1 Physical Page Numbers Disk Addresses V PPN Disk Address PPN PO Physical Address VPN N
9 Implementation of Address Translation Process always uses virtual addresses Memory Management Unit (MMU): part of CPU; hardware that does address translation Caches recently used translations in a Translation Lookaside Buffer (Page Table Cache) The page tables are stored in OS's virtual address space The page tables are (at best) present in the MM One main memory reference per address translation! To translate a virtual memory address, the MMU has to read the relevant page table entry out of memory
10 Virtual Memory Page Faults Situation where virtual address generated by processor is not available in main memory Detected on attempt to translate address Page Table entry is invalid Must be `handled by operating system Identify slot in main memory to be used Get page contents from disk Update page table entry Data can then be provided to the processor
11 Caches and Address Translation Physically Addressed Cache CPU Virtual Address MMU Physical Address Cache CPU Virtual Address Cache Cache Miss MMU Physical Address Main Memory Virtually Addressed Cache
12 Which is less preferable? Physical addressed cache Hit time higher (cache access after translation) Virtual addressed cache Data/instruction of different processes with same virtual address in cache at the same time Flush cache on context switch, or Include Process id as part of each cache directory entry Synonyms Virtual addresses that translate to same physical address More than one copy of a block in cache
13 Synonyms (Aliases) VA-T1 P1 t1 P2 t2 VA-T2 Shared L2 L2 uses virtual addresses T1 and T2 share data from page X X 2 copies of of one physical page in in the the cache!
14 Overlapped Operation MMU CPU Virtual Address Indexing using VA Cache Tag check using PA Virtually Indexed Physically Tagged Cache (VIPT) Other options: PIPT, PIPT, VIVT VIVT
15 Recall Cache Access Direct mapped, 32 KB, 32B block, 32b main memory address Tag Tag b address Index (15b) (15b) 3 Offset 2 Tag is not needed until the cache line has been read W 1 32B 32B W 2 Block 7 W 8 No Cache Miss =? Yes Cache Hit W 1 W 2 7 W 8 To Processor
16 64 b VM address VM Example Virtual Page No (50) Page Offset (14) (43) TLB Tag (7) TLB Index Index (8) Offset (6) (26) Physical Address (Tag) (Tag) Cache Block =? TLB Hit/ Page Fault Physical Address (40) =? L1 Hit/Miss To L2 Tag Index Offset Index comes from the Virtual Address (Virtually Indexed) Tag comes from the Physical Address (Physically tagged) =? L2 L2 Cache Block
17 Fast Translation Address translation is on the critical path Paging 2 memory accesses! Address Translation Table + Data Translation Lookaside Buffer (TLB): Part of MMU that caches address translations
18 Translation Lookaside Buffer Cache of page table mappings entries long SA, FA, or DM Dirty flag use during page write back Ref used for LRU VPN (tag) PPN (data) Valid Ref Dirty Access Rights
19 Size of a Page Page is the unit of Memory Management Too large vs Too small Page Offset field need not be translated What if the Page Offset field was 12 bits? (Page size = 4KB)
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