LMR14050 LMZ20502 LMZ20502

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1 PMP10743-Test Report Wide V IN, 3 Output Rail Design LMR14050 SIMPLE SWITCHER Converter LMZ20502 SIMPLE SWITCHER Nano Module Overview The reference design below shows the wide input voltage capability, simple layout, and small solution size of the LMR14050 SIMPLE SWITCHER Buck Converter and the LMZ20502 Nano Module. Figure 1 can be seen below and shows the block diagram for this design. The LMR14050 provides a 5V output rail which feeds into two LMZ20502 Nano Modules. The modules provide a 3.3V and a 1.8V rail. The 5V, the 3.3V, and the 1.8V rails are capable of delivering a maximum of 2A load at their respective output voltages. 7V 40V Input 5V 2A LMR V 5A Wide-Input Buck Converter 3.3V 2A LMZ V 2A Nano Module 1.8V 2A Figure 1. Block Diagram LMZ V 2A Nano Module 1

2 Table of Contents Overview... 1 Design Specifications... 3 Schematic... 3 Board Layout... 4 Bill Of Materials... 9 Other Design Details Controlling Precision Enable Setting Switch Frequency Typical Performance Converter Efficiency at Various Loads Startup Shutdown Output Voltage Ripple Load Transients Line Transients Thermal Performance with Various Input Voltages and Loads

3 1 2 3 PMP10743 Wide VIN, 3 Output Rail Design Design Specifications Input Voltage: 7V to 40V Output 1 Voltage: 5V Output 1 Current: 2A Output 2 Voltage: 3.3V Output 2 Current: 2A Output 3 Voltage: 1.8V Output 3 Current: 2A Schematic VIN VIN Cin1 68µF Cin2 4.7µF J1 1 2 Cin3 4.7µF PEC02SAAN J2 1 2 PEC02SAAN Cin4 0.22µF R1 432k R2 86.6k Vin En RT/SYNC 6 SS R3 59.0k U1 VIN EN RT/SYNC SS BOOT LMR14050SDDAR Css 0.01µF 1 SW 8 5 FB FB 7 9 PAD Cb BOOT 0.1µF SW L D1 PDS Cout4 1µF Cout1 100µF Cout2 100µF Cout3 100µF Rfbt1 53.6k Rfbb1 9.53k Cin5 10µF Cin6 10µF U2 VIN EN MODE VOUT FB PG Vout_3.3 FB_3.3 PG_3.3 Rfbt2 237k Vout Cff1 82pF Cout5 10µF 5V, 2A Vout=5V 3.3V, 2A Vout=3.3V JVout_ JVout_ NC_3.3 7 NC EP LMZ20502SIL 6 9 Rfbb2 53.6k Cin7 10µF Cin8 10µF U3 8 VIN 2 EN 3 MODE VOUT FB PG Vout_1.8 FB_1.8 PG_1.8 Rfbt3 80.6k Cff2 16pF Cout6 10µF 1.8V, 2A Vout=1.8V JVout_ NC_1.8 7 NC EP LMZ20502SIL 6 9 Rfbb3 40.2k Figure 2. Schematic 3

4 Board Layout Figure 3. PCB Layout (3D View) 4

5 Figure 4. Top Layer Copper with Top Overlay and Top Solder 5

6 Figure 5. Mid Layer 1 Copper 6

7 Figure 6. Mid Layer 2 Copper 7

8 Figure 7. Bottom Layer Copper 8

9 Bill of Materials Qty Reference Part Description Manufacturer 1 Cb CAP, CERM, 0.1 µf, 25 V, +/- 10%, X7R, Cff1 CAP, CERM, 82 pf, 50 V, +/- 5%, C0G/NP0, Cff2 CAP, CERM, 16 pf, 50 V, +/- 5%, C0G/NP0, Cin1 CAP, Polymer, 68 µf, 50 V, +/- 20%, 0.02 ohm, F12, SMD, 2- Leads, Body 10.5x10.5mm, Height 12.7mm SMD MuRata AVX MuRata Panasonic Manufacturer Part Number GRM188R71E104KA01D 06035A820JAT2A GRM1885C1H160JA01D 50SVPF68M 2 Cin2, Cin3 CAP, CERM, 4.7 µf, 50 V, +/- 10%, X7R, Cin4 CAP, CERM, 0.22 µf, 50 V, +/- 10%, X7R, Cin5, Cin6, Cin7, Cin8, Cout5, Cout6 CAP, CERM, 10 µf, 16 V, +/- 20%, X5R, 0603 MuRata TDK Taiyo Yuden GRM32ER71H475KA88L C1608X7R1H224K080AB EMK107BBJ106MA-T 3 Cout1, Cout2, Cout3 CAP, CERM, 100 µf, 10 V, +/- 20%, X5R, 1206_190 1 Cout4 CAP, CERM, 1 µf, 16 V, +/- 10%, X5R, Css CAP, CERM, 0.01 µf, 16 V, +/- 10%, X7R, D1 Diode, Schottky, 45 V, 10 A, PowerDI5 3 FID1, FID2, FID3 Fiducial mark. There is nothing to buy or mount. 4 H1, H2, H3, H4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead TDK MuRata MuRata Diodes Inc. N/A B&F Fastener Supply C3216X5R1A107M160AC GRM188R61C105KA93D GRM188R71C103KA01D PDS N/A 4 H5, H6, H7, H8 Standoff, Hex, 0.5"L #4-40 Nylon Keystone 1902C 2 J1, J2 Header, 100mil, 2x1, Tin, TH Sullins Connector Solutions 4 JVout_1.8, JVout_3.3, JVout_5, TP9 Standard Banana Jack, Insulated, Red Keystone 6091 NY PMS PH PEC02SAAN 1 L1 Inductor, Shielded Drum Core, Superflux, 5.5 µh, 10 A, ohm, SMD Wurth Elektronik R1 RES, 432 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW KFKEA 1 R2 RES, 86.6 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW060386K6FKEA 1 R3 RES, 59.0 k, 1%, W, 0805 Vishay-Dale CRCW080559K0FKEA 1 Rfbb1 RES, 9.53 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW06039K53FKEA 9

10 2 Rfbb2, Rfbt1 RES, 53.6 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW060353K6FKEA 1 Rfbb3 RES, 40.2 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW060340K2FKEA 1 Rfbt2 RES, 237 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW KFKEA 1 Rfbt3 RES, 80.6 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW060380K6FKEA 4 TP1, TP3, TP5, TP7 4 TP2, TP4, TP6, TP8 4 TP10, Vout=1.8V, Vout=3.3V, Vout=5V Standard Banana Jack, Insulated, Black Keystone 6092 Test Point, Compact, Black, TH Keystone 5006 Test Point, Compact, Red, TH Keystone U1 LMR14050SDDAR, DDA0008E Texas Instruments 2 U2, U3 2A Buck Simple Switcher Nano Texas Module, SIL0008F Instruments LMR14050SDDAR LMZ20502SIL 10

11 Other Design Details Controlling Precision Enable The enable jumper J1 on the PCB allows the user to gain control of the precision enable pin on the IC. By adjusting the values of R1 and R2, one can appropriately set the turn on and off thresholds of the converter. When the internal precision enable pin is pulled below 1.2V, the converter is shut off. The converter will delay its turn on until VIN reaches about 7V. By adding a resistor divider, the converter avoids attempting to regulate when the input voltage is too low to provide the proper output. As a result, the IC avoids current limiting the power supply during startup. Figure 8. Controlling Turn-on Threshold 11

12 Setting the Switch Frequency By changing the value of R3, the switching frequency of the LMR14050 can be adjusted and set to the desired value for the user s application. The switching frequency can also be controlled from 250kHz to 2.3MHz by hooking up an external clock to the SYNC pin J2. Refer to the LMR14050 datasheet for more information on connecting an external clock. Figure 9. Setting Switch Frequency 12

13 Typical Performance Converter Efficiency at Various Loads Figure 10. Efficiency 13

14 Startup Figure 11. Startup at 12V Input The 5V output ramps up first and enables both Nano Modules. The Nano Module s enable is tied to its VIN pin. As seen from Figure 9, each module is enabled when the output from the LMR14050 reaches about 2.8V. Note, that by varying the soft start capacitor (Css), one can adjust the converter s startup time. 14

15 Figure 12. Startup at 24V Input 15

16 Shutdown Figure 13. Shutdown at 12V Input 16

17 Figure 14. Shutdown at 24V Input 17

18 Output Voltage Ripple Figure 15. 5V Output Ripple 18

19 Figure 16. 5V Output Ripple and High Frequency Noise 19

20 Figure V Output Ripple 20

21 Figure V Output Ripple and High Frequency Noise 21

22 Figure V Output Ripple 22

23 Figure V Output Ripple and High Frequency Noise 23

24 Load Transients Figure % to 100% Load Step on 5V Rail 24

25 Figure % to 100% Load Step on 3.3V Rail 25

26 Figure % to 100% Load Step on 1.8V Rail 26

27 Line Transients Figure 24. 9V to 15V Line Transient 27

28 Figure V to 28V Line Transient 28

29 Thermal Performance with Various Input Voltages and Loads Figure V Input, 2A on each rail (Max Load) 29

30 Figure V Input, 2A on each rail (Max Load) 30

31 Figure V Input, 1.5A on each rail (3/4 Load) 31

32 Figure V Input, 1.5A on each rail (3/4 Load) 32

33 Figure V Input, 1A on each rail (1/2 Load) 33

34 Figure V Input, 1A on each rail (1/2 Load) 34

35 Figure V Input, 0.5A on each rail (1/4 Load) 35

36 Figure V Input, 0.5A on each rail (1/4 Load) 36

37 IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers ( Buyers ) who are developing systems that incorporate TI semiconductor products (also referred to herein as components ). Buyer understands and agrees that Buyer remains responsible for using its independent analysis, evaluation and judgment in designing Buyer s systems and products. TI reference designs have been created using standard laboratory conditions and engineering practices. TI has not conducted any testing other than that specifically described in the published documentation for a particular reference design. TI may make corrections, enhancements, improvements and other changes to its reference designs. Buyers are authorized to use TI reference designs with the TI component(s) identified in each particular reference design and to modify the reference design in the development of their end products. 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