Large Scale Circuit Partitioning

Transcription

1 Large Scale Circuit Partitioning With Loose/Stable Net Removal And Signal Flow Based Clustering Jason Cong Honching Li Sung-Kyu Lim Dongmin Xu UCLA VLSI CAD Lab Toshiyuki Shibuya Fujitsu Lab, LTD Support : DARPA/ITO, NSF, Fujitsu MICRO

2 Outline Loose and Stable net Removal Partitioning Algorithm Maximum Fanout Free Subgraph Clustering Algorithm Performance of LSR/MFFS Conclusion & Ongoing Work

3 LSR Partitioning 1. Background 2. Motivation 3. Implementation

4 Circuit Partitioning Formulation minimize connection satisfy area constraint Significance fundamental for hierarchical layout essential for future technology Iterative Improvement Partitioning flexible, effective, and efficient

5 Evolution of IIP Algorithm Early Development KL : Kernighan & Lin [Bell70] FM : Fiduccia & Mattheyses [DAC82] LA : Krishnamurthy [TCom84] Recent Development CDIP/PROPf : Dutt & Deng [ICCAD96] Strawman : Hauck & Borriello [TCAD96] hmetis : Karypis & Kumar [DAC97] MLc : Alpert, Huang & Kahng [DAC97]

6 FM Algorithm Basics Basic Operation : Cell Move cost : gain (= reduction in cutsize) constraint : area balance cell status : free or locked Structure while (gain > 0) while ( free cell) move cell retrieve max-gain moves pass run

7 Loose-net Removal (LR) New Gain Formulation FREE net : only free cells block 0 block 1

8 Loose-net Removal (LR) New Gain Formulation LOOSE net : locked cells in one block block 0 block 1

9 Loose-net Removal (LR) New Gain Formulation FREE cells of LOOSE net FM : -3-2 block 0 block 1

10 Loose-net Removal (LR) New Gain Formulation IMMEDIATE ATTENTION, W > 0 LR : W W block 0 block 1

11 Loose-net Removal (LR) New Gain Formulation LR : W+W block 0 block 1

12 Loose-net Removal (LR) New Gain Formulation LOOSE net removed block 0 block 1

13 Loose-net Removal (LR) New Gain Formulation more LOOSE net formed block 0 block 1

14 Loose-net Removal (LR) New Gain Formulation Net Pulling Effect block 0 block 1

15 LR Implementation Gain Increase of LR favor shorter nets block 0 block 1

16 LR Implementation Gain Increase of LR incr(n) = k = 100 size(n) block 0 block 1

17 LR Implementation Gain Increase of LR : upper bound k Less Tie-Break

18 LR Implementation FM Enhancement while (gain > 0) while ( free cell) move max-gain cell c for (each loose net n incident on c) for (each free cell f of n) if (f.gain < T) f.gain += incr(n) retrieve max-gain moves

19 Performance of LR Bipartitioning without Clustering FM 1761 LA CDIP 1023 LR

20 Stable Net Transition (SNT) Stable Net [Shibuya et al, FSTJ95] remain cut during entire run limit FM solution Stable Net Removal at the end of each run detect stable net and isolate new initial partition fast convergence

21 Enhancement of LR Benefit of LR + SNT small loose + big stable net dynamic + static speedup LR How? initial partition by SNT for next run of LR Loose and Stable net Removal (LSR)

22 MFFS Clustering 1. Motivation 2. Algorithm 3. Speedup

23 Circuit Clustering Definition group closely connected component in circuits Significance reduce problem size speedup partitioning improve partitioning solution refinement through decomposition

24 Maximum Fanout Free Cone Significance [Cong & Ding, DAC93] exploit signal flow during clustering group logically dependant cells linear time complexity Benefit partitioning [Cong, Li, & Bagrodia DAC94] placement [Cong & Xu, ASP-DAC95]

25 Definition of MFFC Cone Rooted at v : Cv v and its predecessor s.t. if u in Cv, every path from u to v resides entirely in Cv Fanout Free Cone at v : FFCv Cv is fanout free if output(cv) = output(v) Maximum FFCv : MFFCv fanout free and maximum FFCv

26 Definition of MFFC Find All Single MFFC complexity : O( N + E )

27 Limitation of MFFC Designed for Combinational Circuit can t handle cycles in sequential circuit apply MFFC algorithm

28 Limitation of MFFC Designed for Combinational Circuit can t handle cycles in sequential circuit apply MFFS algorithm

29 Definition of MFFS For a node v in a sequential circuit; Fanout Free Subgraph rooted at v FFSv = {u every path from u to some PO passes through v } Maximum Fanout Free Subgraph rooted at v MFFSv = {u for all FFSv, u FFCv }

30 For Single MFFSv MFFS Construction

31 MFFS Construction For Single MFFSv select root node v and cut its fanout v

32 MFFS Construction For Single MFFSv mark nodes reachable backwards from PO v

33 MFFS Construction For Single MFFSv MFFSv = {unmarked nodes} v

34 MFFS Construction For Single MFFSv complexity : O( N + E ) v

35 MFFS Clustering For Clustering Entire Circuit

36 MFFS Clustering For Clustering Entire Circuit find MFFSv and remove v

37 MFFS Clustering For Clustering Entire Circuit find MFFSv and remove v

38 MFFS Clustering For Clustering Entire Circuit output to removed nodes is new PO v

39 MFFS Clustering For Clustering Entire Circuit repeat until all nodes are clustered v v

40 MFFS Clustering For Clustering Entire Circuit repeat until all nodes are clustered v v

41 MFFS Clustering For Clustering Entire Circuit repeat until all nodes are clustered v v v

42 MFFS Clustering For Clustering Entire Circuit repeat until all nodes are clustered v v v

43 MFFS Clustering For Clustering Entire Circuit complexity : O( N ( N + E ))

44 Speedup of MFFS Clustering Single MFFSv Construction slow : O( N + E ) v

45 Speedup of MFFS Clustering Subset of MFFSv search on subcircuit v

46 Speedup of MFFS Clustering Subset of MFFSv internal node : depth h-bfs at node v pseudo PI/PO : I/O to/from subcircuit pseudo PIs circuit SC (v, h) h pseudo POs v

47 LSR/MFFS Algorithm Overview cluster circuit with MFFS approximation algorithm partition clustered circuit with LSR algorithm decompose clusters completely refine cutline with LSR algorithm on declustered circuit

48 Experimental Result 1. Experiment Setting 2. MFFS Clustering 3. LSR/MFFS Partitioning

49 Experimental Setting Benchmark 16 MCNC circuits with signal flow info SPARC 5-85 with gcc v2.4 bipartitioning under 45-55% skew real cell area Area Variation Ratio = max cell area min cell area Metric cutsize : min of 20 runs runtime : total of 10 runs

50 MFFS Clustering Result Exact Approx ckt size AVR # clst time # clst time s sioo s s avq.sm S avq.lg Total

51 Cutsize Reduction Trend FM SNT LR LSR

52 Cutsize Reduction Trend FM SNT LR LSR

53 Cutsize Reduction Trend FM SNT LR LSR

54 Cutsize Reduction Trend FM SNT LR FLAT MFFS LSR LR, SNT, MFFS are all effective

55 Runtime Reduction Trend FM SNT LR LSR

56 Runtime Reduction Trend FM SNT LR LSR

57 Runtime Reduction Trend FM SNT LR LSR

58 Runtime Reduction Trend FM SNT LR FLAT MFFS LSR SNT and MFFS are both effective

59 Cutsizes Among IIPs CDIP 1023 PROPf 961 Strawman hmetis MLc LSR/MFFS achieved BEST cutsize

60 Runtimes Among IIPs CDIP PROPf Strawman hmetis 1388??? MLc 3455 LSR/MFFS achieved BEST runtime

61 Cutsizes Among Non-IIPs Paraboli 749 FBB 648 PANZA 516 LSR/MFFS achieved BEST cutsize

62 Runtimes Among Non-IIPs Paraboli FBB PANZA LSR/MFFS??? achieved BEST cutsize

63 Conclusion & Ongoing Work LSR Partitioning Loose and Stable net Removal MFFS Clustering Maximum Fanout Free Subgraph Performance of LSR/MFFS Ongoing Work LSR : multi-way partitioning MFFS : multi-level cluster hierarchy LSR/MFFS : mincut based placement

64 Thank You For Your Attention