Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

Transcription

1 Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization Kun Yuan, Jae-Seo Yang, David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at Austin Sponsored in Part by NSF, SRC, Sun, Qualcomm, and equipment donations from Intel 1

2 Outline Bacground and Motivation Simultaneous Conflict and Stitch Minimization Grid Model Basic ILP formulation Speed-Up techniques Experimental Result Conclusion 2

3 Lithography Challenges Aggressive scaling of min. printable half pitch HP HP = λ 1 NA 1: process difficulty NA: numerical aperture λ: wavelength of source NA = 1.8, close to the limit EUV(13.5nm) not available in near future 3

4 Double Patterning Lithography (DPL) Mas 1 4 Mas 2 Most liely lithography solution for 32nm and beyond A layout is decomposed into two mass (colors) The effective pitch is doubled Manufactured through 2x exposures/etches. Layout Decomposition. However, it is NOT a trivial tas

5 Layout Decomposition Challenges stitch conflict mincs mincs mincs Overlay conflict Redesign mincs Coloring Conflict: Two features within minimum coloring spacing should be colored different Splitting Stitch May resolve the conflict but cause yield loss due to overlay. 5

6 Existing Wor Heuristic approaches [Drapeau+, SPIE 2007] Greedy coloring and splitting in two stages ILP based layout decomposition [Kahng+, ICCAD 2008] Layout fracturing. Detect the uncolorable conflict cycle with odd number of nodes, and remove them by splitting the features ILP is then applied to minimize the number of stitches. 6

7 Motivation for Simultaneous Optimization Node Splitting 7 ILP formulation

8 Outline Bacground and Motivation Simultaneous Conflict and Stitch Minimization Grid Model Basic ILP formulation Speed-Up techniques Experimental Result Conclusion 8

9 Grid Model Map the layout into grids The size of each grids is half of the pitch of the original design Offer sufficient stitch candidates for large solution space Minimize the conflict and stitch between layout grids mincs mincs 9

10 Stitch Grid Pair (SGP) Adjacent grids A and B are assigned to different mass A B stitch 10

11 Conflict Grid Pair (CGP) Two grids within minimum coloring distance are assigned into the same mas Boundingbox-Connected (BB-connected) case should be excluded. A B A B A B CGP NOT CGP CGP 11

12 Basic ILP Formulation Coloring binary variable x i = 1 (Red), 0 (Blue) i is the unique id of each grid Objectives mincs Min si, j+ α cm, n si, j SP cm, n CP Binary variables s and c = 1 if there is a SGP and CGP respectively i,j m,n SP or CP are the set of the grid pairs which could form a SGP or CGP. 12

13 Detect SGP Logic equations x i = 1 (Red), 0 (Blue) xx a b a, b xx = 1 s = 1 = 1 s = 1 a b a, b A B Linear Constraints x + (1 x ) 1+ s a b a, b (1 x ) + x 1+ s a b a, b 13

14 Detect CGP Logic equations xx a b = 1 && No RED BB-connected c = 1 xx a b ab, = 1 && No BLUE BB-connected c = 1 ab, x i = 1 (Red), 0 (Blue) A B C D Linear Constraints x + x 1+ c + r a b ab, ab, (1 x ) + (1 x ) 1+ c + b Binary variables r ab ab,, and = 1 b ab, = 1 if if there is is BB-connected in in RED and BLUE respectively : The set of of possible BB-connected paths. a b a, b a, b 14 1 r ab, : Grids C and D are Red 1 b ab, : Grids C and D are Blue

15 Detect BB-connected case Logic Equation x i = 1 (Red), 0 (Blue) r pq, uv x e, f eg r = e, f Ppq, uv 1.. ab, = xx c d x A B C D Linear Constraints x x e, f Ppq, uv e, f Ppq, uv n pq, uv ( 1) x n + r e, f pq, uv pq, uv ( ) (1 x ) n 1 r e, f pq, uv pq, uv is the number of grids in the path eg.. ( 2 1) x + x + r 1 c d a, b ( ) ( 1 ), (1 x ) + 1 x 2 1 r c d a b 15

16 Speed-Up Techniques: Independent Component Computation Independent Components: Isolated layout clusters without possible SGP and CGPs between them. They can be solved individually, and the solution can be simply merged without losing optimality in terms of ILP objectives. 16

17 Speedup Techniques: Layout Partition There could still be large design which has prohibitive problem size even after independent component computation We can apply min-cut partition to divide a large components to several small connected ones 17

18 Coloring Flipping for Layout Partition CGP B B A C A C SGP We can flip the coloring of certain partition to obtain better resolution across the boundaries 18

19 ILP Formulation for Coloring Flipping Binary Variable f i = 0 (Not flipped), 1 (Flipped) for partition i B f f i, j i, j = = 0 if both i and j flip or do not flip 1 if only one of i and j flips A C Objective min ( f ( s + αc ) + (1 f )( s + αc )) s e0/ e1 e0/ e1 i, j i, j e0 e0 e1 e1 i, j i, j i, j i, j i, j i, j and c are the stitch and conflict crossing the boundary Constraints f = ff + ff i, j i j i j 19

20 Experimental Setup Implement in C++. Comparative two-phase approach First Phase:» Color all the layout polygons sequentially.» Assign colors to minimize current conflicts. Second Phase:» Detect the coloring conflict segments» Flip the coloring these segments to resolve the conflicts. 20

21 Benchmar Eight scaled testcases 2 Circuit Area( ) Grid size Layout grids μm c x c x c x c x c x c x c x c x

22 Coloring Conflict and Splitting Stitch 8x reduction on coloring conflict 33% less stitches 22

23 Scalability The runtime is in reasonable scope our algorithm linear fitting Runtime The complexity shows linearity with number of occupied grids in test cases x 10 4 #occupied grid 23

24 Conclusion Double patterning layout decomposition for simultaneous conflict and stitch minimization Grid model, integer linear programming, Independent component computation, layout partition Explore DPL-friendly design methodology DPL-aware detailed routing with redundant via consideration. DPL-aware standard cell design. Special thans to Dr. Minsi Cho at IBM research 24

25 BacUp 25

26 Coloring Flipping 70% less conflicts 40% less stitches 26

27 ILP Constraints for Coloring Flipping Logic equations f = ff + ff i, j i j i j B Linear Constraints A C ff f f+ f 1 + f i j i, j i j i, j f f f (1 f ) + (1 f ) 1+ f i j i, j i j i, j f f f f + (1 f ) 1 + (1 f ) j i, j i j i, j f f f (1 f ) + f 1 + (1 f ) i j i, j i j i, j 27