An Esterel Virtual Machine

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1 An Esterel Virtual Machine Stephen A. Edwards Columbia University Octopi Workshop Chalmers University of Technology Gothenburg, Sweden December 28

2 An Esterel Virtual Machine Goal: Run big Esterel programs in memory constrained settings. Our target: the Hitachi H8 based RCX Microcontroller for Lego Mindstorms [SLAP 26]

3 An Example s s s= s= S s3 P s3 ÑÓ ÙÐ Ü ÑÔÐ ÒÔÙØ Á Ë ÓÙØÔÙØ Ç Ò Ð Ê Ò Ú ÖÝ Ë Ó Û Ø Á Û ÓÖØ Ù Ø Ò Ê Û Ò ÑÑ Ø Ñ Ø Ç ÐÓÓÔ Ô Ù Ô Ù ÔÖ ÒØ Ê Ø Ò Ñ Ø Ò ÔÖ ÒØ Ò ÐÓÓÔ Ò Ú ÖÝ Ò Ò Ð Ò ÑÓ ÙÐ * s6 2 * s s6 s3= s3= s6=2 s6= A P R s6 s6= s6= s3= s6= s6 s6= R s3= I s A 3 3 O P s6= P s= P s= s= s= A s6=2 R

4 Challenges Esterel s semantics require any implementation to deal with three issues: Concurrent execution of sequential threads of control within a cycle The scheduling constraints among these threads due to communication dependencies How control state is updated between cycles

5 How did we handle them? A virtual machine specifically designed to support Esterel features A sequentializing algorithm Conversion from GRC to BAL and then to a compact byte code

6 Phase : Schedule Schedule 2 3 4

7 Phase 2: Assign Threads Assign Threads

8 Phase 3: Sequentialize Sequentialize

9 Phase 4: Add Labels case Add Labels jmp done done 4 4

10 Phase 5: Convert to BAL 2 jmp done 3 case done Convert to BAL Ø¼ ËÌÀÊ ½ Ø½ ÅÌ ½ ËÏ ½ ËÌÀÊ ½ ÆÊ½ Æ ÆÊ½ ËÏ Í Ø½ ÌÏ ¾ ¾ ½ ÂÅÈ ÓÒ ½ ÓÒ ËÏ ¼ 4

11 Phase 6: Convert to Byte Code Ø¼ ËÌÀÊ ½ Ø½ ÅÌ ½ ËÏ ½ ËÌÀÊ ½ ÆÊ½ Æ Convert to byte code ¼ ¼½ ¼¼ ¼ ¼ ¼½ ¼ ¼½ ¼ ¼½ ¼¼ ¼ ¼ ÆÊ½ ËÏ Í Ø½ ÌÏ ¾ ¾ ½ ÂÅÈ ÓÒ ½ ÓÒ ËÏ ¼ ¼ ¼¾ ¼¼ ½ ¼ ¼¼ ½ ¼ ¼¼

12 Sequential Code Generation. Schedule the nodes in the graph 2. Assign thread numbers 3. Sequentialize the graph 4. Set the execution path by adding labels 5. Convert to BAL 6. Assemble to produce bytecode

13 Sequentialization

14 Sequentialization F 2 3 The dotted line labeled F represents the frontier. The frontier starts at the top of the graph. 4

15 Sequentialization F 2 3 The frontier moves down a node at a time in scheduledorder. 4

16 Sequentialization F 2 3 When a node is in the same thread as the most recently moved one, it is simply moved above the frontier. 4

17 Sequentialization F 2 3 However, when the next node is from a different thread, a switch is added to the previous thread and an active point is added to the new thread just above the just moved node. 4

18 Sequentialization 2 3 The algorithm is complete when the frontier has swept across all nodes in scheduled order. F 4

19 Sequentializing Algorithm : for each thread t in G do 2: create new active point p 3: copy first node n of t in G to n new node in G 4: connect p and n 5: add p to P[t ] and add n to A[t ] 6: t = the first thread 7: for each node n in scheduled order do 8: t is thread of n 9: if t t then : for each parent p in P[t ] do : for each successor c of p in A[t ] do 2: create switch node s from t to t and connect s between p and c 3: replace P[t ] with the set of new switch nodes 4: move n to P[t ] and remove it from A[t ] 5: for each unreached successor c of n do 6: copy c to c new node in G 7: if n is a fork then 8: add child to A[thread of c] 9: else 2: add child to A[t ] 2: t = t {remember the last thread}

20 Why VM? Goal: constrained memory environment Instruction set has direct support for Esterel constructs like concurrency, preemption, and signals E.g., a context switch can be specified in just two bytes

21 VM Details

22 VM Details Signal status registers Completion code registers Per thread program counters Inter instant state holding registers

23 VM: Signal, State, and Thread Opcode Description Encoding EMT Emit a Signal 4 RR SSIG Clear Signal A RR SSTT Set State B RR VV STHR Set Thread 7 TT HH LL

24 VM: Control Flow Instructions Opcode Description Encoding END Tick End 3 JMP Jump 6 HH LL NOP No Operation

25 VM: Branch, Switch, Terminate Opcode Description Encoding MWB Multiway Branch (State) 2D NL RR HH2 LL2... Multiway Branch (Comp.) 4D NL RR HH2 LL2... Two Way Branch (State) 29 RR HH LL TWB Two Way Branch (Signal) 49 RR HH LL Two Way Branch (Comp.) 69 RR HH LL SWC Switch Thread 5 TT SWCU Switch Unknown C TRM Set Completion Code 8 RR VV for Join

26 VM: Context Switch ººº Û Ø ÓÔÓ ² ¼Ü½ µß ººº ËÏ»» ÁÒÖ Ñ ÒØ Ø ÔÖÓ Ö Ñ ÓÙÒØ Ö Ô»» ËØÓÖ Ø ÙÖÖ ÒØ Ø Ö Ø Ð Ø Ø Ö Ð Ø Ø Ö ÙÖÖ ÒØ Ø Ö»» Ø Ø Ò ÜØ Ø Ö ÙÖÖ ÒØ Ø Ö Ô»» ÁÒÖ Ñ ÒØ Ø ÔÖÓ Ö Ñ ÓÙÒØ Ö Ô»» ËØÓÖ ÓÐ Ô Ó Ø Û Ø Ø ÓÐ Ø Ö Ø Ö Ð Ø Ø Ö Ô»» ÄÓ Ø Ô Ó Ø Û Ø Ø Ò Û Ø Ö Ô Ø Ö ÙÖÖ ÒØ Ø Ö Ö ººº

27 VM: Switch Unknown ººº ËÏ Í»» Å Ø Ø Ö ØÓÖ Ò Ð Ø Ø Ö Ø ÙÖÖ ÒØ Ø Ö Ø ÑÔ ÙÖÖ ÒØ Ø Ö ÙÖÖ ÒØ Ø Ö Ð Ø Ø Ö Ð Ø Ø Ö Ø ÑÔ»» ËØÓÖ ÓÐ Ô Ø Ö Ð Ø Ø Ö Ô»» ÄÓ Ò Û Ô Ô Ø Ö ÙÖÖ ÒØ Ø Ö Ö ººº

28 VM in action

29 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = last_thread = Threads Signals States Joins....

30 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 4 last_thread = Threads Signals 6 States Joins....

31 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 6 last_thread = Threads Signals 6 States Joins....

32 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 6 last_thread = Threads Signals 8 6 States Joins....

33 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 9 last_thread = Threads Signals 8 6 States Joins....

34 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 22 last_thread = Threads Signals 8 6 States Joins....

35 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 8 last_thread = Threads Signals 8 24 States Joins....

36 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 2 last_thread = Threads Signals 8 5 States Joins....

37 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 5 last_thread = Threads Signals 4 5 States Joins....

38 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 4 last_thread = Threads Signals 4 5 States Joins....

39 VM in action Ø¼ ¼¼ ËÌÀÊ ½ Ø½ ¼ ÅÌ ½ ¼ ËÏ ½ ¼ ËÌÀÊ ½ ÆÊ½ ½¾ ËÏ ½ ½ Æ ÆÊ½ ½ ËÏ Í Ø½ ½ ÌÏ ¾ ½ ½ ½ ÂÅÈ ÓÒ ½ ÓÒ ¾¾ ËÏ ¼ pc = 5 last_thread = Threads Signals 5 5 States Joins....

40 The engineering details brickos 2.6. on Redhat Linux gcc cross compiler for H83 Download lx files to the lego RCX via USB IR tower

41 Code Sizes Example BAL x86 H8 dacexample % % abcd % % greycounter % % tcint % 74 5% atds % % BAL: the size of our bytecode (in bytes) x86: the size of optimized C code for an x86 H8: the size of optimized C code for an Hitachi H8 Percentages represent the size savings of using bytecode.

42 Execution Times Example x86 BAL dacexample.6µs.µs 8 tcint.28µs.µs 4 atds.2µs.4µs 7

43 Conclusions Simple Virtual Machine Compilation scheme statically schedules the concurrent behavior and generates straight line code for each thread VM supports context switching well Bytecode for our virtual machine is roughly half the size of optimized native assembly code generated from C Speed tradeoff not that bad! Between 4 and 7 times slower than optimized C code

An Esterel Virtual Machine for Embedded Systems

SLA 6 An Esterel Virtual Machine for Embedded Systems Becky lummer Department of Computer Science Columbia University New York, USA Mukul Khajanchi Department of Computer Science Columbia University New